• S
    arm64: Fix mismatched cache line size detection · 4c4a39dd
    Suzuki K Poulose 提交于
    If there is a mismatch in the I/D min line size, we must
    always use the system wide safe value both in applications
    and in the kernel, while performing cache operations. However,
    we have been checking more bits than just the min line sizes,
    which triggers false negatives. We may need to trap the user
    accesses in such cases, but not necessarily patch the kernel.
    
    This patch fixes the check to do the right thing as advertised.
    A new capability will be added to check mismatches in other
    fields and ensure we trap the CTR accesses.
    
    Fixes: be68a8aa ("arm64: cpufeature: Fix CTR_EL0 field definitions")
    Cc: <stable@vger.kernel.org>
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Reported-by: NWill Deacon <will.deacon@arm.com>
    Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
    Signed-off-by: NWill Deacon <will.deacon@arm.com>
    4c4a39dd
cpu_errata.c 16.8 KB