Provide simplified models for the necessary clocks on the zynq-7000
platform.  Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.

OF bindings are also provided and documented.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>