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    x86, cpu: Fix cache topology for early P4-SMT · 2a226155
    Peter Zijlstra 提交于
    P4 systems with cpuid level < 4 can have SMT, but the cache topology
    description available (cpuid2) does not include SMP information.
    
    Now we know that SMT shares all cache levels, and therefore we can
    mark all available cache levels as shared.
    
    We do this by setting cpu_llc_id to ->phys_proc_id, since that's
    the same for each SMT thread. We can do this unconditional since if
    there's no SMT its still true, the one CPU shares cache with only
    itself.
    
    This fixes a problem where such CPUs report an incorrect LLC CPU mask.
    
    This in turn fixes a crash in the scheduler where the topology was
    build wrong, it assumes the LLC mask to include at least the SMT CPUs.
    
    Cc: Josh Boyer <jwboyer@redhat.com>
    Cc: Dietmar Eggemann <dietmar.eggemann@arm.com>
    Tested-by: NBruno Wolff III <bruno@wolff.to>
    Signed-off-by: NPeter Zijlstra <peterz@infradead.org>
    Link: http://lkml.kernel.org/r/20140722133514.GM12054@laptop.lanSigned-off-by: NH. Peter Anvin <hpa@zytor.com>
    2a226155
intel_cacheinfo.c 33.0 KB