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由 Stefan Agner 提交于
Extend the clock control for FlexCAN with the second gate which enable the clocks in the Clock Divider (CCM_CSCDR2) register too. Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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