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    ALSA: hda - add AZX_DCAPS_I915_POWERWELL to Baytrail · 40cc2392
    Mengdong Lin 提交于
    This patch addes AZX_DCAPS_I915_POWERWELL to BYT (Baytrail).
    
    Like Braswell and Skylake, the HDMI codec on Bytrail is also in the shared
    power well with GPU. This power well must be turned on before we reset link
    to probe the codec, to avoid communication failure with the codec.
    
    The side effect is that this power is always ON in S0 because the BYT HDMI
    codec does not support EPSS or D3ClkStop and so the controller doesn't enter
    D3 at runtime, and the HDMI codec and analog codec share a single physical
    HD-A link and so we cannot reset the HD-A link freely when we re-enable the
    power to use the HDMI codec.
    
    Next step is to test if an AGP reset or double AGP reset on BYT HDMI codec is
    okay to bring the HDMI codec back to a functional state after restoring the
    power. If okay, we can bind the power on/off with the HDMI codec PM without
    interrupting the analog audio.
    Signed-off-by: NMengdong Lin <mengdong.lin@intel.com>
    Signed-off-by: NTakashi Iwai <tiwai@suse.de>
    40cc2392
hda_intel.c 58.9 KB