source clock need an independent cg to control, when doing clk mode
switch, need gate source clock to avoid hw issue(multi-bit sync hw hang)
Signed-off-by: NChaotian Jing <chaotian.jing@mediatek.com>
Tested-by: NSean Wang <sean.wang@mediatek.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>