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    x86: Skip verification by the watchdog for TSC clocksource. · 395628ef
    Alok Kataria 提交于
    Impact: Changes timekeeping on Vmware (or with tsc=reliable).
    
    This is achieved by resetting the CLOCKSOURCE_MUST_VERIFY flag.
    
    We add a tsc=reliable commandline option to enable this.
    This enables legacy hardware without HPET, LAPIC, or ACPI timers
    to enter high-resolution timer mode.
    
    Along with that have extended this to be used in virtualization environement
    too. Now we also set this flag if the X86_FEATURE_TSC_RELIABLE bit is set.
    
    This is important since there is a wrap-around problem with the acpi_pm timer.
    The acpi_pm counter is just 24bits and this can overflow in ~4 seconds. With
    the NO_HZ kernels in virtualized environment, there can be situations when
    the guest is descheduled for longer duration, as a result we may miss the wrap
    of the acpi counter. When TSC is used as a clocksource and acpi_pm timer is
    being used as the watchdog clocksource this error in acpi_pm results in TSC
    being marked as unstable, and essentially results in time dropping in chunks
    of 4 seconds whenever this wrap is missed. Since the virtualized TSC is
    reliable on VMware, we should always use the TSCs clocksource on VMware, so
    we skip the verfication at runtime, by checking for the feature bit.
    
    Since we reset the flag for mgeode systems too, i have combined
    the mgeode case with the feature bit check.
    Signed-off-by: NJeff Hansen <jhansen@cardaccess-inc.com>
    Signed-off-by: NAlok N Kataria <akataria@vmware.com>
    Signed-off-by: NDan Hecht <dhecht@vmware.com>
    Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
    395628ef
tsc.c 21.9 KB