• P
    MIPS: pm-cps: add PM state entry code for CPS systems · 3179d37e
    Paul Burton 提交于
    This patch adds code to generate entry & exit code for various low power
    states available on systems based around the MIPS Coherent Processing
    System architecture (ie. those with a Coherence Manager, Global
    Interrupt Controller & for >=CM2 a Cluster Power Controller). States
    supported are:
    
      - Non-coherent wait. This state first leaves the coherent domain and
        then executes a regular MIPS wait instruction. Power savings are
        found from the elimination of coherency interventions between the
        core and any other coherent requestors in the system.
    
      - Clock gated. This state leaves the coherent domain and then gates
        the clock input to the core. This removes all dynamic power from the
        core but leaves the core at the mercy of another to restart its
        clock. Register state is preserved, but the core can not service
        interrupts whilst its clock is gated.
    
      - Power gated. This deepest state removes all power input to the core.
        All register state is lost and the core will restart execution from
        its BEV when another core powers it back up. Because register state
        is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
        implementation in order for the core to exit the state successfully.
    
    The code will detect which states are available on the current system
    during boot & generate the entry/exit code for those states. This will
    be used by cpuidle & hotplug implementations.
    Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
    3179d37e
smp-cps.h 1.0 KB