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    i2c: rk3x: Account for repeated start time requirement · 387f0de6
    Doug Anderson 提交于
    On Rockchip I2C the controller drops SDA low slightly too soon to meet
    the "repeated start" requirements.
    
    >From my own experimentation over a number of rates:
     - controller appears to drop SDA at .875x (7/8) programmed clk high.
     - controller appears to keep SCL high for 2x programmed clk high.
    
    The first rule isn't enough to meet tSU;STA requirements in
    Standard-mode on the system I tested on.  The second rule is probably
    enough to meet tHD;STA requirements in nearly all cases (especially
    after accounting for the first), but it doesn't hurt to account for it
    anyway just in case.
    
    Even though the repeated start requirement only need to be accounted
    for during a small part of the transfer, we'll adjust the timings for
    the whole transfer to meet it.  I believe that adjusting the timings
    in just the right place to switch things up for repeated start would
    require several extra interrupts and that doesn't seem terribly worth
    it.
    
    With this change and worst case rise/fall times, I see 100kHz i2c
    going to ~85kHz.  With slightly optimized rise/fall (800ns / 50ns) I
    see i2c going to ~89kHz.  Fast-mode isn't affected much because
    tSU;STA is shorter relative to tHD;STA there.
    
    As part of this change we needed to account for the SDA falling time.
    The specification indicates that this should be the same, but we'll
    follow Designware's lead and add a binding.  Note that we deviate from
    Designware and assign the default SDA falling time to be the same as
    the SCL falling time, which is incredibly likely.
    Signed-off-by: NDoug Anderson <dianders@chromium.org>
    [wsa: rebased to i2c/for-next]
    Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
    387f0de6
i2c-rk3x.c 26.3 KB