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由 Sakari Ailus 提交于
The clock lane is the first lane in the lane_polarities array. Reflect this consistently by putting the number of data lanes after the number of clock lanes. Fixes: 4ee23621 ("media: v4l2-fwnode: suppress a warning at OF parsing logic") Signed-off-by: NSakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>
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