• F
    r8169: RxFIFO overflow oddities with 8168 chipsets. · 1519e57f
    Francois Romieu 提交于
    Some experiment-based action to prevent my 8168 chipsets locking-up hard
    in the irq handler under load (pktgen ~1Mpps). Apparently a reset is not
    always mandatory (is it at all ?).
    
    - RTL_GIGA_MAC_VER_12
    - RTL_GIGA_MAC_VER_25
      Missed ~55% packets. Note:
      - this is an old SiS 965L motherboard
      - the 8168 chipset emits (lots of) control frames towards the sender
    
    - RTL_GIGA_MAC_VER_26
      The chipset does not go into a frenzy of mac control pause when it
      crashes yet but it can still be crashed. It needs more work.
    Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
    Cc: Ivan Vecera <ivecera@redhat.com>
    Cc: Hayes <hayeswang@realtek.com>
    1519e57f
r8169.c 119.7 KB