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    mlx4/mlx5: Use dma_wmb/rmb where appropriate · 12b3375f
    Alexander Duyck 提交于
    This patch should help to improve the performance of the mlx4 and mlx5 on a
    number of architectures.  For example, on x86 the dma_wmb/rmb equates out
    to a barrer() call as the architecture is already strong ordered, and on
    PowerPC the call works out to a lwsync which is significantly less expensive
    than the sync call that was being used for wmb.
    
    I placed the new barriers between any spots that seemed to be trying to
    order memory/memory reads or writes, if there are any spots that involved
    MMIO I left the existing wmb in place as the new barriers cannot order
    transactions between coherent and non-coherent memories.
    
    v2: Reduced the replacments to just the spots where I could clearly
        identify the usage pattern.
    
    Cc: Amir Vadai <amirv@mellanox.com>
    Cc: Ido Shamay <idos@mellanox.com>
    Cc: Eli Cohen <eli@mellanox.com>
    Signed-off-by: NAlexander Duyck <alexander.h.duyck@redhat.com>
    Signed-off-by: NDavid S. Miller <davem@davemloft.net>
    12b3375f
en_tx.c 27.6 KB