Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.
Signed-off-by: NMike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: NMark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org