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    parisc: Fix ordering of cache and TLB flushes · 0adb24e0
    John David Anglin 提交于
    The change to flush_kernel_vmap_range() wasn't sufficient to avoid the
    SMP stalls.  The problem is some drivers call these routines with
    interrupts disabled.  Interrupts need to be enabled for flush_tlb_all()
    and flush_cache_all() to work.  This version adds checks to ensure
    interrupts are not disabled before calling routines that need IPI
    interrupts.  When interrupts are disabled, we now drop into slower code.
    
    The attached change fixes the ordering of cache and TLB flushes in
    several cases.  When we flush the cache using the existing PTE/TLB
    entries, we need to flush the TLB after doing the cache flush.  We don't
    need to do this when we flush the entire instruction and data caches as
    these flushes don't use the existing TLB entries.  The same is true for
    tmpalias region flushes.
    
    The flush_kernel_vmap_range() and invalidate_kernel_vmap_range()
    routines have been updated.
    
    Secondly, we added a new purge_kernel_dcache_range_asm() routine to
    pacache.S and use it in invalidate_kernel_vmap_range().  Nominally,
    purges are faster than flushes as the cache lines don't have to be
    written back to memory.
    
    Hopefully, this is sufficient to resolve the remaining problems due to
    cache speculation.  So far, testing indicates that this is the case.  I
    did work up a patch using tmpalias flushes, but there is a performance
    hit because we need the physical address for each page, and we also need
    to sequence access to the tmpalias flush code.  This increases the
    probability of stalls.
    
    Signed-off-by: John David Anglin <dave.anglin@bell.net>
    Cc: stable@vger.kernel.org # 4.9+
    Signed-off-by: NHelge Deller <deller@gmx.de>
    0adb24e0
cacheflush.h 4.1 KB