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    [MIPS] Malta: Fix reading the PCI clock frequency on big-endian · 0487de91
    Dmitri Vorobiev 提交于
    The JMPRS register on Malta boards keeps a 32-bit CPU-endian
    value. The readw() function assumes that the value it reads is a
    little-endian 16-bit number. Therefore, using readw() to obtain
    the value of the JMPRS register is a mistake. This error leads
    to incorrect reading of the PCI clock frequency on big-endian
    during board start-up.
    
    Change readw() to __raw_readl().
    
    This was tested by injecting a call to printk() and verifying
    that the value of the jmpr variable was consistent with current
    setting of the JP4 "PCI CLK" jumper.
    Signed-off-by: NDmitri Vorobiev <dmitri.vorobiev@gmail.com>
    Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    0487de91
malta_setup.c 5.3 KB