sh_eth.c 61.1 KB
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/*
 *  SuperH Ethernet device driver
 *
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 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
 *  Copyright (C) 2008-2012 Renesas Solutions Corp.
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 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc.,
 *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

#include <linux/init.h>
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#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/mdio-bitbang.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <linux/cache.h>
#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/clk.h>
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#include <linux/sh_eth.h>
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#include "sh_eth.h"

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#define SH_ETH_DEF_MSG_ENABLE \
		(NETIF_MSG_LINK	| \
		NETIF_MSG_TIMER	| \
		NETIF_MSG_RX_ERR| \
		NETIF_MSG_TX_ERR)

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#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
	defined(CONFIG_CPU_SUBTYPE_SH7763) || \
	defined(CONFIG_ARCH_R8A7740)
static void sh_eth_select_mii(struct net_device *ndev)
{
	u32 value = 0x0;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->phy_interface) {
	case PHY_INTERFACE_MODE_GMII:
		value = 0x2;
		break;
	case PHY_INTERFACE_MODE_MII:
		value = 0x1;
		break;
	case PHY_INTERFACE_MODE_RMII:
		value = 0x0;
		break;
	default:
		pr_warn("PHY interface mode was not setup. Set to MII.\n");
		value = 0x1;
		break;
	}

	sh_eth_write(ndev, value, RMII_MII);
}
#endif

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/* There is CPU dependent code */
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#if defined(CONFIG_CPU_SUBTYPE_SH7724) || defined(CONFIG_ARCH_R8A7779)
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#define SH_ETH_RESET_DEFAULT	1
static void sh_eth_set_duplex(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

static void sh_eth_set_rate(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
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	unsigned int bits = ECMR_RTM;

#if defined(CONFIG_ARCH_R8A7779)
	bits |= ECMR_ELB;
#endif
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	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~bits, ECMR);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | bits, ECMR);
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		break;
	default:
		break;
	}
}

/* SH7724 */
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate,

	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
			  EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
	.tx_error_check	= EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
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	.rpadir		= 1,
	.rpadir_value	= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
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};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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#define SH_ETH_HAS_BOTH_MODULES	1
#define SH_ETH_HAS_TSU	1
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static int sh_eth_check_reset(struct net_device *ndev);

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static void sh_eth_set_duplex(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

static void sh_eth_set_rate(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, 0, RTRATE);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, 1, RTRATE);
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		break;
	default:
		break;
	}
}

/* SH7757 */
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.set_duplex		= sh_eth_set_duplex,
	.set_rate		= sh_eth_set_rate,

	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
	.rmcr_value	= 0x00000001,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
			  EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
	.tx_error_check	= EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.no_ade		= 1,
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	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
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};
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#define SH_GIGA_ETH_BASE	0xfee00000
#define GIGA_MALR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
#define GIGA_MAHR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
static void sh_eth_chip_reset_giga(struct net_device *ndev)
{
	int i;
	unsigned long mahr[2], malr[2];

	/* save MAHR and MALR */
	for (i = 0; i < 2; i++) {
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		malr[i] = ioread32((void *)GIGA_MALR(i));
		mahr[i] = ioread32((void *)GIGA_MAHR(i));
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	}

	/* reset device */
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	iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
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	mdelay(1);

	/* restore MAHR and MALR */
	for (i = 0; i < 2; i++) {
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		iowrite32(malr[i], (void *)GIGA_MALR(i));
		iowrite32(mahr[i], (void *)GIGA_MAHR(i));
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	}
}

static int sh_eth_is_gether(struct sh_eth_private *mdp);
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static int sh_eth_reset(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);
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	int ret = 0;
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	if (sh_eth_is_gether(mdp)) {
		sh_eth_write(ndev, 0x03, EDSR);
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
				EDMR);
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		ret = sh_eth_check_reset(ndev);
		if (ret)
			goto out;
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		/* Table Init */
		sh_eth_write(ndev, 0x0, TDLAR);
		sh_eth_write(ndev, 0x0, TDFAR);
		sh_eth_write(ndev, 0x0, TDFXR);
		sh_eth_write(ndev, 0x0, TDFFR);
		sh_eth_write(ndev, 0x0, RDLAR);
		sh_eth_write(ndev, 0x0, RDFAR);
		sh_eth_write(ndev, 0x0, RDFXR);
		sh_eth_write(ndev, 0x0, RDFFR);
	} else {
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
				EDMR);
		mdelay(3);
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
				EDMR);
	}
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out:
	return ret;
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}

static void sh_eth_set_duplex_giga(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
	else		/* Half */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
}

static void sh_eth_set_rate_giga(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, 0x00000000, GECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, 0x00000010, GECMR);
		break;
	case 1000: /* 1000BASE */
		sh_eth_write(ndev, 0x00000020, GECMR);
		break;
	default:
		break;
	}
}

/* SH7757(GETHERC) */
static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
	.chip_reset	= sh_eth_chip_reset_giga,
	.set_duplex	= sh_eth_set_duplex_giga,
	.set_rate	= sh_eth_set_rate_giga,

	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
			  EESR_ECI,
	.tx_error_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
			  EESR_TFE,
	.fdr_value	= 0x0000072f,
	.rmcr_value	= 0x00000001,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
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	.tsu		= 1,
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};

static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
{
	if (sh_eth_is_gether(mdp))
		return &sh_eth_my_cpu_data_giga;
	else
		return &sh_eth_my_cpu_data;
}

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#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
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#define SH_ETH_HAS_TSU	1
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static int sh_eth_check_reset(struct net_device *ndev);
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static void sh_eth_reset_hw_crc(struct net_device *ndev);
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static void sh_eth_chip_reset(struct net_device *ndev)
{
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	struct sh_eth_private *mdp = netdev_priv(ndev);

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	/* reset device */
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	sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
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	mdelay(1);
}

static void sh_eth_set_duplex(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

static void sh_eth_set_rate(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, GECMR_10, GECMR);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, GECMR_100, GECMR);
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		break;
	case 1000: /* 1000BASE */
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		sh_eth_write(ndev, GECMR_1000, GECMR);
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		break;
	default:
		break;
	}
}

/* sh7763 */
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate,

	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
			  EESR_ECI,
	.tx_error_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
			  EESR_TFE,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
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	.tsu		= 1,
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#if defined(CONFIG_CPU_SUBTYPE_SH7734)
	.hw_crc     = 1,
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	.select_mii = 1,
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#endif
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};

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static int sh_eth_reset(struct net_device *ndev)
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{
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	int ret = 0;
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	sh_eth_write(ndev, EDSR_ENALL, EDSR);
	sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
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	ret = sh_eth_check_reset(ndev);
	if (ret)
		goto out;
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	/* Table Init */
	sh_eth_write(ndev, 0x0, TDLAR);
	sh_eth_write(ndev, 0x0, TDFAR);
	sh_eth_write(ndev, 0x0, TDFXR);
	sh_eth_write(ndev, 0x0, TDFFR);
	sh_eth_write(ndev, 0x0, RDLAR);
	sh_eth_write(ndev, 0x0, RDFAR);
	sh_eth_write(ndev, 0x0, RDFXR);
	sh_eth_write(ndev, 0x0, RDFFR);

	/* Reset HW CRC register */
	sh_eth_reset_hw_crc(ndev);

	/* Select MII mode */
	if (sh_eth_my_cpu_data.select_mii)
		sh_eth_select_mii(ndev);
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out:
	return ret;
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}

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static void sh_eth_reset_hw_crc(struct net_device *ndev)
{
	if (sh_eth_my_cpu_data.hw_crc)
		sh_eth_write(ndev, 0x0, CSMR);
}

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#elif defined(CONFIG_ARCH_R8A7740)
#define SH_ETH_HAS_TSU	1
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static int sh_eth_check_reset(struct net_device *ndev);

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static void sh_eth_chip_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* reset device */
	sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
	mdelay(1);

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	sh_eth_select_mii(ndev);
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}

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static int sh_eth_reset(struct net_device *ndev)
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{
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	int ret = 0;
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	sh_eth_write(ndev, EDSR_ENALL, EDSR);
	sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
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	ret = sh_eth_check_reset(ndev);
	if (ret)
		goto out;
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	/* Table Init */
	sh_eth_write(ndev, 0x0, TDLAR);
	sh_eth_write(ndev, 0x0, TDFAR);
	sh_eth_write(ndev, 0x0, TDFXR);
	sh_eth_write(ndev, 0x0, TDFFR);
	sh_eth_write(ndev, 0x0, RDLAR);
	sh_eth_write(ndev, 0x0, RDFAR);
	sh_eth_write(ndev, 0x0, RDFXR);
	sh_eth_write(ndev, 0x0, RDFFR);
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out:
	return ret;
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}

static void sh_eth_set_duplex(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
	else		/* Half */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
}

static void sh_eth_set_rate(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, GECMR_10, GECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, GECMR_100, GECMR);
		break;
	case 1000: /* 1000BASE */
		sh_eth_write(ndev, GECMR_1000, GECMR);
		break;
	default:
		break;
	}
}

/* R8A7740 */
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate,

	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
			  EESR_ECI,
	.tx_error_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
			  EESR_TFE,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
	.tsu		= 1,
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	.select_mii	= 1,
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};

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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
#define SH_ETH_RESET_DEFAULT	1
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
#define SH_ETH_RESET_DEFAULT	1
#define SH_ETH_HAS_TSU	1
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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	.tsu		= 1,
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};
#endif

static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
{
	if (!cd->ecsr_value)
		cd->ecsr_value = DEFAULT_ECSR_INIT;

	if (!cd->ecsipr_value)
		cd->ecsipr_value = DEFAULT_ECSIPR_INIT;

	if (!cd->fcftr_value)
		cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
				  DEFAULT_FIFO_F_D_RFD;

	if (!cd->fdr_value)
		cd->fdr_value = DEFAULT_FDR_INIT;

	if (!cd->rmcr_value)
		cd->rmcr_value = DEFAULT_RMCR_VALUE;

	if (!cd->tx_check)
		cd->tx_check = DEFAULT_TX_CHECK;

	if (!cd->eesr_err_check)
		cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;

	if (!cd->tx_error_check)
		cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
}

#if defined(SH_ETH_RESET_DEFAULT)
/* Chip Reset */
574
static int  sh_eth_reset(struct net_device *ndev)
575
{
576
	sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
577
	mdelay(3);
578
	sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598

	return 0;
}
#else
static int sh_eth_check_reset(struct net_device *ndev)
{
	int ret = 0;
	int cnt = 100;

	while (cnt > 0) {
		if (!(sh_eth_read(ndev, EDMR) & 0x3))
			break;
		mdelay(1);
		cnt--;
	}
	if (cnt < 0) {
		printk(KERN_ERR "Device reset fail\n");
		ret = -ETIMEDOUT;
	}
	return ret;
599 600 601
}
#endif

602
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	int reserve;

	reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
	if (reserve)
		skb_reserve(skb, reserve);
}
#else
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
}
#endif


619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641
/* CPU <-> EDMAC endian convert */
static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return cpu_to_le32(x);
	case EDMAC_BIG_ENDIAN:
		return cpu_to_be32(x);
	}
	return x;
}

static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return le32_to_cpu(x);
	case EDMAC_BIG_ENDIAN:
		return be32_to_cpu(x);
	}
	return x;
}

642 643 644 645 646
/*
 * Program the hardware MAC address from dev->dev_addr.
 */
static void update_mac_address(struct net_device *ndev)
{
647 648 649 650 651
	sh_eth_write(ndev,
		(ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
		(ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
	sh_eth_write(ndev,
		(ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
652 653 654 655 656 657 658 659 660 661
}

/*
 * Get MAC address from SuperH MAC address register
 *
 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 * When you want use this device, you must set MAC address in bootloader.
 *
 */
662
static void read_mac_address(struct net_device *ndev, unsigned char *mac)
663
{
664 665 666
	if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
		memcpy(ndev->dev_addr, mac, 6);
	} else {
667 668 669 670 671 672
		ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
		ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
		ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
		ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
		ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
		ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
673
	}
674 675
}

676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691
static int sh_eth_is_gether(struct sh_eth_private *mdp)
{
	if (mdp->reg_offset == sh_eth_offset_gigabit)
		return 1;
	else
		return 0;
}

static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
{
	if (sh_eth_is_gether(mdp))
		return EDTRR_TRNS_GETHER;
	else
		return EDTRR_TRNS_ETHER;
}

692
struct bb_info {
Y
Yoshihiro Shimoda 已提交
693
	void (*set_gate)(void *addr);
694
	struct mdiobb_ctrl ctrl;
Y
Yoshihiro Shimoda 已提交
695
	void *addr;
696 697 698 699 700 701 702
	u32 mmd_msk;/* MMD */
	u32 mdo_msk;
	u32 mdi_msk;
	u32 mdc_msk;
};

/* PHY bit set */
Y
Yoshihiro Shimoda 已提交
703
static void bb_set(void *addr, u32 msk)
704
{
Y
Yoshihiro Shimoda 已提交
705
	iowrite32(ioread32(addr) | msk, addr);
706 707 708
}

/* PHY bit clear */
Y
Yoshihiro Shimoda 已提交
709
static void bb_clr(void *addr, u32 msk)
710
{
Y
Yoshihiro Shimoda 已提交
711
	iowrite32((ioread32(addr) & ~msk), addr);
712 713 714
}

/* PHY bit read */
Y
Yoshihiro Shimoda 已提交
715
static int bb_read(void *addr, u32 msk)
716
{
Y
Yoshihiro Shimoda 已提交
717
	return (ioread32(addr) & msk) != 0;
718 719 720 721 722 723
}

/* Data I/O pin control */
static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
724 725 726 727

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

728 729 730 731 732 733 734 735 736 737 738
	if (bit)
		bb_set(bitbang->addr, bitbang->mmd_msk);
	else
		bb_clr(bitbang->addr, bitbang->mmd_msk);
}

/* Set bit data*/
static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

739 740 741
	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

742 743 744 745 746 747 748 749 750 751
	if (bit)
		bb_set(bitbang->addr, bitbang->mdo_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdo_msk);
}

/* Get bit data*/
static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
752 753 754 755

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

756 757 758 759 760 761 762 763
	return bb_read(bitbang->addr, bitbang->mdi_msk);
}

/* MDC pin control */
static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

764 765 766
	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789
	if (bit)
		bb_set(bitbang->addr, bitbang->mdc_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdc_msk);
}

/* mdio bus control struct */
static struct mdiobb_ops bb_ops = {
	.owner = THIS_MODULE,
	.set_mdc = sh_mdc_ctrl,
	.set_mdio_dir = sh_mmd_ctrl,
	.set_mdio_data = sh_set_mdio,
	.get_mdio_data = sh_get_mdio,
};

/* free skb and descriptor buffer */
static void sh_eth_ring_free(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;

	/* Free Rx skb ringbuffer */
	if (mdp->rx_skbuff) {
790
		for (i = 0; i < mdp->num_rx_ring; i++) {
791 792 793 794 795
			if (mdp->rx_skbuff[i])
				dev_kfree_skb(mdp->rx_skbuff[i]);
		}
	}
	kfree(mdp->rx_skbuff);
796
	mdp->rx_skbuff = NULL;
797 798 799

	/* Free Tx skb ringbuffer */
	if (mdp->tx_skbuff) {
800
		for (i = 0; i < mdp->num_tx_ring; i++) {
801 802 803 804 805
			if (mdp->tx_skbuff[i])
				dev_kfree_skb(mdp->tx_skbuff[i]);
		}
	}
	kfree(mdp->tx_skbuff);
806
	mdp->tx_skbuff = NULL;
807 808 809 810 811 812 813 814 815 816
}

/* format skb and descriptor buffer */
static void sh_eth_ring_format(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;
	struct sk_buff *skb;
	struct sh_eth_rxdesc *rxdesc = NULL;
	struct sh_eth_txdesc *txdesc = NULL;
817 818
	int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
	int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
819 820 821 822 823 824 825

	mdp->cur_rx = mdp->cur_tx = 0;
	mdp->dirty_rx = mdp->dirty_tx = 0;

	memset(mdp->rx_ring, 0, rx_ringsize);

	/* build Rx ring buffer */
826
	for (i = 0; i < mdp->num_rx_ring; i++) {
827 828
		/* skb */
		mdp->rx_skbuff[i] = NULL;
829
		skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
830 831 832
		mdp->rx_skbuff[i] = skb;
		if (skb == NULL)
			break;
833
		dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
834
				DMA_FROM_DEVICE);
835 836
		sh_eth_set_receive_align(skb);

837 838
		/* RX descriptor */
		rxdesc = &mdp->rx_ring[i];
839
		rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
840
		rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
841 842

		/* The size of the buffer is 16 byte boundary. */
843
		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
844 845
		/* Rx descriptor address set */
		if (i == 0) {
846
			sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
847 848
			if (sh_eth_is_gether(mdp))
				sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
849
		}
850 851
	}

852
	mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
853 854

	/* Mark the last entry as wrapping the ring. */
855
	rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
856 857 858 859

	memset(mdp->tx_ring, 0, tx_ringsize);

	/* build Tx ring buffer */
860
	for (i = 0; i < mdp->num_tx_ring; i++) {
861 862
		mdp->tx_skbuff[i] = NULL;
		txdesc = &mdp->tx_ring[i];
863
		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
864
		txdesc->buffer_length = 0;
865
		if (i == 0) {
866
			/* Tx descriptor address set */
867
			sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
868 869
			if (sh_eth_is_gether(mdp))
				sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
870
		}
871 872
	}

873
	txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889
}

/* Get skb and descriptor buffer */
static int sh_eth_ring_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int rx_ringsize, tx_ringsize, ret = 0;

	/*
	 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
	 * card needs room to do 8 byte alignment, +2 so we can reserve
	 * the first 2 bytes, and +16 gets room for the status word from the
	 * card.
	 */
	mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
			  (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
890 891
	if (mdp->cd->rpadir)
		mdp->rx_buf_sz += NET_IP_ALIGN;
892 893

	/* Allocate RX and TX skb rings */
894
	mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * mdp->num_rx_ring,
895 896
				GFP_KERNEL);
	if (!mdp->rx_skbuff) {
897
		dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
898 899 900 901
		ret = -ENOMEM;
		return ret;
	}

902
	mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * mdp->num_tx_ring,
903 904
				GFP_KERNEL);
	if (!mdp->tx_skbuff) {
905
		dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
906 907 908 909 910
		ret = -ENOMEM;
		goto skb_ring_free;
	}

	/* Allocate all Rx descriptors. */
911
	rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
912 913 914 915
	mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
			GFP_KERNEL);

	if (!mdp->rx_ring) {
916 917
		dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
			rx_ringsize);
918 919 920 921 922 923 924
		ret = -ENOMEM;
		goto desc_ring_free;
	}

	mdp->dirty_rx = 0;

	/* Allocate all Tx descriptors. */
925
	tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
926 927 928
	mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
			GFP_KERNEL);
	if (!mdp->tx_ring) {
929 930
		dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
			tx_ringsize);
931 932 933 934 935 936 937 938 939 940 941 942
		ret = -ENOMEM;
		goto desc_ring_free;
	}
	return ret;

desc_ring_free:
	/* free DMA buffer */
	dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);

skb_ring_free:
	/* Free Rx and Tx skb ring buffer */
	sh_eth_ring_free(ndev);
943 944
	mdp->tx_ring = NULL;
	mdp->rx_ring = NULL;
945 946 947 948

	return ret;
}

949 950 951 952 953
static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
{
	int ringsize;

	if (mdp->rx_ring) {
954
		ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
955 956 957 958 959 960
		dma_free_coherent(NULL, ringsize, mdp->rx_ring,
				  mdp->rx_desc_dma);
		mdp->rx_ring = NULL;
	}

	if (mdp->tx_ring) {
961
		ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
962 963 964 965 966 967
		dma_free_coherent(NULL, ringsize, mdp->tx_ring,
				  mdp->tx_desc_dma);
		mdp->tx_ring = NULL;
	}
}

968
static int sh_eth_dev_init(struct net_device *ndev, bool start)
969 970 971 972 973 974
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 val;

	/* Soft Reset */
975 976 977
	ret = sh_eth_reset(ndev);
	if (ret)
		goto out;
978

979 980
	/* Descriptor format */
	sh_eth_ring_format(ndev);
981
	if (mdp->cd->rpadir)
982
		sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
983 984

	/* all sh_eth int mask */
985
	sh_eth_write(ndev, 0, EESIPR);
986

987
#if defined(__LITTLE_ENDIAN)
988
	if (mdp->cd->hw_swap)
989
		sh_eth_write(ndev, EDMR_EL, EDMR);
990
	else
991
#endif
992
		sh_eth_write(ndev, 0, EDMR);
993

994
	/* FIFO size set */
995 996
	sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
	sh_eth_write(ndev, 0, TFTR);
997

998
	/* Frame recv control */
999
	sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1000

1001
	sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1002

1003
	if (mdp->cd->bculr)
1004
		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
1005

1006
	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1007

1008
	if (!mdp->cd->no_trimd)
1009
		sh_eth_write(ndev, 0, TRIMD);
1010

1011
	/* Recv frame limit set register */
1012 1013
	sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
		     RFLR);
1014

1015
	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1016 1017
	if (start)
		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1018 1019

	/* PAUSE Prohibition */
1020
	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1021 1022
		ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;

1023
	sh_eth_write(ndev, val, ECMR);
1024

1025 1026 1027
	if (mdp->cd->set_rate)
		mdp->cd->set_rate(ndev);

1028
	/* E-MAC Status Register clear */
1029
	sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1030 1031

	/* E-MAC Interrupt Enable register */
1032 1033
	if (start)
		sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1034 1035 1036 1037 1038

	/* Set MAC address */
	update_mac_address(ndev);

	/* mask reset */
1039
	if (mdp->cd->apr)
1040
		sh_eth_write(ndev, APR_AP, APR);
1041
	if (mdp->cd->mpr)
1042
		sh_eth_write(ndev, MPR_MP, MPR);
1043
	if (mdp->cd->tpauser)
1044
		sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1045

1046 1047 1048
	if (start) {
		/* Setting the Rx mode will start the Rx process. */
		sh_eth_write(ndev, EDRRR_R, EDRRR);
1049

1050 1051
		netif_start_queue(ndev);
	}
1052

1053
out:
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065
	return ret;
}

/* free Tx skb function */
static int sh_eth_txfree(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
	int freeNum = 0;
	int entry = 0;

	for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1066
		entry = mdp->dirty_tx % mdp->num_tx_ring;
1067
		txdesc = &mdp->tx_ring[entry];
1068
		if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1069 1070 1071
			break;
		/* Free the original skb. */
		if (mdp->tx_skbuff[entry]) {
1072 1073
			dma_unmap_single(&ndev->dev, txdesc->addr,
					 txdesc->buffer_length, DMA_TO_DEVICE);
1074 1075 1076 1077
			dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
			mdp->tx_skbuff[entry] = NULL;
			freeNum++;
		}
1078
		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1079
		if (entry >= mdp->num_tx_ring - 1)
1080
			txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1081

1082 1083
		ndev->stats.tx_packets++;
		ndev->stats.tx_bytes += txdesc->buffer_length;
1084 1085 1086 1087 1088
	}
	return freeNum;
}

/* Packet receive function */
1089
static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
1090 1091 1092 1093
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;

1094 1095
	int entry = mdp->cur_rx % mdp->num_rx_ring;
	int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1096 1097
	struct sk_buff *skb;
	u16 pkt_len = 0;
1098
	u32 desc_status;
1099 1100

	rxdesc = &mdp->rx_ring[entry];
1101 1102
	while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
		desc_status = edmac_to_cpu(mdp, rxdesc->status);
1103 1104
		pkt_len = rxdesc->frame_length;

1105 1106 1107 1108
#if defined(CONFIG_ARCH_R8A7740)
		desc_status >>= 16;
#endif

1109 1110 1111 1112
		if (--boguscnt < 0)
			break;

		if (!(desc_status & RDFEND))
1113
			ndev->stats.rx_length_errors++;
1114 1115 1116

		if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
				   RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1117
			ndev->stats.rx_errors++;
1118
			if (desc_status & RD_RFS1)
1119
				ndev->stats.rx_crc_errors++;
1120
			if (desc_status & RD_RFS2)
1121
				ndev->stats.rx_frame_errors++;
1122
			if (desc_status & RD_RFS3)
1123
				ndev->stats.rx_length_errors++;
1124
			if (desc_status & RD_RFS4)
1125
				ndev->stats.rx_length_errors++;
1126
			if (desc_status & RD_RFS6)
1127
				ndev->stats.rx_missed_errors++;
1128
			if (desc_status & RD_RFS10)
1129
				ndev->stats.rx_over_errors++;
1130
		} else {
1131 1132 1133 1134
			if (!mdp->cd->hw_swap)
				sh_eth_soft_swap(
					phys_to_virt(ALIGN(rxdesc->addr, 4)),
					pkt_len + 2);
1135 1136
			skb = mdp->rx_skbuff[entry];
			mdp->rx_skbuff[entry] = NULL;
1137 1138
			if (mdp->cd->rpadir)
				skb_reserve(skb, NET_IP_ALIGN);
1139 1140 1141
			skb_put(skb, pkt_len);
			skb->protocol = eth_type_trans(skb, ndev);
			netif_rx(skb);
1142 1143
			ndev->stats.rx_packets++;
			ndev->stats.rx_bytes += pkt_len;
1144
		}
1145
		rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1146
		entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1147
		rxdesc = &mdp->rx_ring[entry];
1148 1149 1150 1151
	}

	/* Refill the Rx ring buffers. */
	for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1152
		entry = mdp->dirty_rx % mdp->num_rx_ring;
1153
		rxdesc = &mdp->rx_ring[entry];
1154
		/* The size of the buffer is 16 byte boundary. */
1155
		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1156

1157
		if (mdp->rx_skbuff[entry] == NULL) {
1158
			skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1159 1160 1161
			mdp->rx_skbuff[entry] = skb;
			if (skb == NULL)
				break;	/* Better luck next round. */
1162
			dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1163
					DMA_FROM_DEVICE);
1164 1165
			sh_eth_set_receive_align(skb);

1166
			skb_checksum_none_assert(skb);
1167
			rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1168
		}
1169
		if (entry >= mdp->num_rx_ring - 1)
1170
			rxdesc->status |=
1171
				cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1172 1173
		else
			rxdesc->status |=
1174
				cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1175 1176 1177 1178
	}

	/* Restart Rx engine if stopped. */
	/* If we don't need to check status, don't. -KDU */
1179
	if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1180 1181 1182 1183 1184
		/* fix the values for the next receiving if RDE is set */
		if (intr_status & EESR_RDE)
			mdp->cur_rx = mdp->dirty_rx =
				(sh_eth_read(ndev, RDFAR) -
				 sh_eth_read(ndev, RDLAR)) >> 4;
1185
		sh_eth_write(ndev, EDRRR_R, EDRRR);
1186
	}
1187 1188 1189 1190

	return 0;
}

1191
static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1192 1193
{
	/* disable tx and rx */
1194 1195
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
		~(ECMR_RE | ECMR_TE), ECMR);
1196 1197
}

1198
static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1199 1200
{
	/* enable tx and rx */
1201 1202
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
		(ECMR_RE | ECMR_TE), ECMR);
1203 1204
}

1205 1206 1207 1208 1209
/* error control function */
static void sh_eth_error(struct net_device *ndev, int intr_status)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 felic_stat;
1210 1211
	u32 link_stat;
	u32 mask;
1212 1213

	if (intr_status & EESR_ECI) {
1214 1215
		felic_stat = sh_eth_read(ndev, ECSR);
		sh_eth_write(ndev, felic_stat, ECSR);	/* clear int */
1216
		if (felic_stat & ECSR_ICD)
1217
			ndev->stats.tx_carrier_errors++;
1218 1219
		if (felic_stat & ECSR_LCHNG) {
			/* Link Changed */
1220
			if (mdp->cd->no_psr || mdp->no_ether_link) {
1221 1222 1223 1224 1225
				if (mdp->link == PHY_DOWN)
					link_stat = 0;
				else
					link_stat = PHY_ST_LINK;
			} else {
1226
				link_stat = (sh_eth_read(ndev, PSR));
1227 1228
				if (mdp->ether_link_active_low)
					link_stat = ~link_stat;
1229
			}
1230
			if (!(link_stat & PHY_ST_LINK))
1231
				sh_eth_rcv_snd_disable(ndev);
1232
			else {
1233
				/* Link Up */
1234 1235
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
					  ~DMAC_M_ECI, EESIPR);
1236
				/*clear int */
1237 1238 1239 1240
				sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
					  ECSR);
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
					  DMAC_M_ECI, EESIPR);
1241
				/* enable tx and rx */
1242
				sh_eth_rcv_snd_enable(ndev);
1243 1244 1245 1246 1247 1248 1249
			}
		}
	}

	if (intr_status & EESR_TWB) {
		/* Write buck end. unused write back interrupt */
		if (intr_status & EESR_TABT)	/* Transmit Abort int */
1250
			ndev->stats.tx_aborted_errors++;
1251 1252
			if (netif_msg_tx_err(mdp))
				dev_err(&ndev->dev, "Transmit Abort\n");
1253 1254 1255 1256 1257 1258
	}

	if (intr_status & EESR_RABT) {
		/* Receive Abort int */
		if (intr_status & EESR_RFRMER) {
			/* Receive Frame Overflow int */
1259
			ndev->stats.rx_frame_errors++;
1260 1261
			if (netif_msg_rx_err(mdp))
				dev_err(&ndev->dev, "Receive Abort\n");
1262 1263
		}
	}
1264

1265 1266
	if (intr_status & EESR_TDE) {
		/* Transmit Descriptor Empty int */
1267
		ndev->stats.tx_fifo_errors++;
1268 1269 1270 1271 1272 1273
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
	}

	if (intr_status & EESR_TFE) {
		/* FIFO under flow */
1274
		ndev->stats.tx_fifo_errors++;
1275 1276
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1277 1278 1279 1280
	}

	if (intr_status & EESR_RDE) {
		/* Receive Descriptor Empty int */
1281
		ndev->stats.rx_over_errors++;
1282

1283 1284
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1285
	}
1286

1287 1288
	if (intr_status & EESR_RFE) {
		/* Receive FIFO Overflow int */
1289
		ndev->stats.rx_fifo_errors++;
1290 1291 1292 1293 1294 1295
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive FIFO Overflow\n");
	}

	if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
		/* Address Error */
1296
		ndev->stats.tx_fifo_errors++;
1297 1298
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Address Error\n");
1299
	}
1300 1301 1302 1303 1304

	mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
	if (mdp->cd->no_ade)
		mask &= ~EESR_ADE;
	if (intr_status & mask) {
1305
		/* Tx error */
1306
		u32 edtrr = sh_eth_read(ndev, EDTRR);
1307
		/* dmesg */
1308 1309 1310
		dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
				intr_status, mdp->cur_tx);
		dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1311 1312 1313 1314 1315
				mdp->dirty_tx, (u32) ndev->state, edtrr);
		/* dirty buffer free */
		sh_eth_txfree(ndev);

		/* SH7712 BUG */
1316
		if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1317
			/* tx dma start */
1318
			sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1319 1320 1321 1322 1323 1324 1325 1326 1327 1328
		}
		/* wakeup */
		netif_wake_queue(ndev);
	}
}

static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
{
	struct net_device *ndev = netdev;
	struct sh_eth_private *mdp = netdev_priv(ndev);
1329
	struct sh_eth_cpu_data *cd = mdp->cd;
1330
	irqreturn_t ret = IRQ_NONE;
1331
	u32 intr_status = 0;
1332 1333 1334

	spin_lock(&mdp->lock);

1335
	/* Get interrpt stat */
1336
	intr_status = sh_eth_read(ndev, EESR);
1337
	/* Clear interrupt */
1338 1339
	if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
			EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1340
			cd->tx_check | cd->eesr_err_check)) {
1341
		sh_eth_write(ndev, intr_status, EESR);
1342 1343 1344
		ret = IRQ_HANDLED;
	} else
		goto other_irq;
1345

1346 1347 1348 1349 1350 1351 1352
	if (intr_status & (EESR_FRC | /* Frame recv*/
			EESR_RMAF | /* Multi cast address recv*/
			EESR_RRF  | /* Bit frame recv */
			EESR_RTLF | /* Long frame recv*/
			EESR_RTSF | /* short frame recv */
			EESR_PRE  | /* PHY-LSI recv error */
			EESR_CERF)){ /* recv frame CRC error */
1353
		sh_eth_rx(ndev, intr_status);
1354
	}
1355

1356
	/* Tx Check */
1357
	if (intr_status & cd->tx_check) {
1358 1359 1360 1361
		sh_eth_txfree(ndev);
		netif_wake_queue(ndev);
	}

1362
	if (intr_status & cd->eesr_err_check)
1363 1364
		sh_eth_error(ndev, intr_status);

1365
other_irq:
1366 1367
	spin_unlock(&mdp->lock);

1368
	return ret;
1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
}

/* PHY state control function */
static void sh_eth_adjust_link(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;
	int new_state = 0;

	if (phydev->link != PHY_DOWN) {
		if (phydev->duplex != mdp->duplex) {
			new_state = 1;
			mdp->duplex = phydev->duplex;
1382 1383
			if (mdp->cd->set_duplex)
				mdp->cd->set_duplex(ndev);
1384 1385 1386 1387 1388
		}

		if (phydev->speed != mdp->speed) {
			new_state = 1;
			mdp->speed = phydev->speed;
1389 1390
			if (mdp->cd->set_rate)
				mdp->cd->set_rate(ndev);
1391 1392
		}
		if (mdp->link == PHY_DOWN) {
1393 1394
			sh_eth_write(ndev,
				(sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1395 1396 1397 1398 1399 1400 1401 1402 1403 1404
			new_state = 1;
			mdp->link = phydev->link;
		}
	} else if (mdp->link) {
		new_state = 1;
		mdp->link = PHY_DOWN;
		mdp->speed = 0;
		mdp->duplex = -1;
	}

1405
	if (new_state && netif_msg_link(mdp))
1406 1407 1408 1409 1410 1411 1412
		phy_print_status(phydev);
}

/* PHY init function */
static int sh_eth_phy_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
1413
	char phy_id[MII_BUS_ID_SIZE + 3];
1414 1415
	struct phy_device *phydev = NULL;

1416
	snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1417 1418 1419 1420 1421 1422 1423
		mdp->mii_bus->id , mdp->phy_id);

	mdp->link = PHY_DOWN;
	mdp->speed = 0;
	mdp->duplex = -1;

	/* Try connect to PHY */
1424
	phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1425
			     mdp->phy_interface);
1426 1427 1428 1429
	if (IS_ERR(phydev)) {
		dev_err(&ndev->dev, "phy_connect failed\n");
		return PTR_ERR(phydev);
	}
1430

1431
	dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1432
		phydev->addr, phydev->drv->name);
1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455

	mdp->phydev = phydev;

	return 0;
}

/* PHY control start function */
static int sh_eth_phy_start(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	ret = sh_eth_phy_init(ndev);
	if (ret)
		return ret;

	/* reset phy - this also wakes it from PDOWN */
	phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
	phy_start(mdp->phydev);

	return 0;
}

1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479
static int sh_eth_get_settings(struct net_device *ndev,
			struct ethtool_cmd *ecmd)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_ethtool_gset(mdp->phydev, ecmd);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_set_settings(struct net_device *ndev,
		struct ethtool_cmd *ecmd)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);

	/* disable tx and rx */
1480
	sh_eth_rcv_snd_disable(ndev);
1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497

	ret = phy_ethtool_sset(mdp->phydev, ecmd);
	if (ret)
		goto error_exit;

	if (ecmd->duplex == DUPLEX_FULL)
		mdp->duplex = 1;
	else
		mdp->duplex = 0;

	if (mdp->cd->set_duplex)
		mdp->cd->set_duplex(ndev);

error_exit:
	mdelay(1);

	/* enable tx and rx */
1498
	sh_eth_rcv_snd_enable(ndev);
1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568

	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_nway_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_start_aneg(mdp->phydev);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static u32 sh_eth_get_msglevel(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	return mdp->msg_enable;
}

static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	mdp->msg_enable = value;
}

static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
	"rx_current", "tx_current",
	"rx_dirty", "tx_dirty",
};
#define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)

static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
{
	switch (sset) {
	case ETH_SS_STATS:
		return SH_ETH_STATS_LEN;
	default:
		return -EOPNOTSUPP;
	}
}

static void sh_eth_get_ethtool_stats(struct net_device *ndev,
			struct ethtool_stats *stats, u64 *data)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i = 0;

	/* device-specific stats */
	data[i++] = mdp->cur_rx;
	data[i++] = mdp->cur_tx;
	data[i++] = mdp->dirty_rx;
	data[i++] = mdp->dirty_tx;
}

static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(data, *sh_eth_gstrings_stats,
					sizeof(sh_eth_gstrings_stats));
		break;
	}
}

1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
static void sh_eth_get_ringparam(struct net_device *ndev,
				 struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	ring->rx_max_pending = RX_RING_MAX;
	ring->tx_max_pending = TX_RING_MAX;
	ring->rx_pending = mdp->num_rx_ring;
	ring->tx_pending = mdp->num_tx_ring;
}

static int sh_eth_set_ringparam(struct net_device *ndev,
				struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	if (ring->tx_pending > TX_RING_MAX ||
	    ring->rx_pending > RX_RING_MAX ||
	    ring->tx_pending < TX_RING_MIN ||
	    ring->rx_pending < RX_RING_MIN)
		return -EINVAL;
	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
		return -EINVAL;

	if (netif_running(ndev)) {
		netif_tx_disable(ndev);
		/* Disable interrupts by clearing the interrupt mask. */
		sh_eth_write(ndev, 0x0000, EESIPR);
		/* Stop the chip's Tx and Rx processes. */
		sh_eth_write(ndev, 0, EDTRR);
		sh_eth_write(ndev, 0, EDRRR);
		synchronize_irq(ndev->irq);
	}

	/* Free all the skbuffs in the Rx queue. */
	sh_eth_ring_free(ndev);
	/* Free DMA buffer */
	sh_eth_free_dma_buffer(mdp);

	/* Set new parameters */
	mdp->num_rx_ring = ring->rx_pending;
	mdp->num_tx_ring = ring->tx_pending;

	ret = sh_eth_ring_init(ndev);
	if (ret < 0) {
		dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
		return ret;
	}
	ret = sh_eth_dev_init(ndev, false);
	if (ret < 0) {
		dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
		return ret;
	}

	if (netif_running(ndev)) {
		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
		/* Setting the Rx mode will start the Rx process. */
		sh_eth_write(ndev, EDRRR_R, EDRRR);
		netif_wake_queue(ndev);
	}

	return 0;
}

S
stephen hemminger 已提交
1634
static const struct ethtool_ops sh_eth_ethtool_ops = {
1635 1636
	.get_settings	= sh_eth_get_settings,
	.set_settings	= sh_eth_set_settings,
S
stephen hemminger 已提交
1637
	.nway_reset	= sh_eth_nway_reset,
1638 1639
	.get_msglevel	= sh_eth_get_msglevel,
	.set_msglevel	= sh_eth_set_msglevel,
S
stephen hemminger 已提交
1640
	.get_link	= ethtool_op_get_link,
1641 1642 1643
	.get_strings	= sh_eth_get_strings,
	.get_ethtool_stats  = sh_eth_get_ethtool_stats,
	.get_sset_count     = sh_eth_get_sset_count,
1644 1645
	.get_ringparam	= sh_eth_get_ringparam,
	.set_ringparam	= sh_eth_set_ringparam,
1646 1647
};

1648 1649 1650 1651 1652 1653
/* network device open function */
static int sh_eth_open(struct net_device *ndev)
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);

1654 1655
	pm_runtime_get_sync(&mdp->pdev->dev);

1656
	ret = request_irq(ndev->irq, sh_eth_interrupt,
1657
#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1658 1659
	defined(CONFIG_CPU_SUBTYPE_SH7764) || \
	defined(CONFIG_CPU_SUBTYPE_SH7757)
1660 1661 1662 1663 1664
				IRQF_SHARED,
#else
				0,
#endif
				ndev->name, ndev);
1665
	if (ret) {
1666
		dev_err(&ndev->dev, "Can not assign IRQ number\n");
1667 1668 1669 1670 1671 1672 1673 1674 1675
		return ret;
	}

	/* Descriptor set */
	ret = sh_eth_ring_init(ndev);
	if (ret)
		goto out_free_irq;

	/* device init */
1676
	ret = sh_eth_dev_init(ndev, true);
1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688
	if (ret)
		goto out_free_irq;

	/* PHY control start*/
	ret = sh_eth_phy_start(ndev);
	if (ret)
		goto out_free_irq;

	return ret;

out_free_irq:
	free_irq(ndev->irq, ndev);
1689
	pm_runtime_put_sync(&mdp->pdev->dev);
1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701
	return ret;
}

/* Timeout function */
static void sh_eth_tx_timeout(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;
	int i;

	netif_stop_queue(ndev);

1702 1703
	if (netif_msg_timer(mdp))
		dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1704
	       " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1705 1706

	/* tx_errors count up */
1707
	ndev->stats.tx_errors++;
1708 1709

	/* Free all the skbuffs in the Rx queue. */
1710
	for (i = 0; i < mdp->num_rx_ring; i++) {
1711 1712 1713 1714 1715 1716 1717
		rxdesc = &mdp->rx_ring[i];
		rxdesc->status = 0;
		rxdesc->addr = 0xBADF00D0;
		if (mdp->rx_skbuff[i])
			dev_kfree_skb(mdp->rx_skbuff[i]);
		mdp->rx_skbuff[i] = NULL;
	}
1718
	for (i = 0; i < mdp->num_tx_ring; i++) {
1719 1720 1721 1722 1723 1724
		if (mdp->tx_skbuff[i])
			dev_kfree_skb(mdp->tx_skbuff[i]);
		mdp->tx_skbuff[i] = NULL;
	}

	/* device init */
1725
	sh_eth_dev_init(ndev, true);
1726 1727 1728 1729 1730 1731 1732 1733
}

/* Packet transmit function */
static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
	u32 entry;
1734
	unsigned long flags;
1735 1736

	spin_lock_irqsave(&mdp->lock, flags);
1737
	if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1738
		if (!sh_eth_txfree(ndev)) {
1739 1740
			if (netif_msg_tx_queued(mdp))
				dev_warn(&ndev->dev, "TxFD exhausted.\n");
1741 1742
			netif_stop_queue(ndev);
			spin_unlock_irqrestore(&mdp->lock, flags);
1743
			return NETDEV_TX_BUSY;
1744 1745 1746 1747
		}
	}
	spin_unlock_irqrestore(&mdp->lock, flags);

1748
	entry = mdp->cur_tx % mdp->num_tx_ring;
1749 1750 1751
	mdp->tx_skbuff[entry] = skb;
	txdesc = &mdp->tx_ring[entry];
	/* soft swap. */
1752 1753 1754
	if (!mdp->cd->hw_swap)
		sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
				 skb->len + 2);
1755 1756
	txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
				      DMA_TO_DEVICE);
1757 1758 1759 1760 1761
	if (skb->len < ETHERSMALL)
		txdesc->buffer_length = ETHERSMALL;
	else
		txdesc->buffer_length = skb->len;

1762
	if (entry >= mdp->num_tx_ring - 1)
1763
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1764
	else
1765
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1766 1767 1768

	mdp->cur_tx++;

1769 1770
	if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
		sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1771

1772
	return NETDEV_TX_OK;
1773 1774 1775 1776 1777 1778 1779 1780 1781 1782
}

/* device close function */
static int sh_eth_close(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	netif_stop_queue(ndev);

	/* Disable interrupts by clearing the interrupt mask. */
1783
	sh_eth_write(ndev, 0x0000, EESIPR);
1784 1785

	/* Stop the chip's Tx and Rx processes. */
1786 1787
	sh_eth_write(ndev, 0, EDTRR);
	sh_eth_write(ndev, 0, EDRRR);
1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800

	/* PHY Disconnect */
	if (mdp->phydev) {
		phy_stop(mdp->phydev);
		phy_disconnect(mdp->phydev);
	}

	free_irq(ndev->irq, ndev);

	/* Free all the skbuffs in the Rx queue. */
	sh_eth_ring_free(ndev);

	/* free DMA buffer */
1801
	sh_eth_free_dma_buffer(mdp);
1802

1803 1804
	pm_runtime_put_sync(&mdp->pdev->dev);

1805 1806 1807 1808 1809 1810 1811
	return 0;
}

static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

1812 1813
	pm_runtime_get_sync(&mdp->pdev->dev);

1814
	ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1815
	sh_eth_write(ndev, 0, TROCR);	/* (write clear) */
1816
	ndev->stats.collisions += sh_eth_read(ndev, CDCR);
1817
	sh_eth_write(ndev, 0, CDCR);	/* (write clear) */
1818
	ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1819
	sh_eth_write(ndev, 0, LCCR);	/* (write clear) */
1820
	if (sh_eth_is_gether(mdp)) {
1821
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1822
		sh_eth_write(ndev, 0, CERCR);	/* (write clear) */
1823
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1824 1825
		sh_eth_write(ndev, 0, CEECR);	/* (write clear) */
	} else {
1826
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1827 1828
		sh_eth_write(ndev, 0, CNDCR);	/* (write clear) */
	}
1829 1830
	pm_runtime_put_sync(&mdp->pdev->dev);

1831
	return &ndev->stats;
1832 1833
}

1834
/* ioctl to device function */
1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846
static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
				int cmd)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;

	if (!netif_running(ndev))
		return -EINVAL;

	if (!phydev)
		return -ENODEV;

1847
	return phy_mii_ioctl(phydev, rq, cmd);
1848 1849
}

1850
#if defined(SH_ETH_HAS_TSU)
1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082
/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
					    int entry)
{
	return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
}

static u32 sh_eth_tsu_get_post_mask(int entry)
{
	return 0x0f << (28 - ((entry % 8) * 4));
}

static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
{
	return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
}

static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
					     int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	tmp = ioread32(reg_offset);
	iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
}

static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 post_mask, ref_mask, tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	post_mask = sh_eth_tsu_get_post_mask(entry);
	ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;

	tmp = ioread32(reg_offset);
	iowrite32(tmp & ~post_mask, reg_offset);

	/* If other port enables, the function returns "true" */
	return tmp & ref_mask;
}

static int sh_eth_tsu_busy(struct net_device *ndev)
{
	int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
		udelay(10);
		timeout--;
		if (timeout <= 0) {
			dev_err(&ndev->dev, "%s: timeout\n", __func__);
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
				  const u8 *addr)
{
	u32 val;

	val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
	iowrite32(val, reg);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	val = addr[4] << 8 | addr[5];
	iowrite32(val, reg + 4);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	return 0;
}

static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
{
	u32 val;

	val = ioread32(reg);
	addr[0] = (val >> 24) & 0xff;
	addr[1] = (val >> 16) & 0xff;
	addr[2] = (val >> 8) & 0xff;
	addr[3] = val & 0xff;
	val = ioread32(reg + 4);
	addr[4] = (val >> 8) & 0xff;
	addr[5] = val & 0xff;
}


static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;
	u8 c_addr[ETH_ALEN];

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, c_addr);
		if (memcmp(addr, c_addr, ETH_ALEN) == 0)
			return i;
	}

	return -ENOENT;
}

static int sh_eth_tsu_find_empty(struct net_device *ndev)
{
	u8 blank[ETH_ALEN];
	int entry;

	memset(blank, 0, sizeof(blank));
	entry = sh_eth_tsu_find_entry(ndev, blank);
	return (entry < 0) ? -ENOMEM : entry;
}

static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int ret;
	u8 blank[ETH_ALEN];

	sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
			 ~(1 << (31 - entry)), TSU_TEN);

	memset(blank, 0, sizeof(blank));
	ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
	if (ret < 0)
		return ret;
	return 0;
}

static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i < 0) {
		/* No entry found, create one */
		i = sh_eth_tsu_find_empty(ndev);
		if (i < 0)
			return -ENOMEM;
		ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
		if (ret < 0)
			return ret;

		/* Enable the entry */
		sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
				 (1 << (31 - i)), TSU_TEN);
	}

	/* Entry found or created, enable POST */
	sh_eth_tsu_enable_cam_entry_post(ndev, i);

	return 0;
}

static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i) {
		/* Entry found */
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			goto done;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}
done:
	return 0;
}

static int sh_eth_tsu_purge_all(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

	if (unlikely(!mdp->cd->tsu))
		return 0;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			continue;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u8 addr[ETH_ALEN];
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;

	if (unlikely(!mdp->cd->tsu))
		return;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, addr);
		if (is_multicast_ether_addr(addr))
			sh_eth_tsu_del_entry(ndev, addr);
	}
}

2083 2084 2085
/* Multicast reception directions set */
static void sh_eth_set_multicast_list(struct net_device *ndev)
{
2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 ecmr_bits;
	int mcast_all = 0;
	unsigned long flags;

	spin_lock_irqsave(&mdp->lock, flags);
	/*
	 * Initial condition is MCT = 1, PRM = 0.
	 * Depending on ndev->flags, set PRM or clear MCT
	 */
	ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;

	if (!(ndev->flags & IFF_MULTICAST)) {
		sh_eth_tsu_purge_mcast(ndev);
		mcast_all = 1;
	}
	if (ndev->flags & IFF_ALLMULTI) {
		sh_eth_tsu_purge_mcast(ndev);
		ecmr_bits &= ~ECMR_MCT;
		mcast_all = 1;
	}

2108
	if (ndev->flags & IFF_PROMISC) {
2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124
		sh_eth_tsu_purge_all(ndev);
		ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
	} else if (mdp->cd->tsu) {
		struct netdev_hw_addr *ha;
		netdev_for_each_mc_addr(ha, ndev) {
			if (mcast_all && is_multicast_ether_addr(ha->addr))
				continue;

			if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
				if (!mcast_all) {
					sh_eth_tsu_purge_mcast(ndev);
					ecmr_bits &= ~ECMR_MCT;
					mcast_all = 1;
				}
			}
		}
2125 2126
	} else {
		/* Normal, unicast/broadcast-only mode. */
2127
		ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2128
	}
2129 2130 2131 2132 2133

	/* update the ethernet mode */
	sh_eth_write(ndev, ecmr_bits, ECMR);

	spin_unlock_irqrestore(&mdp->lock, flags);
2134
}
2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190

static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
{
	if (!mdp->port)
		return TSU_VTAG0;
	else
		return TSU_VTAG1;
}

static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids++;

	/*
	 * The controller has one VLAN tag HW filter. So, if the filter is
	 * already enabled, the driver disables it and the filte
	 */
	if (mdp->vlan_num_ids > 1) {
		/* disable VLAN filter */
		sh_eth_tsu_write(mdp, 0, vtag_reg_index);
		return 0;
	}

	sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
			 vtag_reg_index);

	return 0;
}

static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids--;
	sh_eth_tsu_write(mdp, 0, vtag_reg_index);

	return 0;
}
2191
#endif /* SH_ETH_HAS_TSU */
2192 2193

/* SuperH's TSU register init function */
2194
static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2195
{
2196 2197 2198 2199 2200 2201 2202 2203 2204 2205
	sh_eth_tsu_write(mdp, 0, TSU_FWEN0);	/* Disable forward(0->1) */
	sh_eth_tsu_write(mdp, 0, TSU_FWEN1);	/* Disable forward(1->0) */
	sh_eth_tsu_write(mdp, 0, TSU_FCM);	/* forward fifo 3k-3k */
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
	sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2206 2207 2208 2209 2210 2211 2212
	if (sh_eth_is_gether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_QTAG0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAG1);	/* Disable QTAG(1->0) */
	} else {
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);	/* Disable QTAG(1->0) */
	}
2213 2214 2215 2216 2217 2218 2219
	sh_eth_tsu_write(mdp, 0, TSU_FWSR);	/* all interrupt status clear */
	sh_eth_tsu_write(mdp, 0, TSU_FWINMK);	/* Disable all interrupt */
	sh_eth_tsu_write(mdp, 0, TSU_TEN);	/* Disable all CAM entry */
	sh_eth_tsu_write(mdp, 0, TSU_POST1);	/* Disable CAM entry [ 0- 7] */
	sh_eth_tsu_write(mdp, 0, TSU_POST2);	/* Disable CAM entry [ 8-15] */
	sh_eth_tsu_write(mdp, 0, TSU_POST3);	/* Disable CAM entry [16-23] */
	sh_eth_tsu_write(mdp, 0, TSU_POST4);	/* Disable CAM entry [24-31] */
2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232
}

/* MDIO bus release function */
static int sh_mdio_release(struct net_device *ndev)
{
	struct mii_bus *bus = dev_get_drvdata(&ndev->dev);

	/* unregister mdio bus */
	mdiobus_unregister(bus);

	/* remove mdio bus info from net_device */
	dev_set_drvdata(&ndev->dev, NULL);

2233 2234 2235
	/* free interrupts memory */
	kfree(bus->irq);

2236 2237 2238 2239 2240 2241 2242
	/* free bitbang info */
	free_mdio_bitbang(bus);

	return 0;
}

/* MDIO bus init function */
2243 2244
static int sh_mdio_init(struct net_device *ndev, int id,
			struct sh_eth_plat_data *pd)
2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257
{
	int ret, i;
	struct bb_info *bitbang;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* create bit control struct for PHY */
	bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
	if (!bitbang) {
		ret = -ENOMEM;
		goto out;
	}

	/* bitbang init */
Y
Yoshihiro Shimoda 已提交
2258
	bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2259
	bitbang->set_gate = pd->set_mdio_gate;
2260 2261 2262 2263 2264 2265
	bitbang->mdi_msk = 0x08;
	bitbang->mdo_msk = 0x04;
	bitbang->mmd_msk = 0x02;/* MMD */
	bitbang->mdc_msk = 0x01;
	bitbang->ctrl.ops = &bb_ops;

2266
	/* MII controller setting */
2267 2268 2269 2270 2271 2272 2273 2274
	mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
	if (!mdp->mii_bus) {
		ret = -ENOMEM;
		goto out_free_bitbang;
	}

	/* Hook up MII support for ethtool */
	mdp->mii_bus->name = "sh_mii";
2275
	mdp->mii_bus->parent = &ndev->dev;
2276
	snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2277
		mdp->pdev->name, id);
2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288

	/* PHY IRQ */
	mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
	if (!mdp->mii_bus->irq) {
		ret = -ENOMEM;
		goto out_free_bus;
	}

	for (i = 0; i < PHY_MAX_ADDR; i++)
		mdp->mii_bus->irq[i] = PHY_POLL;

2289
	/* register mdio bus */
2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301
	ret = mdiobus_register(mdp->mii_bus);
	if (ret)
		goto out_free_irq;

	dev_set_drvdata(&ndev->dev, mdp->mii_bus);

	return 0;

out_free_irq:
	kfree(mdp->mii_bus->irq);

out_free_bus:
2302
	free_mdio_bitbang(mdp->mii_bus);
2303 2304 2305 2306 2307 2308 2309 2310

out_free_bitbang:
	kfree(bitbang);

out:
	return ret;
}

2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332
static const u16 *sh_eth_get_register_offset(int register_type)
{
	const u16 *reg_offset = NULL;

	switch (register_type) {
	case SH_ETH_REG_GIGABIT:
		reg_offset = sh_eth_offset_gigabit;
		break;
	case SH_ETH_REG_FAST_SH4:
		reg_offset = sh_eth_offset_fast_sh4;
		break;
	case SH_ETH_REG_FAST_SH3_SH2:
		reg_offset = sh_eth_offset_fast_sh3_sh2;
		break;
	default:
		printk(KERN_ERR "Unknown register type (%d)\n", register_type);
		break;
	}

	return reg_offset;
}

2333 2334 2335 2336 2337
static const struct net_device_ops sh_eth_netdev_ops = {
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
2338
#if defined(SH_ETH_HAS_TSU)
2339
	.ndo_set_rx_mode	= sh_eth_set_multicast_list,
2340 2341
	.ndo_vlan_rx_add_vid	= sh_eth_vlan_rx_add_vid,
	.ndo_vlan_rx_kill_vid	= sh_eth_vlan_rx_kill_vid,
2342
#endif
2343 2344 2345 2346 2347 2348 2349
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
	.ndo_change_mtu		= eth_change_mtu,
};

2350 2351
static int sh_eth_drv_probe(struct platform_device *pdev)
{
2352
	int ret, devno = 0;
2353 2354
	struct resource *res;
	struct net_device *ndev = NULL;
2355
	struct sh_eth_private *mdp = NULL;
2356
	struct sh_eth_plat_data *pd;
2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378

	/* get base addr */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(res == NULL)) {
		dev_err(&pdev->dev, "invalid resource\n");
		ret = -EINVAL;
		goto out;
	}

	ndev = alloc_etherdev(sizeof(struct sh_eth_private));
	if (!ndev) {
		ret = -ENOMEM;
		goto out;
	}

	/* The sh Ether-specific entries in the device structure. */
	ndev->base_addr = res->start;
	devno = pdev->id;
	if (devno < 0)
		devno = 0;

	ndev->dma = -1;
2379 2380
	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
2381 2382 2383
		ret = -ENODEV;
		goto out_release;
	}
2384
	ndev->irq = ret;
2385 2386 2387 2388 2389 2390 2391

	SET_NETDEV_DEV(ndev, &pdev->dev);

	/* Fill in the fields of the device structure with ethernet values. */
	ether_setup(ndev);

	mdp = netdev_priv(ndev);
2392 2393
	mdp->num_tx_ring = TX_RING_SIZE;
	mdp->num_rx_ring = RX_RING_SIZE;
Y
Yoshihiro Shimoda 已提交
2394 2395 2396 2397 2398 2399 2400
	mdp->addr = ioremap(res->start, resource_size(res));
	if (mdp->addr == NULL) {
		ret = -ENOMEM;
		dev_err(&pdev->dev, "ioremap failed.\n");
		goto out_release;
	}

2401
	spin_lock_init(&mdp->lock);
2402 2403 2404
	mdp->pdev = pdev;
	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);
2405

2406
	pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
2407
	/* get PHY ID */
2408
	mdp->phy_id = pd->phy;
2409
	mdp->phy_interface = pd->phy_interface;
2410 2411
	/* EDMAC endian */
	mdp->edmac_endian = pd->edmac_endian;
2412 2413
	mdp->no_ether_link = pd->no_ether_link;
	mdp->ether_link_active_low = pd->ether_link_active_low;
2414
	mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2415

2416
	/* set cpu data */
2417 2418 2419
#if defined(SH_ETH_HAS_BOTH_MODULES)
	mdp->cd = sh_eth_get_cpu_data(mdp);
#else
2420
	mdp->cd = &sh_eth_my_cpu_data;
2421
#endif
2422 2423
	sh_eth_set_default_cpu_data(mdp->cd);

2424
	/* set function */
2425
	ndev->netdev_ops = &sh_eth_netdev_ops;
2426
	SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2427 2428
	ndev->watchdog_timeo = TX_TIMEOUT;

2429 2430
	/* debug message level */
	mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2431 2432

	/* read and set MAC address */
2433
	read_mac_address(ndev, pd->mac_addr);
2434

2435 2436 2437 2438 2439 2440
	/* ioremap the TSU registers */
	if (mdp->cd->tsu) {
		struct resource *rtsu;
		rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
		if (!rtsu) {
			dev_err(&pdev->dev, "Not found TSU resource\n");
2441
			ret = -ENODEV;
2442 2443 2444 2445
			goto out_release;
		}
		mdp->tsu_addr = ioremap(rtsu->start,
					resource_size(rtsu));
2446
		mdp->port = devno % 2;
2447
		ndev->features = NETIF_F_HW_VLAN_FILTER;
2448 2449
	}

2450 2451
	/* initialize first or needed device */
	if (!devno || pd->needs_init) {
2452 2453
		if (mdp->cd->chip_reset)
			mdp->cd->chip_reset(ndev);
2454

2455 2456 2457 2458
		if (mdp->cd->tsu) {
			/* TSU init (Init only)*/
			sh_eth_tsu_init(mdp);
		}
2459 2460 2461 2462 2463 2464 2465 2466
	}

	/* network device register */
	ret = register_netdev(ndev);
	if (ret)
		goto out_release;

	/* mdio bus init */
2467
	ret = sh_mdio_init(ndev, pdev->id, pd);
2468 2469 2470
	if (ret)
		goto out_unregister;

L
Lucas De Marchi 已提交
2471
	/* print device information */
2472 2473
	pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
	       (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2474 2475 2476 2477 2478 2479 2480 2481 2482 2483

	platform_set_drvdata(pdev, ndev);

	return ret;

out_unregister:
	unregister_netdev(ndev);

out_release:
	/* net_dev free */
Y
Yoshihiro Shimoda 已提交
2484 2485
	if (mdp && mdp->addr)
		iounmap(mdp->addr);
2486
	if (mdp && mdp->tsu_addr)
2487
		iounmap(mdp->tsu_addr);
2488 2489 2490 2491 2492 2493 2494 2495 2496 2497
	if (ndev)
		free_netdev(ndev);

out:
	return ret;
}

static int sh_eth_drv_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
2498
	struct sh_eth_private *mdp = netdev_priv(ndev);
2499

2500 2501
	if (mdp->cd->tsu)
		iounmap(mdp->tsu_addr);
2502 2503
	sh_mdio_release(ndev);
	unregister_netdev(ndev);
2504
	pm_runtime_disable(&pdev->dev);
Y
Yoshihiro Shimoda 已提交
2505
	iounmap(mdp->addr);
2506 2507 2508 2509 2510 2511
	free_netdev(ndev);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529
static int sh_eth_runtime_nop(struct device *dev)
{
	/*
	 * Runtime PM callback shared between ->runtime_suspend()
	 * and ->runtime_resume(). Simply returns success.
	 *
	 * This driver re-initializes all registers after
	 * pm_runtime_get_sync() anyway so there is no need
	 * to save and restore registers here.
	 */
	return 0;
}

static struct dev_pm_ops sh_eth_dev_pm_ops = {
	.runtime_suspend = sh_eth_runtime_nop,
	.runtime_resume = sh_eth_runtime_nop,
};

2530 2531 2532 2533 2534
static struct platform_driver sh_eth_driver = {
	.probe = sh_eth_drv_probe,
	.remove = sh_eth_drv_remove,
	.driver = {
		   .name = CARDNAME,
2535
		   .pm = &sh_eth_dev_pm_ops,
2536 2537 2538
	},
};

2539
module_platform_driver(sh_eth_driver);
2540 2541 2542 2543

MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
MODULE_LICENSE("GPL v2");