gemini.c 67.1 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542
// SPDX-License-Identifier: GPL-2.0
/* Ethernet device driver for Cortina Systems Gemini SoC
 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
 * Net Engine and Gigabit Ethernet MAC (GMAC)
 * This hardware contains a TCP Offload Engine (TOE) but currently the
 * driver does not make use of it.
 *
 * Authors:
 * Linus Walleij <linus.walleij@linaro.org>
 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
 * Paulius Zaleckas <paulius.zaleckas@gmail.com>
 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
 * Gary Chen & Ch Hsu Storlink Semiconductor
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <linux/reset.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/of_platform.h>
#include <linux/etherdevice.h>
#include <linux/if_vlan.h>
#include <linux/skbuff.h>
#include <linux/phy.h>
#include <linux/crc32.h>
#include <linux/ethtool.h>
#include <linux/tcp.h>
#include <linux/u64_stats_sync.h>

#include <linux/in.h>
#include <linux/ip.h>
#include <linux/ipv6.h>

#include "gemini.h"

#define DRV_NAME		"gmac-gemini"
#define DRV_VERSION		"1.0"

#define HSIZE_8			0x00
#define HSIZE_16		0x01
#define HSIZE_32		0x02

#define HBURST_SINGLE		0x00
#define HBURST_INCR		0x01
#define HBURST_INCR4		0x02
#define HBURST_INCR8		0x03

#define HPROT_DATA_CACHE	BIT(0)
#define HPROT_PRIVILIGED	BIT(1)
#define HPROT_BUFFERABLE	BIT(2)
#define HPROT_CACHABLE		BIT(3)

#define DEFAULT_RX_COALESCE_NSECS	0
#define DEFAULT_GMAC_RXQ_ORDER		9
#define DEFAULT_GMAC_TXQ_ORDER		8
#define DEFAULT_RX_BUF_ORDER		11
#define DEFAULT_NAPI_WEIGHT		64
#define TX_MAX_FRAGS			16
#define TX_QUEUE_NUM			1	/* max: 6 */
#define RX_MAX_ALLOC_ORDER		2

#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
		      GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
			      GMAC0_SWTQ00_FIN_INT_BIT)
#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)

#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
		NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
		NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)

/**
 * struct gmac_queue_page - page buffer per-page info
 */
struct gmac_queue_page {
	struct page *page;
	dma_addr_t mapping;
};

struct gmac_txq {
	struct gmac_txdesc *ring;
	struct sk_buff	**skb;
	unsigned int	cptr;
	unsigned int	noirq_packets;
};

struct gemini_ethernet;

struct gemini_ethernet_port {
	u8 id; /* 0 or 1 */

	struct gemini_ethernet *geth;
	struct net_device *netdev;
	struct device *dev;
	void __iomem *dma_base;
	void __iomem *gmac_base;
	struct clk *pclk;
	struct reset_control *reset;
	int irq;
	__le32 mac_addr[3];

	void __iomem		*rxq_rwptr;
	struct gmac_rxdesc	*rxq_ring;
	unsigned int		rxq_order;

	struct napi_struct	napi;
	struct hrtimer		rx_coalesce_timer;
	unsigned int		rx_coalesce_nsecs;
	unsigned int		freeq_refill;
	struct gmac_txq		txq[TX_QUEUE_NUM];
	unsigned int		txq_order;
	unsigned int		irq_every_tx_packets;

	dma_addr_t		rxq_dma_base;
	dma_addr_t		txq_dma_base;

	unsigned int		msg_enable;
	spinlock_t		config_lock; /* Locks config register */

	struct u64_stats_sync	tx_stats_syncp;
	struct u64_stats_sync	rx_stats_syncp;
	struct u64_stats_sync	ir_stats_syncp;

	struct rtnl_link_stats64 stats;
	u64			hw_stats[RX_STATS_NUM];
	u64			rx_stats[RX_STATUS_NUM];
	u64			rx_csum_stats[RX_CHKSUM_NUM];
	u64			rx_napi_exits;
	u64			tx_frag_stats[TX_MAX_FRAGS];
	u64			tx_frags_linearized;
	u64			tx_hw_csummed;
};

struct gemini_ethernet {
	struct device *dev;
	void __iomem *base;
	struct gemini_ethernet_port *port0;
	struct gemini_ethernet_port *port1;

	spinlock_t	irq_lock; /* Locks IRQ-related registers */
	unsigned int	freeq_order;
	unsigned int	freeq_frag_order;
	struct gmac_rxdesc *freeq_ring;
	dma_addr_t	freeq_dma_base;
	struct gmac_queue_page	*freeq_pages;
	unsigned int	num_freeq_pages;
	spinlock_t	freeq_lock; /* Locks queue from reentrance */
};

#define GMAC_STATS_NUM	( \
	RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
	TX_MAX_FRAGS + 2)

static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
	"GMAC_IN_DISCARDS",
	"GMAC_IN_ERRORS",
	"GMAC_IN_MCAST",
	"GMAC_IN_BCAST",
	"GMAC_IN_MAC1",
	"GMAC_IN_MAC2",
	"RX_STATUS_GOOD_FRAME",
	"RX_STATUS_TOO_LONG_GOOD_CRC",
	"RX_STATUS_RUNT_FRAME",
	"RX_STATUS_SFD_NOT_FOUND",
	"RX_STATUS_CRC_ERROR",
	"RX_STATUS_TOO_LONG_BAD_CRC",
	"RX_STATUS_ALIGNMENT_ERROR",
	"RX_STATUS_TOO_LONG_BAD_ALIGN",
	"RX_STATUS_RX_ERR",
	"RX_STATUS_DA_FILTERED",
	"RX_STATUS_BUFFER_FULL",
	"RX_STATUS_11",
	"RX_STATUS_12",
	"RX_STATUS_13",
	"RX_STATUS_14",
	"RX_STATUS_15",
	"RX_CHKSUM_IP_UDP_TCP_OK",
	"RX_CHKSUM_IP_OK_ONLY",
	"RX_CHKSUM_NONE",
	"RX_CHKSUM_3",
	"RX_CHKSUM_IP_ERR_UNKNOWN",
	"RX_CHKSUM_IP_ERR",
	"RX_CHKSUM_TCP_UDP_ERR",
	"RX_CHKSUM_7",
	"RX_NAPI_EXITS",
	"TX_FRAGS[1]",
	"TX_FRAGS[2]",
	"TX_FRAGS[3]",
	"TX_FRAGS[4]",
	"TX_FRAGS[5]",
	"TX_FRAGS[6]",
	"TX_FRAGS[7]",
	"TX_FRAGS[8]",
	"TX_FRAGS[9]",
	"TX_FRAGS[10]",
	"TX_FRAGS[11]",
	"TX_FRAGS[12]",
	"TX_FRAGS[13]",
	"TX_FRAGS[14]",
	"TX_FRAGS[15]",
	"TX_FRAGS[16+]",
	"TX_FRAGS_LINEARIZED",
	"TX_HW_CSUMMED",
};

static void gmac_dump_dma_state(struct net_device *netdev);

static void gmac_update_config0_reg(struct net_device *netdev,
				    u32 val, u32 vmask)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&port->config_lock, flags);

	reg = readl(port->gmac_base + GMAC_CONFIG0);
	reg = (reg & ~vmask) | val;
	writel(reg, port->gmac_base + GMAC_CONFIG0);

	spin_unlock_irqrestore(&port->config_lock, flags);
}

static void gmac_enable_tx_rx(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&port->config_lock, flags);

	reg = readl(port->gmac_base + GMAC_CONFIG0);
	reg &= ~CONFIG0_TX_RX_DISABLE;
	writel(reg, port->gmac_base + GMAC_CONFIG0);

	spin_unlock_irqrestore(&port->config_lock, flags);
}

static void gmac_disable_tx_rx(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&port->config_lock, flags);

	val = readl(port->gmac_base + GMAC_CONFIG0);
	val |= CONFIG0_TX_RX_DISABLE;
	writel(val, port->gmac_base + GMAC_CONFIG0);

	spin_unlock_irqrestore(&port->config_lock, flags);

	mdelay(10);	/* let GMAC consume packet */
}

static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&port->config_lock, flags);

	val = readl(port->gmac_base + GMAC_CONFIG0);
	val &= ~CONFIG0_FLOW_CTL;
	if (tx)
		val |= CONFIG0_FLOW_TX;
	if (rx)
		val |= CONFIG0_FLOW_RX;
	writel(val, port->gmac_base + GMAC_CONFIG0);

	spin_unlock_irqrestore(&port->config_lock, flags);
}

static void gmac_speed_set(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct phy_device *phydev = netdev->phydev;
	union gmac_status status, old_status;
	int pause_tx = 0;
	int pause_rx = 0;

	status.bits32 = readl(port->gmac_base + GMAC_STATUS);
	old_status.bits32 = status.bits32;
	status.bits.link = phydev->link;
	status.bits.duplex = phydev->duplex;

	switch (phydev->speed) {
	case 1000:
		status.bits.speed = GMAC_SPEED_1000;
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
			status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
		netdev_info(netdev, "connect to RGMII @ 1Gbit\n");
		break;
	case 100:
		status.bits.speed = GMAC_SPEED_100;
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
			status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
		netdev_info(netdev, "connect to RGMII @ 100 Mbit\n");
		break;
	case 10:
		status.bits.speed = GMAC_SPEED_10;
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
			status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
		netdev_info(netdev, "connect to RGMII @ 10 Mbit\n");
		break;
	default:
		netdev_warn(netdev, "Not supported PHY speed (%d)\n",
			    phydev->speed);
	}

	if (phydev->duplex == DUPLEX_FULL) {
		u16 lcladv = phy_read(phydev, MII_ADVERTISE);
		u16 rmtadv = phy_read(phydev, MII_LPA);
		u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);

		if (cap & FLOW_CTRL_RX)
			pause_rx = 1;
		if (cap & FLOW_CTRL_TX)
			pause_tx = 1;
	}

	gmac_set_flow_control(netdev, pause_tx, pause_rx);

	if (old_status.bits32 == status.bits32)
		return;

	if (netif_msg_link(port)) {
		phy_print_status(phydev);
		netdev_info(netdev, "link flow control: %s\n",
			    phydev->pause
			    ? (phydev->asym_pause ? "tx" : "both")
			    : (phydev->asym_pause ? "rx" : "none")
		);
	}

	gmac_disable_tx_rx(netdev);
	writel(status.bits32, port->gmac_base + GMAC_STATUS);
	gmac_enable_tx_rx(netdev);
}

static int gmac_setup_phy(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	union gmac_status status = { .bits32 = 0 };
	struct device *dev = port->dev;
	struct phy_device *phy;

	phy = of_phy_get_and_connect(netdev,
				     dev->of_node,
				     gmac_speed_set);
	if (!phy)
		return -ENODEV;
	netdev->phydev = phy;

	netdev_info(netdev, "connected to PHY \"%s\"\n",
		    phydev_name(phy));
	phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n",
			   (unsigned long)phy->phy_id,
			   phy_modes(phy->interface));

	phy->supported &= PHY_GBIT_FEATURES;
	phy->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
	phy->advertising = phy->supported;

	/* set PHY interface type */
	switch (phy->interface) {
	case PHY_INTERFACE_MODE_MII:
		netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
		status.bits.mii_rmii = GMAC_PHY_MII;
		netdev_info(netdev, "connect to MII\n");
		break;
	case PHY_INTERFACE_MODE_GMII:
		netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
		status.bits.mii_rmii = GMAC_PHY_GMII;
		netdev_info(netdev, "connect to GMII\n");
		break;
	case PHY_INTERFACE_MODE_RGMII:
		dev_info(dev, "set GMAC0 and GMAC1 to MII/RGMII mode\n");
		status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
		netdev_info(netdev, "connect to RGMII\n");
		break;
	default:
		netdev_err(netdev, "Unsupported MII interface\n");
		phy_disconnect(phy);
		netdev->phydev = NULL;
		return -EINVAL;
	}
	writel(status.bits32, port->gmac_base + GMAC_STATUS);

	return 0;
}

static int gmac_pick_rx_max_len(int max_l3_len)
{
	/* index = CONFIG_MAXLEN_XXX values */
	static const int max_len[8] = {
		1536, 1518, 1522, 1542,
		9212, 10236, 1518, 1518
	};
	int i, n = 5;

	max_l3_len += ETH_HLEN + VLAN_HLEN;

	if (max_l3_len > max_len[n])
		return -1;

	for (i = 0; i < 5; i++) {
		if (max_len[i] >= max_l3_len && max_len[i] < max_len[n])
			n = i;
	}

	return n;
}

static int gmac_init(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	union gmac_config0 config0 = { .bits = {
		.dis_tx = 1,
		.dis_rx = 1,
		.ipv4_rx_chksum = 1,
		.ipv6_rx_chksum = 1,
		.rx_err_detect = 1,
		.rgmm_edge = 1,
		.port0_chk_hwq = 1,
		.port1_chk_hwq = 1,
		.port0_chk_toeq = 1,
		.port1_chk_toeq = 1,
		.port0_chk_classq = 1,
		.port1_chk_classq = 1,
	} };
	union gmac_ahb_weight ahb_weight = { .bits = {
		.rx_weight = 1,
		.tx_weight = 1,
		.hash_weight = 1,
		.pre_req = 0x1f,
		.tq_dv_threshold = 0,
	} };
	union gmac_tx_wcr0 hw_weigh = { .bits = {
		.hw_tq3 = 1,
		.hw_tq2 = 1,
		.hw_tq1 = 1,
		.hw_tq0 = 1,
	} };
	union gmac_tx_wcr1 sw_weigh = { .bits = {
		.sw_tq5 = 1,
		.sw_tq4 = 1,
		.sw_tq3 = 1,
		.sw_tq2 = 1,
		.sw_tq1 = 1,
		.sw_tq0 = 1,
	} };
	union gmac_config1 config1 = { .bits = {
		.set_threshold = 16,
		.rel_threshold = 24,
	} };
	union gmac_config2 config2 = { .bits = {
		.set_threshold = 16,
		.rel_threshold = 32,
	} };
	union gmac_config3 config3 = { .bits = {
		.set_threshold = 0,
		.rel_threshold = 0,
	} };
	union gmac_config0 tmp;
	u32 val;

	config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
	tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
	config0.bits.reserved = tmp.bits.reserved;
	writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
	writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
	writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
	writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);

	val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
	writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);

	writel(hw_weigh.bits32,
	       port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
	writel(sw_weigh.bits32,
	       port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);

	port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
	port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
	port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;

	/* Mark every quarter of the queue a packet for interrupt
	 * in order to be able to wake up the queue if it was stopped
	 */
	port->irq_every_tx_packets = 1 << (port->txq_order - 2);

	return 0;
}

static void gmac_uninit(struct net_device *netdev)
{
	if (netdev->phydev)
		phy_disconnect(netdev->phydev);
}

static int gmac_setup_txqs(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned int n_txq = netdev->num_tx_queues;
	struct gemini_ethernet *geth = port->geth;
	size_t entries = 1 << port->txq_order;
	struct gmac_txq *txq = port->txq;
	struct gmac_txdesc *desc_ring;
	size_t len = n_txq * entries;
	struct sk_buff **skb_tab;
	void __iomem *rwptr_reg;
	unsigned int r;
	int i;

	rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;

	skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
	if (!skb_tab)
		return -ENOMEM;

	desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
				       &port->txq_dma_base, GFP_KERNEL);

	if (!desc_ring) {
		kfree(skb_tab);
		return -ENOMEM;
	}

	if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
		dev_warn(geth->dev, "TX queue base it not aligned\n");
I
Igor Pylypiv 已提交
543
		kfree(skb_tab);
544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594
		return -ENOMEM;
	}

	writel(port->txq_dma_base | port->txq_order,
	       port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);

	for (i = 0; i < n_txq; i++) {
		txq->ring = desc_ring;
		txq->skb = skb_tab;
		txq->noirq_packets = 0;

		r = readw(rwptr_reg);
		rwptr_reg += 2;
		writew(r, rwptr_reg);
		rwptr_reg += 2;
		txq->cptr = r;

		txq++;
		desc_ring += entries;
		skb_tab += entries;
	}

	return 0;
}

static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
			   unsigned int r)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned int m = (1 << port->txq_order) - 1;
	struct gemini_ethernet *geth = port->geth;
	unsigned int c = txq->cptr;
	union gmac_txdesc_0 word0;
	union gmac_txdesc_1 word1;
	unsigned int hwchksum = 0;
	unsigned long bytes = 0;
	struct gmac_txdesc *txd;
	unsigned short nfrags;
	unsigned int errs = 0;
	unsigned int pkts = 0;
	unsigned int word3;
	dma_addr_t mapping;

	if (c == r)
		return;

	while (c != r) {
		txd = txq->ring + c;
		word0 = txd->word0;
		word1 = txd->word1;
		mapping = txd->word2.buf_adr;
		word3 = txd->word3.bits32;

		dma_unmap_single(geth->dev, mapping,
				 word0.bits.buffer_size, DMA_TO_DEVICE);

		if (word3 & EOF_BIT)
			dev_kfree_skb(txq->skb[c]);

		c++;
		c &= m;

		if (!(word3 & SOF_BIT))
			continue;

		if (!word0.bits.status_tx_ok) {
			errs++;
			continue;
		}

		pkts++;
		bytes += txd->word1.bits.byte_count;

		if (word1.bits32 & TSS_CHECKUM_ENABLE)
			hwchksum++;

		nfrags = word0.bits.desc_count - 1;
		if (nfrags) {
			if (nfrags >= TX_MAX_FRAGS)
				nfrags = TX_MAX_FRAGS - 1;

			u64_stats_update_begin(&port->tx_stats_syncp);
			port->tx_frag_stats[nfrags]++;
			u64_stats_update_end(&port->ir_stats_syncp);
		}
	}

	u64_stats_update_begin(&port->ir_stats_syncp);
	port->stats.tx_errors += errs;
	port->stats.tx_packets += pkts;
	port->stats.tx_bytes += bytes;
	port->tx_hw_csummed += hwchksum;
	u64_stats_update_end(&port->ir_stats_syncp);

	txq->cptr = c;
}

static void gmac_cleanup_txqs(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned int n_txq = netdev->num_tx_queues;
	struct gemini_ethernet *geth = port->geth;
	void __iomem *rwptr_reg;
	unsigned int r, i;

	rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;

	for (i = 0; i < n_txq; i++) {
		r = readw(rwptr_reg);
		rwptr_reg += 2;
		writew(r, rwptr_reg);
		rwptr_reg += 2;

		gmac_clean_txq(netdev, port->txq + i, r);
	}
	writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);

	kfree(port->txq->skb);
	dma_free_coherent(geth->dev,
			  n_txq * sizeof(*port->txq->ring) << port->txq_order,
			  port->txq->ring, port->txq_dma_base);
}

static int gmac_setup_rxq(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct gemini_ethernet *geth = port->geth;
	struct nontoe_qhdr __iomem *qhdr;

	qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
	port->rxq_rwptr = &qhdr->word1;

	/* Remap a slew of memory to use for the RX queue */
	port->rxq_ring = dma_alloc_coherent(geth->dev,
				sizeof(*port->rxq_ring) << port->rxq_order,
				&port->rxq_dma_base, GFP_KERNEL);
	if (!port->rxq_ring)
		return -ENOMEM;
	if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
		dev_warn(geth->dev, "RX queue base it not aligned\n");
		return -ENOMEM;
	}

	writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
	writel(0, port->rxq_rwptr);
	return 0;
}

static struct gmac_queue_page *
gmac_get_queue_page(struct gemini_ethernet *geth,
		    struct gemini_ethernet_port *port,
		    dma_addr_t addr)
{
	struct gmac_queue_page *gpage;
	dma_addr_t mapping;
	int i;

	/* Only look for even pages */
	mapping = addr & PAGE_MASK;

	if (!geth->freeq_pages) {
		dev_err(geth->dev, "try to get page with no page list\n");
		return NULL;
	}

	/* Look up a ring buffer page from virtual mapping */
	for (i = 0; i < geth->num_freeq_pages; i++) {
		gpage = &geth->freeq_pages[i];
		if (gpage->mapping == mapping)
			return gpage;
	}

	return NULL;
}

static void gmac_cleanup_rxq(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct gemini_ethernet *geth = port->geth;
	struct gmac_rxdesc *rxd = port->rxq_ring;
	static struct gmac_queue_page *gpage;
	struct nontoe_qhdr __iomem *qhdr;
	void __iomem *dma_reg;
	void __iomem *ptr_reg;
	dma_addr_t mapping;
	union dma_rwptr rw;
	unsigned int r, w;

	qhdr = geth->base +
		TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
	dma_reg = &qhdr->word0;
	ptr_reg = &qhdr->word1;

	rw.bits32 = readl(ptr_reg);
	r = rw.bits.rptr;
	w = rw.bits.wptr;
	writew(r, ptr_reg + 2);

	writel(0, dma_reg);

	/* Loop from read pointer to write pointer of the RX queue
	 * and free up all pages by the queue.
	 */
	while (r != w) {
		mapping = rxd[r].word2.buf_adr;
		r++;
		r &= ((1 << port->rxq_order) - 1);

		if (!mapping)
			continue;

		/* Freeq pointers are one page off */
		gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
		if (!gpage) {
			dev_err(geth->dev, "could not find page\n");
			continue;
		}
		/* Release the RX queue reference to the page */
		put_page(gpage->page);
	}

	dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
			  port->rxq_ring, port->rxq_dma_base);
}

static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
					      int pn)
{
	struct gmac_rxdesc *freeq_entry;
	struct gmac_queue_page *gpage;
	unsigned int fpp_order;
	unsigned int frag_len;
	dma_addr_t mapping;
	struct page *page;
	int i;

	/* First allocate and DMA map a single page */
	page = alloc_page(GFP_ATOMIC);
	if (!page)
		return NULL;

	mapping = dma_map_single(geth->dev, page_address(page),
				 PAGE_SIZE, DMA_FROM_DEVICE);
	if (dma_mapping_error(geth->dev, mapping)) {
		put_page(page);
		return NULL;
	}

	/* The assign the page mapping (physical address) to the buffer address
	 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
	 * 4k), and the default RX frag order is 11 (fragments are up 20 2048
	 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
	 * each page normally needs two entries in the queue.
	 */
	frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
	fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
	freeq_entry = geth->freeq_ring + (pn << fpp_order);
	dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
		 pn, frag_len, (1 << fpp_order), freeq_entry);
	for (i = (1 << fpp_order); i > 0; i--) {
		freeq_entry->word2.buf_adr = mapping;
		freeq_entry++;
		mapping += frag_len;
	}

	/* If the freeq entry already has a page mapped, then unmap it. */
	gpage = &geth->freeq_pages[pn];
	if (gpage->page) {
		mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
		dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
		/* This should be the last reference to the page so it gets
		 * released
		 */
		put_page(gpage->page);
	}

	/* Then put our new mapping into the page table */
	dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
		pn, (unsigned int)mapping, page);
	gpage->mapping = mapping;
	gpage->page = page;

	return page;
}

/**
 * geth_fill_freeq() - Fill the freeq with empty fragments to use
 * @geth: the ethernet adapter
 * @refill: whether to reset the queue by filling in all freeq entries or
 * just refill it, usually the interrupt to refill the queue happens when
 * the queue is half empty.
 */
static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
{
	unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
	unsigned int count = 0;
	unsigned int pn, epn;
	unsigned long flags;
	union dma_rwptr rw;
	unsigned int m_pn;

	/* Mask for page */
	m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;

	spin_lock_irqsave(&geth->freeq_lock, flags);

	rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
	pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
	epn = (rw.bits.rptr >> fpp_order) - 1;
	epn &= m_pn;

	/* Loop over the freeq ring buffer entries */
	while (pn != epn) {
		struct gmac_queue_page *gpage;
		struct page *page;

		gpage = &geth->freeq_pages[pn];
		page = gpage->page;

		dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
			pn, page_ref_count(page), 1 << fpp_order);

		if (page_ref_count(page) > 1) {
			unsigned int fl = (pn - epn) & m_pn;

			if (fl > 64 >> fpp_order)
				break;

			page = geth_freeq_alloc_map_page(geth, pn);
			if (!page)
				break;
		}

		/* Add one reference per fragment in the page */
		page_ref_add(page, 1 << fpp_order);
		count += 1 << fpp_order;
		pn++;
		pn &= m_pn;
	}

	writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);

	spin_unlock_irqrestore(&geth->freeq_lock, flags);

	return count;
}

static int geth_setup_freeq(struct gemini_ethernet *geth)
{
	unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
	unsigned int frag_len = 1 << geth->freeq_frag_order;
	unsigned int len = 1 << geth->freeq_order;
	unsigned int pages = len >> fpp_order;
	union queue_threshold qt;
	union dma_skb_size skbsz;
	unsigned int filled;
	unsigned int pn;

	geth->freeq_ring = dma_alloc_coherent(geth->dev,
		sizeof(*geth->freeq_ring) << geth->freeq_order,
		&geth->freeq_dma_base, GFP_KERNEL);
	if (!geth->freeq_ring)
		return -ENOMEM;
	if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
		dev_warn(geth->dev, "queue ring base it not aligned\n");
		goto err_freeq;
	}

	/* Allocate a mapping to page look-up index */
	geth->freeq_pages = kzalloc(pages * sizeof(*geth->freeq_pages),
				   GFP_KERNEL);
	if (!geth->freeq_pages)
		goto err_freeq;
	geth->num_freeq_pages = pages;

	dev_info(geth->dev, "allocate %d pages for queue\n", pages);
	for (pn = 0; pn < pages; pn++)
		if (!geth_freeq_alloc_map_page(geth, pn))
			goto err_freeq_alloc;

	filled = geth_fill_freeq(geth, false);
	if (!filled)
		goto err_freeq_alloc;

	qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
	qt.bits.swfq_empty = 32;
	writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);

	skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
	writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
	writel(geth->freeq_dma_base | geth->freeq_order,
	       geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);

	return 0;

err_freeq_alloc:
	while (pn > 0) {
		struct gmac_queue_page *gpage;
		dma_addr_t mapping;

		--pn;
		mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
		dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
		gpage = &geth->freeq_pages[pn];
		put_page(gpage->page);
	}

	kfree(geth->freeq_pages);
err_freeq:
	dma_free_coherent(geth->dev,
			  sizeof(*geth->freeq_ring) << geth->freeq_order,
			  geth->freeq_ring, geth->freeq_dma_base);
	geth->freeq_ring = NULL;
	return -ENOMEM;
}

/**
 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
 * @geth: the Gemini global ethernet state
 */
static void geth_cleanup_freeq(struct gemini_ethernet *geth)
{
	unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
	unsigned int frag_len = 1 << geth->freeq_frag_order;
	unsigned int len = 1 << geth->freeq_order;
	unsigned int pages = len >> fpp_order;
	unsigned int pn;

	writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
	       geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
	writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);

	for (pn = 0; pn < pages; pn++) {
		struct gmac_queue_page *gpage;
		dma_addr_t mapping;

		mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
		dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);

		gpage = &geth->freeq_pages[pn];
		while (page_ref_count(gpage->page) > 0)
			put_page(gpage->page);
	}

	kfree(geth->freeq_pages);

	dma_free_coherent(geth->dev,
			  sizeof(*geth->freeq_ring) << geth->freeq_order,
			  geth->freeq_ring, geth->freeq_dma_base);
}

/**
 * geth_resize_freeq() - resize the software queue depth
 * @port: the port requesting the change
 *
 * This gets called at least once during probe() so the device queue gets
 * "resized" from the hardware defaults. Since both ports/net devices share
 * the same hardware queue, some synchronization between the ports is
 * needed.
 */
static int geth_resize_freeq(struct gemini_ethernet_port *port)
{
	struct gemini_ethernet *geth = port->geth;
	struct net_device *netdev = port->netdev;
	struct gemini_ethernet_port *other_port;
	struct net_device *other_netdev;
	unsigned int new_size = 0;
	unsigned int new_order;
	unsigned long flags;
	u32 en;
	int ret;

	if (netdev->dev_id == 0)
		other_netdev = geth->port1->netdev;
	else
		other_netdev = geth->port0->netdev;

	if (other_netdev && netif_running(other_netdev))
		return -EBUSY;

	new_size = 1 << (port->rxq_order + 1);
	netdev_dbg(netdev, "port %d size: %d order %d\n",
		   netdev->dev_id,
		   new_size,
		   port->rxq_order);
	if (other_netdev) {
		other_port = netdev_priv(other_netdev);
		new_size += 1 << (other_port->rxq_order + 1);
		netdev_dbg(other_netdev, "port %d size: %d order %d\n",
			   other_netdev->dev_id,
			   (1 << (other_port->rxq_order + 1)),
			   other_port->rxq_order);
	}

	new_order = min(15, ilog2(new_size - 1) + 1);
	dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
		new_size, new_order);
	if (geth->freeq_order == new_order)
		return 0;

	spin_lock_irqsave(&geth->irq_lock, flags);

	/* Disable the software queue IRQs */
	en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
	en &= ~SWFQ_EMPTY_INT_BIT;
	writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
	spin_unlock_irqrestore(&geth->irq_lock, flags);

	/* Drop the old queue */
	if (geth->freeq_ring)
		geth_cleanup_freeq(geth);

	/* Allocate a new queue with the desired order */
	geth->freeq_order = new_order;
	ret = geth_setup_freeq(geth);

	/* Restart the interrupts - NOTE if this is the first resize
	 * after probe(), this is where the interrupts get turned on
	 * in the first place.
	 */
	spin_lock_irqsave(&geth->irq_lock, flags);
	en |= SWFQ_EMPTY_INT_BIT;
	writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
	spin_unlock_irqrestore(&geth->irq_lock, flags);

	return ret;
}

static void gmac_tx_irq_enable(struct net_device *netdev,
			       unsigned int txq, int en)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct gemini_ethernet *geth = port->geth;
	u32 val, mask;

	netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);

	mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);

	if (en)
		writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);

	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
	val = en ? val | mask : val & ~mask;
	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
}

static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
{
	struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);

	gmac_tx_irq_enable(netdev, txq_num, 0);
	netif_tx_wake_queue(ntxq);
}

static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
			    struct gmac_txq *txq, unsigned short *desc)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct skb_shared_info *skb_si =  skb_shinfo(skb);
	unsigned short m = (1 << port->txq_order) - 1;
	short frag, last_frag = skb_si->nr_frags - 1;
	struct gemini_ethernet *geth = port->geth;
	unsigned int word1, word3, buflen;
	unsigned short w = *desc;
	struct gmac_txdesc *txd;
	skb_frag_t *skb_frag;
	dma_addr_t mapping;
	unsigned short mtu;
	void *buffer;

	mtu  = ETH_HLEN;
	mtu += netdev->mtu;
	if (skb->protocol == htons(ETH_P_8021Q))
		mtu += VLAN_HLEN;

	word1 = skb->len;
	word3 = SOF_BIT;

	if (word1 > mtu) {
		word1 |= TSS_MTU_ENABLE_BIT;
		word3 |= mtu;
	}

	if (skb->ip_summed != CHECKSUM_NONE) {
		int tcp = 0;

		if (skb->protocol == htons(ETH_P_IP)) {
			word1 |= TSS_IP_CHKSUM_BIT;
			tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
		} else { /* IPv6 */
			word1 |= TSS_IPV6_ENABLE_BIT;
			tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
		}

		word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
	}

	frag = -1;
	while (frag <= last_frag) {
		if (frag == -1) {
			buffer = skb->data;
			buflen = skb_headlen(skb);
		} else {
			skb_frag = skb_si->frags + frag;
			buffer = page_address(skb_frag_page(skb_frag)) +
				 skb_frag->page_offset;
			buflen = skb_frag->size;
		}

		if (frag == last_frag) {
			word3 |= EOF_BIT;
			txq->skb[w] = skb;
		}

		mapping = dma_map_single(geth->dev, buffer, buflen,
					 DMA_TO_DEVICE);
		if (dma_mapping_error(geth->dev, mapping))
			goto map_error;

		txd = txq->ring + w;
		txd->word0.bits32 = buflen;
		txd->word1.bits32 = word1;
		txd->word2.buf_adr = mapping;
		txd->word3.bits32 = word3;

		word3 &= MTU_SIZE_BIT_MASK;
		w++;
		w &= m;
		frag++;
	}

	*desc = w;
	return 0;

map_error:
	while (w != *desc) {
		w--;
		w &= m;

		dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
			       txq->ring[w].word0.bits.buffer_size,
			       DMA_TO_DEVICE);
	}
	return -ENOMEM;
}

static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned short m = (1 << port->txq_order) - 1;
	struct netdev_queue *ntxq;
	unsigned short r, w, d;
	void __iomem *ptr_reg;
	struct gmac_txq *txq;
	int txq_num, nfrags;
	union dma_rwptr rw;

	SKB_FRAG_ASSERT(skb);

	if (skb->len >= 0x10000)
		goto out_drop_free;

	txq_num = skb_get_queue_mapping(skb);
	ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
	txq = &port->txq[txq_num];
	ntxq = netdev_get_tx_queue(netdev, txq_num);
	nfrags = skb_shinfo(skb)->nr_frags;

	rw.bits32 = readl(ptr_reg);
	r = rw.bits.rptr;
	w = rw.bits.wptr;

	d = txq->cptr - w - 1;
	d &= m;

	if (d < nfrags + 2) {
		gmac_clean_txq(netdev, txq, r);
		d = txq->cptr - w - 1;
		d &= m;

		if (d < nfrags + 2) {
			netif_tx_stop_queue(ntxq);

			d = txq->cptr + nfrags + 16;
			d &= m;
			txq->ring[d].word3.bits.eofie = 1;
			gmac_tx_irq_enable(netdev, txq_num, 1);

			u64_stats_update_begin(&port->tx_stats_syncp);
			netdev->stats.tx_fifo_errors++;
			u64_stats_update_end(&port->tx_stats_syncp);
			return NETDEV_TX_BUSY;
		}
	}

	if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
		if (skb_linearize(skb))
			goto out_drop;

		u64_stats_update_begin(&port->tx_stats_syncp);
		port->tx_frags_linearized++;
		u64_stats_update_end(&port->tx_stats_syncp);

		if (gmac_map_tx_bufs(netdev, skb, txq, &w))
			goto out_drop_free;
	}

	writew(w, ptr_reg + 2);

	gmac_clean_txq(netdev, txq, r);
	return NETDEV_TX_OK;

out_drop_free:
	dev_kfree_skb(skb);
out_drop:
	u64_stats_update_begin(&port->tx_stats_syncp);
	port->stats.tx_dropped++;
	u64_stats_update_end(&port->tx_stats_syncp);
	return NETDEV_TX_OK;
}

static void gmac_tx_timeout(struct net_device *netdev)
{
	netdev_err(netdev, "Tx timeout\n");
	gmac_dump_dma_state(netdev);
}

static void gmac_enable_irq(struct net_device *netdev, int enable)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct gemini_ethernet *geth = port->geth;
	unsigned long flags;
	u32 val, mask;

	netdev_info(netdev, "%s device %d %s\n", __func__,
		    netdev->dev_id, enable ? "enable" : "disable");
	spin_lock_irqsave(&geth->irq_lock, flags);

	mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
	val = enable ? (val | mask) : (val & ~mask);
	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);

	mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
	val = enable ? (val | mask) : (val & ~mask);
	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);

	mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
	val = enable ? (val | mask) : (val & ~mask);
	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);

	spin_unlock_irqrestore(&geth->irq_lock, flags);
}

static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct gemini_ethernet *geth = port->geth;
	unsigned long flags;
	u32 val, mask;

	netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
		   enable ? "enable" : "disable");
	spin_lock_irqsave(&geth->irq_lock, flags);
	mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;

	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
	val = enable ? (val | mask) : (val & ~mask);
	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);

	spin_unlock_irqrestore(&geth->irq_lock, flags);
}

static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
					      union gmac_rxdesc_0 word0,
					      unsigned int frame_len)
{
	unsigned int rx_csum = word0.bits.chksum_status;
	unsigned int rx_status = word0.bits.status;
	struct sk_buff *skb = NULL;

	port->rx_stats[rx_status]++;
	port->rx_csum_stats[rx_csum]++;

	if (word0.bits.derr || word0.bits.perr ||
	    rx_status || frame_len < ETH_ZLEN ||
	    rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
		port->stats.rx_errors++;

		if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
			port->stats.rx_length_errors++;
		if (RX_ERROR_OVER(rx_status))
			port->stats.rx_over_errors++;
		if (RX_ERROR_CRC(rx_status))
			port->stats.rx_crc_errors++;
		if (RX_ERROR_FRAME(rx_status))
			port->stats.rx_frame_errors++;
		return NULL;
	}

	skb = napi_get_frags(&port->napi);
	if (!skb)
		goto update_exit;

	if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
		skb->ip_summed = CHECKSUM_UNNECESSARY;

update_exit:
	port->stats.rx_bytes += frame_len;
	port->stats.rx_packets++;
	return skb;
}

static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned short m = (1 << port->rxq_order) - 1;
	struct gemini_ethernet *geth = port->geth;
	void __iomem *ptr_reg = port->rxq_rwptr;
	unsigned int frame_len, frag_len;
	struct gmac_rxdesc *rx = NULL;
	struct gmac_queue_page *gpage;
	static struct sk_buff *skb;
	union gmac_rxdesc_0 word0;
	union gmac_rxdesc_1 word1;
	union gmac_rxdesc_3 word3;
	struct page *page = NULL;
	unsigned int page_offs;
	unsigned short r, w;
	union dma_rwptr rw;
	dma_addr_t mapping;
	int frag_nr = 0;

	rw.bits32 = readl(ptr_reg);
	/* Reset interrupt as all packages until here are taken into account */
	writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
	       geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
	r = rw.bits.rptr;
	w = rw.bits.wptr;

	while (budget && w != r) {
		rx = port->rxq_ring + r;
		word0 = rx->word0;
		word1 = rx->word1;
		mapping = rx->word2.buf_adr;
		word3 = rx->word3;

		r++;
		r &= m;

		frag_len = word0.bits.buffer_size;
		frame_len = word1.bits.byte_count;
		page_offs = mapping & ~PAGE_MASK;

		if (!mapping) {
			netdev_err(netdev,
				   "rxq[%u]: HW BUG: zero DMA desc\n", r);
			goto err_drop;
		}

		/* Freeq pointers are one page off */
		gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
		if (!gpage) {
			dev_err(geth->dev, "could not find mapping\n");
			continue;
		}
		page = gpage->page;

		if (word3.bits32 & SOF_BIT) {
			if (skb) {
				napi_free_frags(&port->napi);
				port->stats.rx_dropped++;
			}

			skb = gmac_skb_if_good_frame(port, word0, frame_len);
			if (!skb)
				goto err_drop;

			page_offs += NET_IP_ALIGN;
			frag_len -= NET_IP_ALIGN;
			frag_nr = 0;

		} else if (!skb) {
			put_page(page);
			continue;
		}

		if (word3.bits32 & EOF_BIT)
			frag_len = frame_len - skb->len;

		/* append page frag to skb */
		if (frag_nr == MAX_SKB_FRAGS)
			goto err_drop;

		if (frag_len == 0)
			netdev_err(netdev, "Received fragment with len = 0\n");

		skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
		skb->len += frag_len;
		skb->data_len += frag_len;
		skb->truesize += frag_len;
		frag_nr++;

		if (word3.bits32 & EOF_BIT) {
			napi_gro_frags(&port->napi);
			skb = NULL;
			--budget;
		}
		continue;

err_drop:
		if (skb) {
			napi_free_frags(&port->napi);
			skb = NULL;
		}

		if (mapping)
			put_page(page);

		port->stats.rx_dropped++;
	}

	writew(r, ptr_reg);
	return budget;
}

static int gmac_napi_poll(struct napi_struct *napi, int budget)
{
	struct gemini_ethernet_port *port = netdev_priv(napi->dev);
	struct gemini_ethernet *geth = port->geth;
	unsigned int freeq_threshold;
	unsigned int received;

	freeq_threshold = 1 << (geth->freeq_order - 1);
	u64_stats_update_begin(&port->rx_stats_syncp);

	received = gmac_rx(napi->dev, budget);
	if (received < budget) {
		napi_gro_flush(napi, false);
		napi_complete_done(napi, received);
		gmac_enable_rx_irq(napi->dev, 1);
		++port->rx_napi_exits;
	}

	port->freeq_refill += (budget - received);
	if (port->freeq_refill > freeq_threshold) {
		port->freeq_refill -= freeq_threshold;
		geth_fill_freeq(geth, true);
	}

	u64_stats_update_end(&port->rx_stats_syncp);
	return received;
}

static void gmac_dump_dma_state(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct gemini_ethernet *geth = port->geth;
	void __iomem *ptr_reg;
	u32 reg[5];

	/* Interrupt status */
	reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
	reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
	reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
	reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
	reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
	netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   reg[0], reg[1], reg[2], reg[3], reg[4]);

	/* Interrupt enable */
	reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
	reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
	reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
	reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
	reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
	netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   reg[0], reg[1], reg[2], reg[3], reg[4]);

	/* RX DMA status */
	reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
	reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
	reg[2] = GET_RPTR(port->rxq_rwptr);
	reg[3] = GET_WPTR(port->rxq_rwptr);
	netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
		   reg[0], reg[1], reg[2], reg[3]);

	reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
	reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
	reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
	reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
	netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   reg[0], reg[1], reg[2], reg[3]);

	/* TX DMA status */
	ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;

	reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
	reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
	reg[2] = GET_RPTR(ptr_reg);
	reg[3] = GET_WPTR(ptr_reg);
	netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
		   reg[0], reg[1], reg[2], reg[3]);

	reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
	reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
	reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
	reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
	netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   reg[0], reg[1], reg[2], reg[3]);

	/* FREE queues status */
	ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;

	reg[0] = GET_RPTR(ptr_reg);
	reg[1] = GET_WPTR(ptr_reg);

	ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;

	reg[2] = GET_RPTR(ptr_reg);
	reg[3] = GET_WPTR(ptr_reg);
	netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
		   reg[0], reg[1], reg[2], reg[3]);
}

static void gmac_update_hw_stats(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned int rx_discards, rx_mcast, rx_bcast;
	struct gemini_ethernet *geth = port->geth;
	unsigned long flags;

	spin_lock_irqsave(&geth->irq_lock, flags);
	u64_stats_update_begin(&port->ir_stats_syncp);

	rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
	port->hw_stats[0] += rx_discards;
	port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
	rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
	port->hw_stats[2] += rx_mcast;
	rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
	port->hw_stats[3] += rx_bcast;
	port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
	port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);

	port->stats.rx_missed_errors += rx_discards;
	port->stats.multicast += rx_mcast;
	port->stats.multicast += rx_bcast;

	writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
	       geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);

	u64_stats_update_end(&port->ir_stats_syncp);
	spin_unlock_irqrestore(&geth->irq_lock, flags);
}

/**
 * gmac_get_intr_flags() - get interrupt status flags for a port from
 * @netdev: the net device for the port to get flags from
 * @i: the interrupt status register 0..4
 */
static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	struct gemini_ethernet *geth = port->geth;
	void __iomem *irqif_reg, *irqen_reg;
	unsigned int offs, val;

	/* Calculate the offset using the stride of the status registers */
	offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
		    GLOBAL_INTERRUPT_STATUS_0_REG);

	irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
	irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;

	val = readl(irqif_reg) & readl(irqen_reg);
	return val;
}

static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
{
	struct gemini_ethernet_port *port =
		container_of(timer, struct gemini_ethernet_port,
			     rx_coalesce_timer);

	napi_schedule(&port->napi);
	return HRTIMER_NORESTART;
}

static irqreturn_t gmac_irq(int irq, void *data)
{
	struct gemini_ethernet_port *port;
	struct net_device *netdev = data;
	struct gemini_ethernet *geth;
	u32 val, orr = 0;

	port = netdev_priv(netdev);
	geth = port->geth;

	val = gmac_get_intr_flags(netdev, 0);
	orr |= val;

	if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
		/* Oh, crap */
		netdev_err(netdev, "hw failure/sw bug\n");
		gmac_dump_dma_state(netdev);

		/* don't know how to recover, just reduce losses */
		gmac_enable_irq(netdev, 0);
		return IRQ_HANDLED;
	}

	if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
		gmac_tx_irq(netdev, 0);

	val = gmac_get_intr_flags(netdev, 1);
	orr |= val;

	if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
		gmac_enable_rx_irq(netdev, 0);

		if (!port->rx_coalesce_nsecs) {
			napi_schedule(&port->napi);
		} else {
			ktime_t ktime;

			ktime = ktime_set(0, port->rx_coalesce_nsecs);
			hrtimer_start(&port->rx_coalesce_timer, ktime,
				      HRTIMER_MODE_REL);
		}
	}

	val = gmac_get_intr_flags(netdev, 4);
	orr |= val;

	if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
		gmac_update_hw_stats(netdev);

	if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
		writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
		       geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);

		spin_lock(&geth->irq_lock);
		u64_stats_update_begin(&port->ir_stats_syncp);
		++port->stats.rx_fifo_errors;
		u64_stats_update_end(&port->ir_stats_syncp);
		spin_unlock(&geth->irq_lock);
	}

	return orr ? IRQ_HANDLED : IRQ_NONE;
}

static void gmac_start_dma(struct gemini_ethernet_port *port)
{
	void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
	union gmac_dma_ctrl dma_ctrl;

	dma_ctrl.bits32 = readl(dma_ctrl_reg);
	dma_ctrl.bits.rd_enable = 1;
	dma_ctrl.bits.td_enable = 1;
	dma_ctrl.bits.loopback = 0;
	dma_ctrl.bits.drop_small_ack = 0;
	dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
	dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
	dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
	dma_ctrl.bits.rd_bus = HSIZE_8;
	dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
	dma_ctrl.bits.td_burst_size = HBURST_INCR8;
	dma_ctrl.bits.td_bus = HSIZE_8;

	writel(dma_ctrl.bits32, dma_ctrl_reg);
}

static void gmac_stop_dma(struct gemini_ethernet_port *port)
{
	void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
	union gmac_dma_ctrl dma_ctrl;

	dma_ctrl.bits32 = readl(dma_ctrl_reg);
	dma_ctrl.bits.rd_enable = 0;
	dma_ctrl.bits.td_enable = 0;
	writel(dma_ctrl.bits32, dma_ctrl_reg);
}

static int gmac_open(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	int err;

	if (!netdev->phydev) {
		err = gmac_setup_phy(netdev);
		if (err) {
			netif_err(port, ifup, netdev,
				  "PHY init failed: %d\n", err);
			return err;
		}
	}

	err = request_irq(netdev->irq, gmac_irq,
			  IRQF_SHARED, netdev->name, netdev);
	if (err) {
		netdev_err(netdev, "no IRQ\n");
		return err;
	}

	netif_carrier_off(netdev);
	phy_start(netdev->phydev);

	err = geth_resize_freeq(port);
	if (err) {
		netdev_err(netdev, "could not resize freeq\n");
		goto err_stop_phy;
	}

	err = gmac_setup_rxq(netdev);
	if (err) {
		netdev_err(netdev, "could not setup RXQ\n");
		goto err_stop_phy;
	}

	err = gmac_setup_txqs(netdev);
	if (err) {
		netdev_err(netdev, "could not setup TXQs\n");
		gmac_cleanup_rxq(netdev);
		goto err_stop_phy;
	}

	napi_enable(&port->napi);

	gmac_start_dma(port);
	gmac_enable_irq(netdev, 1);
	gmac_enable_tx_rx(netdev);
	netif_tx_start_all_queues(netdev);

	hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
		     HRTIMER_MODE_REL);
	port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;

	netdev_info(netdev, "opened\n");

	return 0;

err_stop_phy:
	phy_stop(netdev->phydev);
	free_irq(netdev->irq, netdev);
	return err;
}

static int gmac_stop(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);

	hrtimer_cancel(&port->rx_coalesce_timer);
	netif_tx_stop_all_queues(netdev);
	gmac_disable_tx_rx(netdev);
	gmac_stop_dma(port);
	napi_disable(&port->napi);

	gmac_enable_irq(netdev, 0);
	gmac_cleanup_rxq(netdev);
	gmac_cleanup_txqs(netdev);

	phy_stop(netdev->phydev);
	free_irq(netdev->irq, netdev);

	gmac_update_hw_stats(netdev);
	return 0;
}

static void gmac_set_rx_mode(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	union gmac_rx_fltr filter = { .bits = {
		.broadcast = 1,
		.multicast = 1,
		.unicast = 1,
	} };
	struct netdev_hw_addr *ha;
	unsigned int bit_nr;
	u32 mc_filter[2];

	mc_filter[1] = 0;
	mc_filter[0] = 0;

	if (netdev->flags & IFF_PROMISC) {
		filter.bits.error = 1;
		filter.bits.promiscuous = 1;
		mc_filter[1] = ~0;
		mc_filter[0] = ~0;
	} else if (netdev->flags & IFF_ALLMULTI) {
		mc_filter[1] = ~0;
		mc_filter[0] = ~0;
	} else {
		netdev_for_each_mc_addr(ha, netdev) {
			bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
		}
	}

	writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
	writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
	writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
}

static void gmac_write_mac_address(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	__le32 addr[3];

	memset(addr, 0, sizeof(addr));
	memcpy(addr, netdev->dev_addr, ETH_ALEN);

	writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
	writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
	writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
}

static int gmac_set_mac_address(struct net_device *netdev, void *addr)
{
	struct sockaddr *sa = addr;

	memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
	gmac_write_mac_address(netdev);

	return 0;
}

static void gmac_clear_hw_stats(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);

	readl(port->gmac_base + GMAC_IN_DISCARDS);
	readl(port->gmac_base + GMAC_IN_ERRORS);
	readl(port->gmac_base + GMAC_IN_MCAST);
	readl(port->gmac_base + GMAC_IN_BCAST);
	readl(port->gmac_base + GMAC_IN_MAC1);
	readl(port->gmac_base + GMAC_IN_MAC2);
}

static void gmac_get_stats64(struct net_device *netdev,
			     struct rtnl_link_stats64 *stats)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned int start;

	gmac_update_hw_stats(netdev);

	/* Racing with RX NAPI */
	do {
		start = u64_stats_fetch_begin(&port->rx_stats_syncp);

		stats->rx_packets = port->stats.rx_packets;
		stats->rx_bytes = port->stats.rx_bytes;
		stats->rx_errors = port->stats.rx_errors;
		stats->rx_dropped = port->stats.rx_dropped;

		stats->rx_length_errors = port->stats.rx_length_errors;
		stats->rx_over_errors = port->stats.rx_over_errors;
		stats->rx_crc_errors = port->stats.rx_crc_errors;
		stats->rx_frame_errors = port->stats.rx_frame_errors;

	} while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));

	/* Racing with MIB and TX completion interrupts */
	do {
		start = u64_stats_fetch_begin(&port->ir_stats_syncp);

		stats->tx_errors = port->stats.tx_errors;
		stats->tx_packets = port->stats.tx_packets;
		stats->tx_bytes = port->stats.tx_bytes;

		stats->multicast = port->stats.multicast;
		stats->rx_missed_errors = port->stats.rx_missed_errors;
		stats->rx_fifo_errors = port->stats.rx_fifo_errors;

	} while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));

	/* Racing with hard_start_xmit */
	do {
		start = u64_stats_fetch_begin(&port->tx_stats_syncp);

		stats->tx_dropped = port->stats.tx_dropped;

	} while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));

	stats->rx_dropped += stats->rx_missed_errors;
}

static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
{
	int max_len = gmac_pick_rx_max_len(new_mtu);

	if (max_len < 0)
		return -EINVAL;

	gmac_disable_tx_rx(netdev);

	netdev->mtu = new_mtu;
	gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
				CONFIG0_MAXLEN_MASK);

	netdev_update_features(netdev);

	gmac_enable_tx_rx(netdev);

	return 0;
}

static netdev_features_t gmac_fix_features(struct net_device *netdev,
					   netdev_features_t features)
{
	if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
		features &= ~GMAC_OFFLOAD_FEATURES;

	return features;
}

static int gmac_set_features(struct net_device *netdev,
			     netdev_features_t features)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	int enable = features & NETIF_F_RXCSUM;
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&port->config_lock, flags);

	reg = readl(port->gmac_base + GMAC_CONFIG0);
	reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
	writel(reg, port->gmac_base + GMAC_CONFIG0);

	spin_unlock_irqrestore(&port->config_lock, flags);
	return 0;
}

static int gmac_get_sset_count(struct net_device *netdev, int sset)
{
	return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
}

static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
{
	if (stringset != ETH_SS_STATS)
		return;

	memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
}

static void gmac_get_ethtool_stats(struct net_device *netdev,
				   struct ethtool_stats *estats, u64 *values)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	unsigned int start;
	u64 *p;
	int i;

	gmac_update_hw_stats(netdev);

	/* Racing with MIB interrupt */
	do {
		p = values;
		start = u64_stats_fetch_begin(&port->ir_stats_syncp);

		for (i = 0; i < RX_STATS_NUM; i++)
			*p++ = port->hw_stats[i];

	} while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
	values = p;

	/* Racing with RX NAPI */
	do {
		p = values;
		start = u64_stats_fetch_begin(&port->rx_stats_syncp);

		for (i = 0; i < RX_STATUS_NUM; i++)
			*p++ = port->rx_stats[i];
		for (i = 0; i < RX_CHKSUM_NUM; i++)
			*p++ = port->rx_csum_stats[i];
		*p++ = port->rx_napi_exits;

	} while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
	values = p;

	/* Racing with TX start_xmit */
	do {
		p = values;
		start = u64_stats_fetch_begin(&port->tx_stats_syncp);

		for (i = 0; i < TX_MAX_FRAGS; i++) {
			*values++ = port->tx_frag_stats[i];
			port->tx_frag_stats[i] = 0;
		}
		*values++ = port->tx_frags_linearized;
		*values++ = port->tx_hw_csummed;

	} while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
}

static int gmac_get_ksettings(struct net_device *netdev,
			      struct ethtool_link_ksettings *cmd)
{
	if (!netdev->phydev)
		return -ENXIO;
	phy_ethtool_ksettings_get(netdev->phydev, cmd);

	return 0;
}

static int gmac_set_ksettings(struct net_device *netdev,
			      const struct ethtool_link_ksettings *cmd)
{
	if (!netdev->phydev)
		return -ENXIO;
	return phy_ethtool_ksettings_set(netdev->phydev, cmd);
}

static int gmac_nway_reset(struct net_device *netdev)
{
	if (!netdev->phydev)
		return -ENXIO;
	return phy_start_aneg(netdev->phydev);
}

static void gmac_get_pauseparam(struct net_device *netdev,
				struct ethtool_pauseparam *pparam)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	union gmac_config0 config0;

	config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);

	pparam->rx_pause = config0.bits.rx_fc_en;
	pparam->tx_pause = config0.bits.tx_fc_en;
	pparam->autoneg = true;
}

static void gmac_get_ringparam(struct net_device *netdev,
			       struct ethtool_ringparam *rp)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	union gmac_config0 config0;

	config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);

	rp->rx_max_pending = 1 << 15;
	rp->rx_mini_max_pending = 0;
	rp->rx_jumbo_max_pending = 0;
	rp->tx_max_pending = 1 << 15;

	rp->rx_pending = 1 << port->rxq_order;
	rp->rx_mini_pending = 0;
	rp->rx_jumbo_pending = 0;
	rp->tx_pending = 1 << port->txq_order;
}

static int gmac_set_ringparam(struct net_device *netdev,
			      struct ethtool_ringparam *rp)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);
	int err = 0;

	if (netif_running(netdev))
		return -EBUSY;

	if (rp->rx_pending) {
		port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
		err = geth_resize_freeq(port);
	}
	if (rp->tx_pending) {
		port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
		port->irq_every_tx_packets = 1 << (port->txq_order - 2);
	}

	return err;
}

static int gmac_get_coalesce(struct net_device *netdev,
			     struct ethtool_coalesce *ecmd)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);

	ecmd->rx_max_coalesced_frames = 1;
	ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
	ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;

	return 0;
}

static int gmac_set_coalesce(struct net_device *netdev,
			     struct ethtool_coalesce *ecmd)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);

	if (ecmd->tx_max_coalesced_frames < 1)
		return -EINVAL;
	if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
		return -EINVAL;

	port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
	port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;

	return 0;
}

static u32 gmac_get_msglevel(struct net_device *netdev)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);

	return port->msg_enable;
}

static void gmac_set_msglevel(struct net_device *netdev, u32 level)
{
	struct gemini_ethernet_port *port = netdev_priv(netdev);

	port->msg_enable = level;
}

static void gmac_get_drvinfo(struct net_device *netdev,
			     struct ethtool_drvinfo *info)
{
	strcpy(info->driver,  DRV_NAME);
	strcpy(info->version, DRV_VERSION);
	strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
}

static const struct net_device_ops gmac_351x_ops = {
	.ndo_init		= gmac_init,
	.ndo_uninit		= gmac_uninit,
	.ndo_open		= gmac_open,
	.ndo_stop		= gmac_stop,
	.ndo_start_xmit		= gmac_start_xmit,
	.ndo_tx_timeout		= gmac_tx_timeout,
	.ndo_set_rx_mode	= gmac_set_rx_mode,
	.ndo_set_mac_address	= gmac_set_mac_address,
	.ndo_get_stats64	= gmac_get_stats64,
	.ndo_change_mtu		= gmac_change_mtu,
	.ndo_fix_features	= gmac_fix_features,
	.ndo_set_features	= gmac_set_features,
};

static const struct ethtool_ops gmac_351x_ethtool_ops = {
	.get_sset_count	= gmac_get_sset_count,
	.get_strings	= gmac_get_strings,
	.get_ethtool_stats = gmac_get_ethtool_stats,
	.get_link	= ethtool_op_get_link,
	.get_link_ksettings = gmac_get_ksettings,
	.set_link_ksettings = gmac_set_ksettings,
	.nway_reset	= gmac_nway_reset,
	.get_pauseparam	= gmac_get_pauseparam,
	.get_ringparam	= gmac_get_ringparam,
	.set_ringparam	= gmac_set_ringparam,
	.get_coalesce	= gmac_get_coalesce,
	.set_coalesce	= gmac_set_coalesce,
	.get_msglevel	= gmac_get_msglevel,
	.set_msglevel	= gmac_set_msglevel,
	.get_drvinfo	= gmac_get_drvinfo,
};

static irqreturn_t gemini_port_irq_thread(int irq, void *data)
{
	unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
	struct gemini_ethernet_port *port = data;
	struct gemini_ethernet *geth;
	unsigned long flags;

	geth = port->geth;
	/* The queue is half empty so refill it */
	geth_fill_freeq(geth, true);

	spin_lock_irqsave(&geth->irq_lock, flags);
	/* ACK queue interrupt */
	writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
	/* Enable queue interrupt again */
	irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
	writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
	spin_unlock_irqrestore(&geth->irq_lock, flags);

	return IRQ_HANDLED;
}

static irqreturn_t gemini_port_irq(int irq, void *data)
{
	struct gemini_ethernet_port *port = data;
	struct gemini_ethernet *geth;
	irqreturn_t ret = IRQ_NONE;
	u32 val, en;

	geth = port->geth;
	spin_lock(&geth->irq_lock);

	val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
	en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);

	if (val & en & SWFQ_EMPTY_INT_BIT) {
		/* Disable the queue empty interrupt while we work on
		 * processing the queue. Also disable overrun interrupts
		 * as there is not much we can do about it here.
		 */
		en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
					   | GMAC1_RX_OVERRUN_INT_BIT);
		writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
		ret = IRQ_WAKE_THREAD;
	}

	spin_unlock(&geth->irq_lock);

	return ret;
}

static void gemini_port_remove(struct gemini_ethernet_port *port)
{
	if (port->netdev)
		unregister_netdev(port->netdev);
	clk_disable_unprepare(port->pclk);
	geth_cleanup_freeq(port->geth);
}

static void gemini_ethernet_init(struct gemini_ethernet *geth)
{
	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);

	/* Interrupt config:
	 *
	 *	GMAC0 intr bits ------> int0 ----> eth0
	 *	GMAC1 intr bits ------> int1 ----> eth1
	 *	TOE intr -------------> int1 ----> eth1
	 *	Classification Intr --> int0 ----> eth0
	 *	Default Q0 -----------> int0 ----> eth0
	 *	Default Q1 -----------> int1 ----> eth1
	 *	FreeQ intr -----------> int1 ----> eth1
	 */
	writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
	writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
	writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
	writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
	writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);

	/* edge-triggered interrupts packed to level-triggered one... */
	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);

	/* Set up queue */
	writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
	writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
	writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
	writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);

	geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
	/* This makes the queue resize on probe() so that we
	 * set up and enable the queue IRQ. FIXME: fragile.
	 */
	geth->freeq_order = 1;
}

static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
{
	port->mac_addr[0] =
		cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
	port->mac_addr[1] =
		cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
	port->mac_addr[2] =
		cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
}

static int gemini_ethernet_port_probe(struct platform_device *pdev)
{
	char *port_names[2] = { "ethernet0", "ethernet1" };
	struct gemini_ethernet_port *port;
	struct device *dev = &pdev->dev;
	struct gemini_ethernet *geth;
	struct net_device *netdev;
	struct resource *gmacres;
	struct resource *dmares;
	struct device *parent;
	unsigned int id;
	int irq;
	int ret;

	parent = dev->parent;
	geth = dev_get_drvdata(parent);

	if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
		id = 0;
	else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
		id = 1;
	else
		return -ENODEV;

	dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);

	netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM);
	if (!netdev) {
		dev_err(dev, "Can't allocate ethernet device #%d\n", id);
		return -ENOMEM;
	}

	port = netdev_priv(netdev);
	SET_NETDEV_DEV(netdev, dev);
	port->netdev = netdev;
	port->id = id;
	port->geth = geth;
	port->dev = dev;

	/* DMA memory */
	dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!dmares) {
		dev_err(dev, "no DMA resource\n");
		return -ENODEV;
	}
	port->dma_base = devm_ioremap_resource(dev, dmares);
	if (IS_ERR(port->dma_base))
		return PTR_ERR(port->dma_base);

	/* GMAC config memory */
	gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!gmacres) {
		dev_err(dev, "no GMAC resource\n");
		return -ENODEV;
	}
	port->gmac_base = devm_ioremap_resource(dev, gmacres);
	if (IS_ERR(port->gmac_base))
		return PTR_ERR(port->gmac_base);

	/* Interrupt */
	irq = platform_get_irq(pdev, 0);
	if (irq <= 0) {
		dev_err(dev, "no IRQ\n");
		return irq ? irq : -ENODEV;
	}
	port->irq = irq;

	/* Clock the port */
	port->pclk = devm_clk_get(dev, "PCLK");
	if (IS_ERR(port->pclk)) {
		dev_err(dev, "no PCLK\n");
		return PTR_ERR(port->pclk);
	}
	ret = clk_prepare_enable(port->pclk);
	if (ret)
		return ret;

	/* Maybe there is a nice ethernet address we should use */
	gemini_port_save_mac_addr(port);

	/* Reset the port */
	port->reset = devm_reset_control_get_exclusive(dev, NULL);
	if (IS_ERR(port->reset)) {
		dev_err(dev, "no reset\n");
		return PTR_ERR(port->reset);
	}
	reset_control_reset(port->reset);
	usleep_range(100, 500);

	/* Assign pointer in the main state container */
	if (!id)
		geth->port0 = port;
	else
		geth->port1 = port;
	platform_set_drvdata(pdev, port);

	/* Set up and register the netdev */
	netdev->dev_id = port->id;
	netdev->irq = irq;
	netdev->netdev_ops = &gmac_351x_ops;
	netdev->ethtool_ops = &gmac_351x_ethtool_ops;

	spin_lock_init(&port->config_lock);
	gmac_clear_hw_stats(netdev);

	netdev->hw_features = GMAC_OFFLOAD_FEATURES;
	netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;

	port->freeq_refill = 0;
	netif_napi_add(netdev, &port->napi, gmac_napi_poll,
		       DEFAULT_NAPI_WEIGHT);

	if (is_valid_ether_addr((void *)port->mac_addr)) {
		memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
	} else {
		dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
			port->mac_addr[0], port->mac_addr[1],
			port->mac_addr[2]);
		dev_info(dev, "using a random ethernet address\n");
		random_ether_addr(netdev->dev_addr);
	}
	gmac_write_mac_address(netdev);

	ret = devm_request_threaded_irq(port->dev,
					port->irq,
					gemini_port_irq,
					gemini_port_irq_thread,
					IRQF_SHARED,
					port_names[port->id],
					port);
	if (ret)
		return ret;

	ret = register_netdev(netdev);
	if (!ret) {
		netdev_info(netdev,
			    "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
			    port->irq, &dmares->start,
			    &gmacres->start);
		ret = gmac_setup_phy(netdev);
		if (ret)
			netdev_info(netdev,
				    "PHY init failed, deferring to ifup time\n");
		return 0;
	}

	port->netdev = NULL;
	free_netdev(netdev);
	return ret;
}

static int gemini_ethernet_port_remove(struct platform_device *pdev)
{
	struct gemini_ethernet_port *port = platform_get_drvdata(pdev);

	gemini_port_remove(port);
	return 0;
}

static const struct of_device_id gemini_ethernet_port_of_match[] = {
	{
		.compatible = "cortina,gemini-ethernet-port",
	},
	{},
};
MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);

static struct platform_driver gemini_ethernet_port_driver = {
	.driver = {
		.name = "gemini-ethernet-port",
		.of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
	},
	.probe = gemini_ethernet_port_probe,
	.remove = gemini_ethernet_port_remove,
};

static int gemini_ethernet_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct gemini_ethernet *geth;
	unsigned int retry = 5;
	struct resource *res;
	u32 val;

	/* Global registers */
	geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
	if (!geth)
		return -ENOMEM;
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;
	geth->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(geth->base))
		return PTR_ERR(geth->base);
	geth->dev = dev;

	/* Wait for ports to stabilize */
	do {
		udelay(2);
		val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
		barrier();
	} while (!val && --retry);
	if (!retry) {
		dev_err(dev, "failed to reset ethernet\n");
		return -EIO;
	}
	dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
		 (val >> 4) & 0xFFFU, val & 0xFU);

	spin_lock_init(&geth->irq_lock);
	spin_lock_init(&geth->freeq_lock);
	gemini_ethernet_init(geth);

	/* The children will use this */
	platform_set_drvdata(pdev, geth);

	/* Spawn child devices for the two ports */
	return devm_of_platform_populate(dev);
}

static int gemini_ethernet_remove(struct platform_device *pdev)
{
	struct gemini_ethernet *geth = platform_get_drvdata(pdev);

	gemini_ethernet_init(geth);
	geth_cleanup_freeq(geth);

	return 0;
}

static const struct of_device_id gemini_ethernet_of_match[] = {
	{
		.compatible = "cortina,gemini-ethernet",
	},
	{},
};
MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);

static struct platform_driver gemini_ethernet_driver = {
	.driver = {
		.name = DRV_NAME,
		.of_match_table = of_match_ptr(gemini_ethernet_of_match),
	},
	.probe = gemini_ethernet_probe,
	.remove = gemini_ethernet_remove,
};

static int __init gemini_ethernet_module_init(void)
{
	int ret;

	ret = platform_driver_register(&gemini_ethernet_port_driver);
	if (ret)
		return ret;

	ret = platform_driver_register(&gemini_ethernet_driver);
	if (ret) {
		platform_driver_unregister(&gemini_ethernet_port_driver);
		return ret;
	}

	return 0;
}
module_init(gemini_ethernet_module_init);

static void __exit gemini_ethernet_module_exit(void)
{
	platform_driver_unregister(&gemini_ethernet_driver);
	platform_driver_unregister(&gemini_ethernet_port_driver);
}
module_exit(gemini_ethernet_module_exit);

MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);