idle_book3s.S 15.3 KB
Newer Older
1
/*
2 3
 *  This file contains idle entry/exit functions for POWER7,
 *  POWER8 and POWER9 CPUs.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ppc-opcode.h>
19
#include <asm/hw_irq.h>
20
#include <asm/kvm_book3s_asm.h>
21
#include <asm/opal.h>
22
#include <asm/cpuidle.h>
23
#include <asm/book3s/64/mmu-hash.h>
24
#include <asm/mmu.h>
25 26 27

#undef DEBUG

28 29 30 31 32 33 34 35 36 37 38 39 40
/*
 * Use unused space in the interrupt stack to save and restore
 * registers for winkle support.
 */
#define _SDR1	GPR3
#define _RPR	GPR4
#define _SPURR	GPR5
#define _PURR	GPR6
#define _TSCR	GPR7
#define _DSCR	GPR8
#define _AMOR	GPR9
#define _WORT	GPR10
#define _WORC	GPR11
41 42 43 44 45
#define _PTCR	GPR12

#define PSSCR_HV_TEMPLATE	PSSCR_ESL | PSSCR_EC | \
				PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
				PSSCR_MTL_MASK
46

47 48
	.text

49 50 51 52 53 54 55 56 57
/*
 * Used by threads before entering deep idle states. Saves SPRs
 * in interrupt stack frame
 */
save_sprs_to_stack:
	/*
	 * Note all register i.e per-core, per-subcore or per-thread is saved
	 * here since any thread in the core might wake up first
	 */
58 59 60 61 62 63 64 65
BEGIN_FTR_SECTION
	mfspr	r3,SPRN_PTCR
	std	r3,_PTCR(r1)
	/*
	 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
	 * SDR1 here
	 */
FTR_SECTION_ELSE
66 67
	mfspr	r3,SPRN_SDR1
	std	r3,_SDR1(r1)
68
ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
	mfspr	r3,SPRN_RPR
	std	r3,_RPR(r1)
	mfspr	r3,SPRN_SPURR
	std	r3,_SPURR(r1)
	mfspr	r3,SPRN_PURR
	std	r3,_PURR(r1)
	mfspr	r3,SPRN_TSCR
	std	r3,_TSCR(r1)
	mfspr	r3,SPRN_DSCR
	std	r3,_DSCR(r1)
	mfspr	r3,SPRN_AMOR
	std	r3,_AMOR(r1)
	mfspr	r3,SPRN_WORT
	std	r3,_WORT(r1)
	mfspr	r3,SPRN_WORC
	std	r3,_WORC(r1)

	blr

88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
/*
 * Used by threads when the lock bit of core_idle_state is set.
 * Threads will spin in HMT_LOW until the lock bit is cleared.
 * r14 - pointer to core_idle_state
 * r15 - used to load contents of core_idle_state
 */

core_idle_lock_held:
	HMT_LOW
3:	lwz	r15,0(r14)
	andi.   r15,r15,PNV_CORE_IDLE_LOCK_BIT
	bne	3b
	HMT_MEDIUM
	lwarx	r15,0,r14
	blr

104 105
/*
 * Pass requested state in r3:
106 107
 *	r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
 *	   - Requested STOP state in POWER9
108 109 110 111
 *
 * To check IRQ_HAPPENED in r4
 * 	0 - don't check
 * 	1 - check
112 113
 *
 * Address to 'rfid' to in r5
114
 */
115
_GLOBAL(pnv_powersave_common)
116
	/* Use r3 to pass state nap/sleep/winkle */
117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133
	/* NAP is a state loss, we create a regs frame on the
	 * stack, fill it up with the state we care about and
	 * stick a pointer to it in PACAR1. We really only
	 * need to save PC, some CR bits and the NV GPRs,
	 * but for now an interrupt frame will do.
	 */
	mflr	r0
	std	r0,16(r1)
	stdu	r1,-INT_FRAME_SIZE(r1)
	std	r0,_LINK(r1)
	std	r0,_NIP(r1)

	/* Hard disable interrupts */
	mfmsr	r9
	rldicl	r9,r9,48,1
	rotldi	r9,r9,16
	mtmsrd	r9,1			/* hard-disable interrupts */
134 135 136

	/* Check if something happened while soft-disabled */
	lbz	r0,PACAIRQHAPPENED(r13)
137
	andi.	r0,r0,~PACA_IRQ_HARD_DIS@l
138
	beq	1f
139 140
	cmpwi	cr0,r4,0
	beq	1f
141 142
	addi	r1,r1,INT_FRAME_SIZE
	ld	r0,16(r1)
143
	li	r3,0			/* Return 0 (no nap) */
144 145 146 147 148 149 150 151 152 153 154
	mtlr	r0
	blr

1:	/* We mark irqs hard disabled as this is the state we'll
	 * be in when returning and we need to tell arch_local_irq_restore()
	 * about it
	 */
	li	r0,PACA_IRQ_HARD_DIS
	stb	r0,PACAIRQHAPPENED(r13)

	/* We haven't lost state ... yet */
155
	li	r0,0
156
	stb	r0,PACA_NAPSTATELOST(r13)
157 158 159 160

	/* Continue saving state */
	SAVE_GPR(2, r1)
	SAVE_NVGPRS(r1)
161 162
	mfcr	r4
	std	r4,_CCR(r1)
163 164 165
	std	r9,_MSR(r1)
	std	r1,PACAR1(r13)

166 167
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	/* Tell KVM we're entering idle */
168
	li	r4,KVM_HWTHREAD_IN_IDLE
169 170 171
	stb	r4,HSTATE_HWTHREAD_STATE(r13)
#endif

172 173 174 175 176 177
	/*
	 * Go to real mode to do the nap, as required by the architecture.
	 * Also, we need to be in real mode before setting hwthread_state,
	 * because as soon as we do that, another thread can switch
	 * the MMU context to the guest.
	 */
178
	LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
179 180 181
	li	r6, MSR_RI
	andc	r6, r9, r6
	mtmsrd	r6, 1		/* clear RI before setting SRR0/1 */
182 183
	mtspr	SPRN_SRR0, r5
	mtspr	SPRN_SRR1, r7
184 185
	rfid

186 187
	.globl pnv_enter_arch207_idle_mode
pnv_enter_arch207_idle_mode:
188
	stb	r3,PACA_THREAD_IDLE_STATE(r13)
189 190
	cmpwi	cr3,r3,PNV_THREAD_SLEEP
	bge	cr3,2f
191 192
	IDLE_STATE_ENTER_SEQ(PPC_NAP)
	/* No return */
193 194 195 196 197 198
2:
	/* Sleep or winkle */
	lbz	r7,PACA_THREAD_MASK(r13)
	ld	r14,PACA_CORE_IDLE_STATE_PTR(r13)
lwarx_loop1:
	lwarx	r15,0,r14
199 200 201 202

	andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
	bnel	core_idle_lock_held

203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222
	andc	r15,r15,r7			/* Clear thread bit */

	andi.	r15,r15,PNV_CORE_IDLE_THREAD_BITS

/*
 * If cr0 = 0, then current thread is the last thread of the core entering
 * sleep. Last thread needs to execute the hardware bug workaround code if
 * required by the platform.
 * Make the workaround call unconditionally here. The below branch call is
 * patched out when the idle states are discovered if the platform does not
 * require it.
 */
.global pnv_fastsleep_workaround_at_entry
pnv_fastsleep_workaround_at_entry:
	beq	fastsleep_workaround_at_entry

	stwcx.	r15,0,r14
	bne-	lwarx_loop1
	isync

223 224
common_enter: /* common code for all the threads entering sleep or winkle */
	bgt	cr3,enter_winkle
225 226 227 228 229 230 231 232 233 234 235
	IDLE_STATE_ENTER_SEQ(PPC_SLEEP)

fastsleep_workaround_at_entry:
	ori	r15,r15,PNV_CORE_IDLE_LOCK_BIT
	stwcx.	r15,0,r14
	bne-	lwarx_loop1
	isync

	/* Fast sleep workaround */
	li	r3,1
	li	r4,1
236
	bl	opal_rm_config_cpu_idle_state
237 238 239 240 241 242 243

	/* Clear Lock bit */
	li	r0,0
	lwsync
	stw	r0,0(r14)
	b	common_enter

244
enter_winkle:
245 246
	bl	save_sprs_to_stack

247
	IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
248

249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283
/*
 * r3 - requested stop state
 */
power_enter_stop:
/*
 * Check if the requested state is a deep idle state.
 */
	LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
	ld	r4,ADDROFF(pnv_first_deep_stop_state)(r5)
	cmpd	r3,r4
	bge	2f
	IDLE_STATE_ENTER_SEQ(PPC_STOP)
2:
/*
 * Entering deep idle state.
 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
 * stack and enter stop
 */
	lbz     r7,PACA_THREAD_MASK(r13)
	ld      r14,PACA_CORE_IDLE_STATE_PTR(r13)

lwarx_loop_stop:
	lwarx   r15,0,r14
	andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
	bnel    core_idle_lock_held
	andc    r15,r15,r7                      /* Clear thread bit */

	stwcx.  r15,0,r14
	bne-    lwarx_loop_stop
	isync

	bl	save_sprs_to_stack

	IDLE_STATE_ENTER_SEQ(PPC_STOP)

284 285 286 287 288 289
_GLOBAL(power7_idle)
	/* Now check if user or arch enabled NAP mode */
	LOAD_REG_ADDRBASE(r3,powersave_nap)
	lwz	r4,ADDROFF(powersave_nap)(r3)
	cmpwi	0,r4,0
	beqlr
290
	li	r3, 1
291 292 293
	/* fall through */

_GLOBAL(power7_nap)
294
	mr	r4,r3
295
	li	r3,PNV_THREAD_NAP
296
	LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
297
	b	pnv_powersave_common
298 299 300
	/* No return */

_GLOBAL(power7_sleep)
301
	li	r3,PNV_THREAD_SLEEP
302
	li	r4,1
303
	LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
304
	b	pnv_powersave_common
305
	/* No return */
306

307
_GLOBAL(power7_winkle)
308
	li	r3,PNV_THREAD_WINKLE
309
	li	r4,1
310
	LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
311
	b	pnv_powersave_common
312 313
	/* No return */

314 315 316 317 318 319 320 321 322 323 324 325 326
#define CHECK_HMI_INTERRUPT						\
	mfspr	r0,SPRN_SRR1;						\
BEGIN_FTR_SECTION_NESTED(66);						\
	rlwinm	r0,r0,45-31,0xf;  /* extract wake reason field (P8) */	\
FTR_SECTION_ELSE_NESTED(66);						\
	rlwinm	r0,r0,45-31,0xe;  /* P7 wake reason field is 3 bits */	\
ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66);		\
	cmpwi	r0,0xa;			/* Hypervisor maintenance ? */	\
	bne	20f;							\
	/* Invoke opal call to handle hmi */				\
	ld	r2,PACATOC(r13);					\
	ld	r1,PACAR1(r13);						\
	std	r3,ORIG_GPR3(r1);	/* Save original r3 */		\
327 328 329
	li	r3,0;			/* NULL argument */		\
	bl	hmi_exception_realmode;					\
	nop;								\
330 331 332 333
	ld	r3,ORIG_GPR3(r1);	/* Restore original r3 */	\
20:	nop;


334 335 336 337 338 339 340 341 342 343 344
/*
 * r3 - requested stop state
 */
_GLOBAL(power9_idle_stop)
	LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
	or	r4,r4,r3
	mtspr	SPRN_PSSCR, r4
	li	r4, 1
	LOAD_REG_ADDR(r5,power_enter_stop)
	b	pnv_powersave_common
	/* No return */
345 346 347 348 349 350 351 352
/*
 * Called from reset vector. Check whether we have woken up with
 * hypervisor state loss. If yes, restore hypervisor state and return
 * back to reset vector.
 *
 * r13 - Contents of HSPRG0
 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
 */
353
_GLOBAL(pnv_restore_hyp_resource)
354
BEGIN_FTR_SECTION
355
	ld	r2,PACATOC(r13);
356 357 358 359 360 361 362 363
	/*
	 * POWER ISA 3. Use PSSCR to determine if we
	 * are waking up from deep idle state
	 */
	LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
	ld	r4,ADDROFF(pnv_first_deep_stop_state)(r5)

	mfspr	r5,SPRN_PSSCR
364
	/*
365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380
	 * 0-3 bits correspond to Power-Saving Level Status
	 * which indicates the idle state we are waking up from
	 */
	rldicl  r5,r5,4,60
	cmpd	cr4,r5,r4
	bge	cr4,pnv_wakeup_tb_loss
	/*
	 * Waking up without hypervisor state loss. Return to
	 * reset vector
	 */
	blr

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)

	/*
	 * POWER ISA 2.07 or less.
381 382 383 384 385
	 * Check if last bit of HSPGR0 is set. This indicates whether we are
	 * waking up from winkle.
	 */
	clrldi	r5,r13,63
	clrrdi	r13,r13,1
386 387 388

	/* Now that we are sure r13 is corrected, load TOC */
	ld	r2,PACATOC(r13);
389 390 391 392 393
	cmpwi	cr4,r5,1
	mtspr	SPRN_HSPRG0,r13

	lbz	r0,PACA_THREAD_IDLE_STATE(r13)
	cmpwi   cr2,r0,PNV_THREAD_NAP
394
	bgt     cr2,pnv_wakeup_tb_loss	/* Either sleep or Winkle */
395 396 397 398 399 400 401 402 403

	/*
	 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
	 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
	 * indicates we are waking with hypervisor state loss from nap.
	 */
	bgt	cr3,.

	blr	/* Return back to System Reset vector from where
404
		   pnv_restore_hyp_resource was invoked */
405

406 407 408 409 410 411 412 413 414 415
/*
 * Called if waking up from idle state which can cause either partial or
 * complete hyp state loss.
 * In POWER8, called if waking up from fastsleep or winkle
 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
 *
 * r13 - PACA
 * cr3 - gt if waking up with partial/complete hypervisor state loss
 * cr4 - eq if waking up from complete hypervisor state loss.
 */
416
_GLOBAL(pnv_wakeup_tb_loss)
417
	ld	r1,PACAR1(r13)
418 419 420 421 422
	/*
	 * Before entering any idle state, the NVGPRs are saved in the stack
	 * and they are restored before switching to the process context. Hence
	 * until they are restored, they are free to be used.
	 *
423
	 * Save SRR1 and LR in NVGPRs as they might be clobbered in
424
	 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
425 426 427
	 * to determine the wakeup reason if we branch to kvm_start_guest. LR
	 * is required to return back to reset vector after hypervisor state
	 * restore is complete.
428
	 */
429
	mflr	r17
430
	mfspr	r16,SPRN_SRR1
431 432 433
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
434 435 436 437 438 439 440 441 442 443 444 445 446 447

	lbz	r7,PACA_THREAD_MASK(r13)
	ld	r14,PACA_CORE_IDLE_STATE_PTR(r13)
lwarx_loop2:
	lwarx	r15,0,r14
	andi.	r9,r15,PNV_CORE_IDLE_LOCK_BIT
	/*
	 * Lock bit is set in one of the 2 cases-
	 * a. In the sleep/winkle enter path, the last thread is executing
	 * fastsleep workaround code.
	 * b. In the wake up path, another thread is executing fastsleep
	 * workaround undo code or resyncing timebase or restoring context
	 * In either case loop until the lock bit is cleared.
	 */
448
	bnel	core_idle_lock_held
449 450

	cmpwi	cr2,r15,0
451 452 453

	/*
	 * At this stage
454 455 456
	 * cr2 - eq if first thread to wakeup in core
	 * cr3-  gt if waking up with partial/complete hypervisor state loss
	 * cr4 - eq if waking up from complete hypervisor state loss.
457 458
	 */

459 460 461 462 463
	ori	r15,r15,PNV_CORE_IDLE_LOCK_BIT
	stwcx.	r15,0,r14
	bne-	lwarx_loop2
	isync

464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479
BEGIN_FTR_SECTION
	lbz	r4,PACA_SUBCORE_SIBLING_MASK(r13)
	and	r4,r4,r15
	cmpwi	r4,0	/* Check if first in subcore */

	or	r15,r15,r7		/* Set thread bit */
	beq	first_thread_in_subcore
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)

	or	r15,r15,r7		/* Set thread bit */
	beq	cr2,first_thread_in_core

	/* Not first thread in core or subcore to wake up */
	b	clear_lock

first_thread_in_subcore:
480 481 482 483 484 485 486 487 488
	/*
	 * If waking up from sleep, subcore state is not lost. Hence
	 * skip subcore state restore
	 */
	bne	cr4,subcore_state_restored

	/* Restore per-subcore state */
	ld      r4,_SDR1(r1)
	mtspr   SPRN_SDR1,r4
489

490 491 492 493 494 495 496 497 498 499 500 501 502 503
	ld      r4,_RPR(r1)
	mtspr   SPRN_RPR,r4
	ld	r4,_AMOR(r1)
	mtspr	SPRN_AMOR,r4

subcore_state_restored:
	/*
	 * Check if the thread is also the first thread in the core. If not,
	 * skip to clear_lock.
	 */
	bne	cr2,clear_lock

first_thread_in_core:

504
	/*
505 506
	 * First thread in the core waking up from any state which can cause
	 * partial or complete hypervisor state loss. It needs to
507 508
	 * call the fastsleep workaround code if the platform requires it.
	 * Call it unconditionally here. The below branch instruction will
509 510 511
	 * be patched out if the platform does not have fastsleep or does not
	 * require the workaround. Patching will be performed during the
	 * discovery of idle-states.
512 513 514 515 516 517
	 */
.global pnv_fastsleep_workaround_at_exit
pnv_fastsleep_workaround_at_exit:
	b	fastsleep_workaround_at_exit

timebase_resync:
518 519 520 521
	/*
	 * Use cr3 which indicates that we are waking up with atleast partial
	 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
	 */
522
	ble	cr3,clear_lock
523
	/* Time base re-sync */
524
	bl	opal_rm_resync_timebase;
525 526 527 528 529 530
	/*
	 * If waking up from sleep, per core state is not lost, skip to
	 * clear_lock.
	 */
	bne	cr4,clear_lock

531 532 533 534 535 536 537 538 539 540 541 542
	/*
	 * First thread in the core to wake up and its waking up with
	 * complete hypervisor state loss. Restore per core hypervisor
	 * state.
	 */
BEGIN_FTR_SECTION
	ld	r4,_PTCR(r1)
	mtspr	SPRN_PTCR,r4
	ld	r4,_RPR(r1)
	mtspr	SPRN_RPR,r4
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)

543 544 545 546 547
	ld	r4,_TSCR(r1)
	mtspr	SPRN_TSCR,r4
	ld	r4,_WORC(r1)
	mtspr	SPRN_WORC,r4

548 549 550 551 552 553
clear_lock:
	andi.	r15,r15,PNV_CORE_IDLE_THREAD_BITS
	lwsync
	stw	r15,0(r14)

common_exit:
554 555 556 557 558 559 560 561 562 563
	/*
	 * Common to all threads.
	 *
	 * If waking up from sleep, hypervisor state is not lost. Hence
	 * skip hypervisor state restore.
	 */
	bne	cr4,hypervisor_state_restored

	/* Waking up from winkle */

564 565
BEGIN_MMU_FTR_SECTION
	b	no_segments
566
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
567 568 569 570 571 572 573 574 575 576 577 578 579
	/* Restore SLB  from PACA */
	ld	r8,PACA_SLBSHADOWPTR(r13)

	.rept	SLB_NUM_BOLTED
	li	r3, SLBSHADOW_SAVEAREA
	LDX_BE	r5, r8, r3
	addi	r3, r3, 8
	LDX_BE	r6, r8, r3
	andis.	r7,r5,SLB_ESID_V@h
	beq	1f
	slbmte	r6,r5
1:	addi	r8,r8,16
	.endr
580 581 582
no_segments:

	/* Restore per thread state */
583 584 585 586 587 588 589 590 591 592

	ld	r4,_SPURR(r1)
	mtspr	SPRN_SPURR,r4
	ld	r4,_PURR(r1)
	mtspr	SPRN_PURR,r4
	ld	r4,_DSCR(r1)
	mtspr	SPRN_DSCR,r4
	ld	r4,_WORT(r1)
	mtspr	SPRN_WORT,r4

593 594 595 596 597 598 599 600 601 602
	/* Call cur_cpu_spec->cpu_restore() */
	LOAD_REG_ADDR(r4, cur_cpu_spec)
	ld	r4,0(r4)
	ld	r12,CPU_SPEC_RESTORE(r4)
#ifdef PPC64_ELF_ABI_v1
	ld	r12,0(r12)
#endif
	mtctr	r12
	bctrl

603 604
hypervisor_state_restored:

605
	mtspr	SPRN_SRR1,r16
606 607
	mtlr	r17
	blr	/* Return back to System Reset vector from where
608
		   pnv_restore_hyp_resource was invoked */
609

610 611 612
fastsleep_workaround_at_exit:
	li	r3,1
	li	r4,0
613
	bl	opal_rm_config_cpu_idle_state
614 615
	b	timebase_resync

616 617 618 619
/*
 * R3 here contains the value that will be returned to the caller
 * of power7_nap.
 */
620
_GLOBAL(pnv_wakeup_loss)
621
	ld	r1,PACAR1(r13)
622 623 624
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
625 626
	REST_NVGPRS(r1)
	REST_GPR(2, r1)
627
	ld	r6,_CCR(r1)
628 629 630
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
631
	mtcr	r6
632 633 634 635
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid

636 637 638 639
/*
 * R3 here contains the value that will be returned to the caller
 * of power7_nap.
 */
640
_GLOBAL(pnv_wakeup_noloss)
641 642
	lbz	r0,PACA_NAPSTATELOST(r13)
	cmpwi	r0,0
643
	bne	pnv_wakeup_loss
644 645 646
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
647
	ld	r1,PACAR1(r13)
648
	ld	r6,_CCR(r1)
649 650 651
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
652
	mtcr	r6
653 654 655
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid