omap5.dtsi 14.9 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

/*
 * Carveout for multimedia usecases
 * It should be the last 48MB of the first 512MB memory part
 * In theory, it should not even exist. That zone should be reserved
 * dynamically during the .reserve callback.
 */
/memreserve/ 0x9d000000 0x03000000;

/include/ "skeleton.dtsi"

/ {
21 22 23
	#address-cells = <1>;
	#size-cells = <1>;

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
		};
	};

45 46
	timer {
		compatible = "arm,armv7-timer";
47 48
		/* PPI secure/nonsecure IRQ, active low level-sensitive */
		interrupts = <1 13 0x308>,
49 50 51
			     <1 14 0x308>,
			     <1 11 0x308>,
			     <1 10 0x308>;
52 53 54
		clock-frequency = <6144000>;
	};

55 56 57 58 59
	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48211000 0x1000>,
60 61 62
		      <0x48212000 0x1000>,
		      <0x48214000 0x2000>,
		      <0x48216000 0x2000>;
63 64
	};

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";

J
Jon Hunter 已提交
91 92 93 94 95 96
		counter32k: counter@4ae04000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4ae04000 0x40>;
			ti,hwmods = "counter_32k";
		};

97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
		omap5_pmx_core: pinmux@4a002840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a002840 0x01b6>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap5_pmx_wkup: pinmux@4ae0c840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4ae0c840 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

114 115 116 117 118 119 120 121 122 123 124 125
		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0 12 0x4>,
				     <0 13 0x4>,
				     <0 14 0x4>,
				     <0 15 0x4>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <127>;
		};

126 127
		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
128 129
			reg = <0x4ae10000 0x200>;
			interrupts = <0 29 0x4>;
130 131 132 133
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
134
			#interrupt-cells = <2>;
135 136 137 138
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
139 140
			reg = <0x48055000 0x200>;
			interrupts = <0 30 0x4>;
141 142 143 144
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
145
			#interrupt-cells = <2>;
146 147 148 149
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
150 151
			reg = <0x48057000 0x200>;
			interrupts = <0 31 0x4>;
152 153 154 155
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
156
			#interrupt-cells = <2>;
157 158 159 160
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
161 162
			reg = <0x48059000 0x200>;
			interrupts = <0 32 0x4>;
163 164 165 166
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
167
			#interrupt-cells = <2>;
168 169 170 171
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
172 173
			reg = <0x4805b000 0x200>;
			interrupts = <0 33 0x4>;
174 175 176 177
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
178
			#interrupt-cells = <2>;
179 180 181 182
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
183 184
			reg = <0x4805d000 0x200>;
			interrupts = <0 34 0x4>;
185 186 187 188
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
189
			#interrupt-cells = <2>;
190 191 192 193
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
194 195
			reg = <0x48051000 0x200>;
			interrupts = <0 35 0x4>;
196 197 198 199
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
200
			#interrupt-cells = <2>;
201 202 203 204
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
205 206
			reg = <0x48053000 0x200>;
			interrupts = <0 121 0x4>;
207 208 209 210
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
211
			#interrupt-cells = <2>;
212 213
		};

214 215 216 217 218 219 220 221 222 223 224
		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <0 20 0x4>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
		};

225 226
		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
227 228
			reg = <0x48070000 0x100>;
			interrupts = <0 56 0x4>;
229 230 231 232 233 234 235
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
236 237
			reg = <0x48072000 0x100>;
			interrupts = <0 57 0x4>;
238 239 240 241 242 243 244
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
245 246
			reg = <0x48060000 0x100>;
			interrupts = <0 61 0x4>;
247 248 249 250 251
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

252
		i2c4: i2c@4807a000 {
253
			compatible = "ti,omap4-i2c";
254 255
			reg = <0x4807a000 0x100>;
			interrupts = <0 62 0x4>;
256 257 258 259 260
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

261
		i2c5: i2c@4807c000 {
262
			compatible = "ti,omap4-i2c";
263 264
			reg = <0x4807c000 0x100>;
			interrupts = <0 60 0x4>;
265 266 267 268 269
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

F
Felipe Balbi 已提交
270 271 272 273 274 275 276 277
		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0 65 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
278 279 280 281 282 283 284 285 286 287
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
F
Felipe Balbi 已提交
288 289 290 291 292 293 294 295 296 297
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0 66 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
298 299 300 301 302
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
F
Felipe Balbi 已提交
303 304 305 306 307 308 309 310 311 312
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0 91 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
313 314
			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
F
Felipe Balbi 已提交
315 316 317 318 319 320 321 322 323 324
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0 48 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
325 326
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
F
Felipe Balbi 已提交
327 328
		};

329 330
		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
331 332
			reg = <0x4806a000 0x100>;
			interrupts = <0 72 0x4>;
333 334 335 336 337 338
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
339 340
			reg = <0x4806c000 0x100>;
			interrupts = <0 73 0x4>;
341 342 343 344 345 346
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
347 348
			reg = <0x48020000 0x100>;
			interrupts = <0 74 0x4>;
349 350 351 352 353 354
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
355 356
			reg = <0x4806e000 0x100>;
			interrupts = <0 70 0x4>;
357 358 359 360 361
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
362 363 364
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0 105 0x4>;
365 366 367 368 369
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
370 371 372
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0 106 0x4>;
373 374 375
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};
376 377 378

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
379 380
			reg = <0x4809c000 0x400>;
			interrupts = <0 83 0x4>;
381 382 383
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
384 385
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
386 387 388 389
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
390 391
			reg = <0x480b4000 0x400>;
			interrupts = <0 86 0x4>;
392 393
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
394 395
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
396 397 398 399
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
400 401
			reg = <0x480ad000 0x400>;
			interrupts = <0 94 0x4>;
402 403
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
404 405
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
406 407 408 409
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
410 411
			reg = <0x480d1000 0x400>;
			interrupts = <0 96 0x4>;
412 413
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
414 415
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
416 417 418 419
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
420 421
			reg = <0x480d5000 0x400>;
			interrupts = <0 59 0x4>;
422 423
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
424 425
			dmas = <&sdma 59>, <&sdma 60>;
			dma-names = "tx", "rx";
426
		};
427 428 429

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
430
			reg = <0x4ae1c000 0x400>;
431 432
			ti,hwmods = "kbd";
		};
433

434 435 436 437 438 439 440
		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			ti,hwmods = "mcpdm";
441 442 443
			dmas = <&sdma 65>,
			       <&sdma 66>;
			dma-names = "up_link", "dn_link";
444 445 446 447 448 449 450 451 452
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			ti,hwmods = "dmic";
453 454
			dmas = <&sdma 67>;
			dma-names = "up_link";
455 456
		};

457 458 459 460 461 462 463 464 465
		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
466 467 468
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
469 470 471 472 473 474 475 476 477 478 479
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
480 481 482
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
483 484 485 486 487 488 489 490 491 492 493
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
494 495 496
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
497
		};
J
Jon Hunter 已提交
498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586

		timer1: timer@4ae18000 {
			compatible = "ti,omap2-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0 37 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap2-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0 38 0x4>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap2-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0 39 0x4>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap2-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0 40 0x4>;
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
			compatible = "ti,omap2-timer";
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
			interrupts = <0 41 0x4>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@4013a000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
			interrupts = <0 42 0x4>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@4013c000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
			interrupts = <0 43 0x4>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
			interrupts = <0 44 0x4>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap2-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0 45 0x4>;
			ti,hwmods = "timer9";
		};

		timer10: timer@48086000 {
			compatible = "ti,omap2-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0 46 0x4>;
			ti,hwmods = "timer10";
		};

		timer11: timer@48088000 {
			compatible = "ti,omap2-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0 47 0x4>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};
587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608

		emif1: emif@0x4c000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
			interrupts = <0 110 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@0x4d000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
			interrupts = <0 111 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};
609 610 611 612 613 614 615 616

		omap_control_usb: omap-control-usb@4a002300 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002300 0x4>,
			      <0x4a002370 0x4>;
			reg-names = "control_dev_conf", "phy_power_usb";
			ti,type = <2>;
		};
617

618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635
		omap_dwc3@4a020000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss";
			reg = <0x4a020000 0x1000>;
			interrupts = <0 93 4>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
			dwc3@4a030000 {
				compatible = "synopsys,dwc3";
				reg = <0x4a030000 0x1000>;
				interrupts = <0 92 4>;
				usb-phy = <&usb2_phy>, <&usb3_phy>;
				tx-fifo-resize;
			};
		};

636 637 638 639 640 641
		ocp2scp {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp1";
642 643 644 645 646 647 648 649 650 651 652 653 654 655
			usb2_phy: usb2phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
				ctrl-module = <&omap_control_usb>;
			};

			usb3_phy: usb3phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80>,
				      <0x4a084800 0x64>,
				      <0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <&omap_control_usb>;
			};
656
		};
657 658
	};
};