amdgpu_dm.c 142.3 KB
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/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services_types.h"
#include "dc.h"
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#include "dc/inc/core_types.h"
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#include "vid.h"
#include "amdgpu.h"
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#include "amdgpu_display.h"
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#include "atom.h"
#include "amdgpu_dm.h"
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#include "amdgpu_pm.h"
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#include "amd_shared.h"
#include "amdgpu_dm_irq.h"
#include "dm_helpers.h"
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#include "dm_services_types.h"
#include "amdgpu_dm_mst_types.h"
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#if defined(CONFIG_DEBUG_FS)
#include "amdgpu_dm_debugfs.h"
#endif
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#include "ivsrcid/ivsrcid_vislands30.h"

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/pm_runtime.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_dp_mst_helper.h>
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#include <drm/drm_fb_helper.h>
#include <drm/drm_edid.h>
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#include "modules/inc/mod_freesync.h"

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#ifdef CONFIG_X86
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#include "ivsrcid/irqsrcs_dcn_1_0.h"

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#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
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#include "soc15_hw_ip.h"
#include "vega10_ip_offset.h"
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#include "soc15_common.h"
#endif

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#include "modules/inc/mod_freesync.h"

#include "i2caux_interface.h"

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/* basic init/fini API */
static int amdgpu_dm_init(struct amdgpu_device *adev);
static void amdgpu_dm_fini(struct amdgpu_device *adev);

/* initializes drm_device display related structures, based on the information
 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 * drm_encoder, drm_mode_config
 *
 * Returns 0 on success
 */
static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
/* removes and deallocates the drm structures, created by the above function */
static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);

static void
amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);

static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
				struct amdgpu_plane *aplane,
				unsigned long possible_crtcs);
static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
			       struct drm_plane *plane,
			       uint32_t link_index);
static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
				    struct amdgpu_dm_connector *amdgpu_dm_connector,
				    uint32_t link_index,
				    struct amdgpu_encoder *amdgpu_encoder);
static int amdgpu_dm_encoder_init(struct drm_device *dev,
				  struct amdgpu_encoder *aencoder,
				  uint32_t link_index);

static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);

static int amdgpu_dm_atomic_commit(struct drm_device *dev,
				   struct drm_atomic_state *state,
				   bool nonblock);

static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);

static int amdgpu_dm_atomic_check(struct drm_device *dev,
				  struct drm_atomic_state *state);



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static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
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	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
};

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static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
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	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
};

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static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
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	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_PRIMARY,
	DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
};

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/*
 * dm_vblank_get_counter
 *
 * @brief
 * Get counter for number of vertical blanks
 *
 * @param
 * struct amdgpu_device *adev - [in] desired amdgpu device
 * int disp_idx - [in] which CRTC to get the counter from
 *
 * @return
 * Counter for vertical blanks
 */
static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
{
	if (crtc >= adev->mode_info.num_crtc)
		return 0;
	else {
		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
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		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
				acrtc->base.state);
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		if (acrtc_state->stream == NULL) {
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			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
				  crtc);
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			return 0;
		}

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		return dc_stream_get_vblank_counter(acrtc_state->stream);
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	}
}

static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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				  u32 *vbl, u32 *position)
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{
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	uint32_t v_blank_start, v_blank_end, h_position, v_position;

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	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
		return -EINVAL;
	else {
		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
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		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
						acrtc->base.state);
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		if (acrtc_state->stream ==  NULL) {
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			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
				  crtc);
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			return 0;
		}

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		/*
		 * TODO rework base driver to use values directly.
		 * for now parse it back into reg-format
		 */
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		dc_stream_get_scanoutpos(acrtc_state->stream,
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					 &v_blank_start,
					 &v_blank_end,
					 &h_position,
					 &v_position);

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		*position = v_position | (h_position << 16);
		*vbl = v_blank_start | (v_blank_end << 16);
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	}

	return 0;
}

static bool dm_is_idle(void *handle)
{
	/* XXX todo */
	return true;
}

static int dm_wait_for_idle(void *handle)
{
	/* XXX todo */
	return 0;
}

static bool dm_check_soft_reset(void *handle)
{
	return false;
}

static int dm_soft_reset(void *handle)
{
	/* XXX todo */
	return 0;
}

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static struct amdgpu_crtc *
get_crtc_by_otg_inst(struct amdgpu_device *adev,
		     int otg_inst)
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{
	struct drm_device *dev = adev->ddev;
	struct drm_crtc *crtc;
	struct amdgpu_crtc *amdgpu_crtc;

	/*
	 * following if is check inherited from both functions where this one is
	 * used now. Need to be checked why it could happen.
	 */
	if (otg_inst == -1) {
		WARN_ON(1);
		return adev->mode_info.crtcs[0];
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		amdgpu_crtc = to_amdgpu_crtc(crtc);

		if (amdgpu_crtc->otg_inst == otg_inst)
			return amdgpu_crtc;
	}

	return NULL;
}

static void dm_pflip_high_irq(void *interrupt_params)
{
	struct amdgpu_crtc *amdgpu_crtc;
	struct common_irq_params *irq_params = interrupt_params;
	struct amdgpu_device *adev = irq_params->adev;
	unsigned long flags;

	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);

	/* IRQ could occur when in initial stage */
	/*TODO work and BO cleanup */
	if (amdgpu_crtc == NULL) {
		DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
		return;
	}

	spin_lock_irqsave(&adev->ddev->event_lock, flags);

	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
						 amdgpu_crtc->pflip_status,
						 AMDGPU_FLIP_SUBMITTED,
						 amdgpu_crtc->crtc_id,
						 amdgpu_crtc);
		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
		return;
	}


	/* wakeup usersapce */
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	if (amdgpu_crtc->event) {
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		/* Update to correct count/ts if racing with vblank irq */
		drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);

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		drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
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		/* page flip completed. clean up */
		amdgpu_crtc->event = NULL;
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	} else
		WARN_ON(1);
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	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
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	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);

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	DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
					__func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
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	drm_crtc_vblank_put(&amdgpu_crtc->base);
}

static void dm_crtc_high_irq(void *interrupt_params)
{
	struct common_irq_params *irq_params = interrupt_params;
	struct amdgpu_device *adev = irq_params->adev;
	uint8_t crtc_index = 0;
	struct amdgpu_crtc *acrtc;

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	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
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	if (acrtc)
		crtc_index = acrtc->crtc_id;

	drm_handle_vblank(adev->ddev, crtc_index);
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	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
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}

static int dm_set_clockgating_state(void *handle,
		  enum amd_clockgating_state state)
{
	return 0;
}

static int dm_set_powergating_state(void *handle,
		  enum amd_powergating_state state)
{
	return 0;
}

/* Prototypes of private functions */
static int dm_early_init(void* handle);

static void hotplug_notify_work_func(struct work_struct *work)
{
	struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
	struct drm_device *dev = dm->ddev;

	drm_kms_helper_hotplug_event(dev);
}

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/* Allocate memory for FBC compressed data  */
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static void amdgpu_dm_fbc_init(struct drm_connector *connector)
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{
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	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
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	struct dm_comressor_info *compressor = &adev->dm.compressor;
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	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
	struct drm_display_mode *mode;
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	unsigned long max_size = 0;

	if (adev->dm.dc->fbc_compressor == NULL)
		return;
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	if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
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		return;

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	if (compressor->bo_ptr)
		return;
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	list_for_each_entry(mode, &connector->modes, head) {
		if (max_size < mode->htotal * mode->vtotal)
			max_size = mode->htotal * mode->vtotal;
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	}

	if (max_size) {
		int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
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			    AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
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			    &compressor->gpu_addr, &compressor->cpu_addr);
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		if (r)
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			DRM_ERROR("DM: Failed to initialize FBC\n");
		else {
			adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
			DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
		}

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	}

}


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/* Init display KMS
 *
 * Returns 0 on success
 */
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static int amdgpu_dm_init(struct amdgpu_device *adev)
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{
	struct dc_init_data init_data;
	adev->dm.ddev = adev->ddev;
	adev->dm.adev = adev;

	/* Zero all the fields */
	memset(&init_data, 0, sizeof(init_data));

	if(amdgpu_dm_irq_init(adev)) {
		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
		goto error;
	}

	init_data.asic_id.chip_family = adev->family;

	init_data.asic_id.pci_revision_id = adev->rev_id;
	init_data.asic_id.hw_internal_rev = adev->external_rev_id;

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	init_data.asic_id.vram_width = adev->gmc.vram_width;
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	/* TODO: initialize init_data.asic_id.vram_type here!!!! */
	init_data.asic_id.atombios_base_address =
		adev->mode_info.atom_context->bios;

	init_data.driver = adev;

	adev->dm.cgs_device = amdgpu_cgs_create_device(adev);

	if (!adev->dm.cgs_device) {
		DRM_ERROR("amdgpu: failed to create cgs device.\n");
		goto error;
	}

	init_data.cgs_device = adev->dm.cgs_device;

	adev->dm.dal = NULL;

	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;

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	/*
	 * TODO debug why this doesn't work on Raven
	 */
	if (adev->flags & AMD_IS_APU &&
	    adev->asic_type >= CHIP_CARRIZO &&
	    adev->asic_type < CHIP_RAVEN)
		init_data.flags.gpu_vm_support = true;

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	/* Display Core create. */
	adev->dm.dc = dc_create(&init_data);

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	if (adev->dm.dc) {
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		DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
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	} else {
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		DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
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		goto error;
	}
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	INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);

	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
	if (!adev->dm.freesync_module) {
		DRM_ERROR(
		"amdgpu: failed to initialize freesync_module.\n");
	} else
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		DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
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				adev->dm.freesync_module);

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	amdgpu_dm_init_color_mod();

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	if (amdgpu_dm_initialize_drm_device(adev)) {
		DRM_ERROR(
		"amdgpu: failed to initialize sw for display support.\n");
		goto error;
	}

	/* Update the actual used number of crtc */
	adev->mode_info.num_crtc = adev->dm.display_indexes_num;

	/* TODO: Add_display_info? */

	/* TODO use dynamic cursor width */
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	adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
	adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
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	if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
		DRM_ERROR(
		"amdgpu: failed to initialize sw for display support.\n");
		goto error;
	}

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	DRM_DEBUG_DRIVER("KMS initialized.\n");
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	return 0;
error:
	amdgpu_dm_fini(adev);

	return -1;
}

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static void amdgpu_dm_fini(struct amdgpu_device *adev)
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{
	amdgpu_dm_destroy_drm_device(&adev->dm);
	/*
	 * TODO: pageflip, vlank interrupt
	 *
	 * amdgpu_dm_irq_fini(adev);
	 */

	if (adev->dm.cgs_device) {
		amdgpu_cgs_destroy_device(adev->dm.cgs_device);
		adev->dm.cgs_device = NULL;
	}
	if (adev->dm.freesync_module) {
		mod_freesync_destroy(adev->dm.freesync_module);
		adev->dm.freesync_module = NULL;
	}
	/* DC Destroy TODO: Replace destroy DAL */
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	if (adev->dm.dc)
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		dc_destroy(&adev->dm.dc);
	return;
}

static int dm_sw_init(void *handle)
{
	return 0;
}

static int dm_sw_fini(void *handle)
{
	return 0;
}

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static int detect_mst_link_for_all_connectors(struct drm_device *dev)
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{
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	struct amdgpu_dm_connector *aconnector;
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	struct drm_connector *connector;
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	int ret = 0;
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	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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		aconnector = to_amdgpu_dm_connector(connector);
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		if (aconnector->dc_link->type == dc_connection_mst_branch &&
		    aconnector->mst_mgr.aux) {
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			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
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					aconnector, aconnector->base.base.id);

			ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
			if (ret < 0) {
				DRM_ERROR("DM_MST: Failed to start MST\n");
				((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
				return ret;
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				}
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			}
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	}

	drm_modeset_unlock(&dev->mode_config.connection_mutex);
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	return ret;
}

static int dm_late_init(void *handle)
{
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	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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	return detect_mst_link_for_all_connectors(adev->ddev);
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}

static void s3_handle_mst(struct drm_device *dev, bool suspend)
{
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	struct amdgpu_dm_connector *aconnector;
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	struct drm_connector *connector;

	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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		   aconnector = to_amdgpu_dm_connector(connector);
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		   if (aconnector->dc_link->type == dc_connection_mst_branch &&
				   !aconnector->mst_port) {

			   if (suspend)
				   drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
			   else
				   drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
		   }
	}

	drm_modeset_unlock(&dev->mode_config.connection_mutex);
}

static int dm_hw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	/* Create DAL display manager */
	amdgpu_dm_init(adev);
	amdgpu_dm_hpd_init(adev);

	return 0;
}

static int dm_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_dm_hpd_fini(adev);

	amdgpu_dm_irq_fini(adev);
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	amdgpu_dm_fini(adev);
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	return 0;
}

static int dm_suspend(void *handle)
{
	struct amdgpu_device *adev = handle;
	struct amdgpu_display_manager *dm = &adev->dm;
	int ret = 0;

	s3_handle_mst(adev->ddev, true);

	amdgpu_dm_irq_suspend(adev);

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	WARN_ON(adev->dm.cached_state);
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	adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);

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	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
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	return ret;
}

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static struct amdgpu_dm_connector *
amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
					     struct drm_crtc *crtc)
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{
	uint32_t i;
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	struct drm_connector_state *new_con_state;
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	struct drm_connector *connector;
	struct drm_crtc *crtc_from_state;

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	for_each_new_connector_in_state(state, connector, new_con_state, i) {
		crtc_from_state = new_con_state->crtc;
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		if (crtc_from_state == crtc)
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			return to_amdgpu_dm_connector(connector);
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	}

	return NULL;
}

static int dm_resume(void *handle)
{
	struct amdgpu_device *adev = handle;
	struct drm_device *ddev = adev->ddev;
	struct amdgpu_display_manager *dm = &adev->dm;
651
	struct amdgpu_dm_connector *aconnector;
652 653
	struct drm_connector *connector;
	struct drm_crtc *crtc;
654
	struct drm_crtc_state *new_crtc_state;
655 656 657 658
	struct dm_crtc_state *dm_new_crtc_state;
	struct drm_plane *plane;
	struct drm_plane_state *new_plane_state;
	struct dm_plane_state *dm_new_plane_state;
659
	int ret;
660
	int i;
661

662 663 664
	/* power on hardware */
	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

665 666 667 668 669 670 671 672 673 674 675 676 677
	/* program HPD filter */
	dc_resume(dm->dc);

	/* On resume we need to  rewrite the MSTM control bits to enamble MST*/
	s3_handle_mst(ddev, false);

	/*
	 * early enable HPD Rx IRQ, should be done before set mode as short
	 * pulse interrupts are used for MST
	 */
	amdgpu_dm_irq_resume_early(adev);

	/* Do detection*/
678
	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
679
		aconnector = to_amdgpu_dm_connector(connector);
680 681 682 683 684 685 686 687

		/*
		 * this is the case when traversing through already created
		 * MST connectors, should be skipped
		 */
		if (aconnector->mst_port)
			continue;

688
		mutex_lock(&aconnector->hpd_lock);
689
		dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
R
Roman Li 已提交
690 691 692 693

		if (aconnector->fake_enable && aconnector->dc_link->local_sink)
			aconnector->fake_enable = false;

694 695
		aconnector->dc_sink = NULL;
		amdgpu_dm_update_connector_after_detect(aconnector);
696
		mutex_unlock(&aconnector->hpd_lock);
697 698
	}

699
	/* Force mode set in atomic comit */
700
	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
701
		new_crtc_state->active_changed = true;
702

703 704 705 706 707
	/*
	 * atomic_check is expected to create the dc states. We need to release
	 * them here, since they were duplicated as part of the suspend
	 * procedure.
	 */
708
	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
709 710 711 712 713 714 715 716
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
		if (dm_new_crtc_state->stream) {
			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
			dc_stream_release(dm_new_crtc_state->stream);
			dm_new_crtc_state->stream = NULL;
		}
	}

717
	for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
718 719 720 721 722 723 724 725
		dm_new_plane_state = to_dm_plane_state(new_plane_state);
		if (dm_new_plane_state->dc_state) {
			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
			dc_plane_state_release(dm_new_plane_state->dc_state);
			dm_new_plane_state->dc_state = NULL;
		}
	}

726
	ret = drm_atomic_helper_resume(ddev, dm->cached_state);
727

728
	dm->cached_state = NULL;
729

730
	amdgpu_dm_irq_resume_late(adev);
731 732 733 734 735 736 737

	return ret;
}

static const struct amd_ip_funcs amdgpu_dm_funcs = {
	.name = "dm",
	.early_init = dm_early_init,
738
	.late_init = dm_late_init,
739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761
	.sw_init = dm_sw_init,
	.sw_fini = dm_sw_fini,
	.hw_init = dm_hw_init,
	.hw_fini = dm_hw_fini,
	.suspend = dm_suspend,
	.resume = dm_resume,
	.is_idle = dm_is_idle,
	.wait_for_idle = dm_wait_for_idle,
	.check_soft_reset = dm_check_soft_reset,
	.soft_reset = dm_soft_reset,
	.set_clockgating_state = dm_set_clockgating_state,
	.set_powergating_state = dm_set_powergating_state,
};

const struct amdgpu_ip_block_version dm_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_DCE,
	.major = 1,
	.minor = 0,
	.rev = 0,
	.funcs = &amdgpu_dm_funcs,
};

762

763
static struct drm_atomic_state *
764 765 766 767
dm_atomic_state_alloc(struct drm_device *dev)
{
	struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);

768
	if (!state)
769
		return NULL;
770 771 772 773

	if (drm_atomic_state_init(dev, &state->base) < 0)
		goto fail;

774
	return &state->base;
775 776 777 778

fail:
	kfree(state);
	return NULL;
779 780
}

781 782 783 784 785 786
static void
dm_atomic_state_clear(struct drm_atomic_state *state)
{
	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);

	if (dm_state->context) {
787
		dc_release_state(dm_state->context);
788 789 790 791 792 793 794 795 796 797 798 799 800 801
		dm_state->context = NULL;
	}

	drm_atomic_state_default_clear(state);
}

static void
dm_atomic_state_alloc_free(struct drm_atomic_state *state)
{
	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
	drm_atomic_state_default_release(state);
	kfree(dm_state);
}

802
static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
803
	.fb_create = amdgpu_display_user_framebuffer_create,
804
	.output_poll_changed = drm_fb_helper_output_poll_changed,
805
	.atomic_check = amdgpu_dm_atomic_check,
806
	.atomic_commit = amdgpu_dm_atomic_commit,
807
	.atomic_state_alloc = dm_atomic_state_alloc,
808 809
	.atomic_state_clear = dm_atomic_state_clear,
	.atomic_state_free = dm_atomic_state_alloc_free
810 811 812 813
};

static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail
814 815
};

816
static void
817
amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
818 819 820
{
	struct drm_connector *connector = &aconnector->base;
	struct drm_device *dev = connector->dev;
821
	struct dc_sink *sink;
822 823 824 825 826 827 828 829 830 831 832 833 834 835 836

	/* MST handled by drm_mst framework */
	if (aconnector->mst_mgr.mst_state == true)
		return;


	sink = aconnector->dc_link->local_sink;

	/* Edid mgmt connector gets first update only in mode_valid hook and then
	 * the connector sink is set to either fake or physical sink depends on link status.
	 * don't do it here if u are during boot
	 */
	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
			&& aconnector->dc_em_sink) {

837
		/* For S3 resume with headless use eml_sink to fake stream
838 839 840 841 842
		 * because on resume connecotr->sink is set ti NULL
		 */
		mutex_lock(&dev->mode_config.mutex);

		if (sink) {
843
			if (aconnector->dc_sink) {
844 845
				amdgpu_dm_remove_sink_from_freesync_module(
								connector);
846 847 848 849 850 851 852 853
				/* retain and release bellow are used for
				 * bump up refcount for sink because the link don't point
				 * to it anymore after disconnect so on next crtc to connector
				 * reshuffle by UMD we will get into unwanted dc_sink release
				 */
				if (aconnector->dc_sink != aconnector->dc_em_sink)
					dc_sink_release(aconnector->dc_sink);
			}
854 855 856 857 858 859 860
			aconnector->dc_sink = sink;
			amdgpu_dm_add_sink_to_freesync_module(
						connector, aconnector->edid);
		} else {
			amdgpu_dm_remove_sink_from_freesync_module(connector);
			if (!aconnector->dc_sink)
				aconnector->dc_sink = aconnector->dc_em_sink;
861 862
			else if (aconnector->dc_sink != aconnector->dc_em_sink)
				dc_sink_retain(aconnector->dc_sink);
863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878
		}

		mutex_unlock(&dev->mode_config.mutex);
		return;
	}

	/*
	 * TODO: temporary guard to look for proper fix
	 * if this sink is MST sink, we should not do anything
	 */
	if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
		return;

	if (aconnector->dc_sink == sink) {
		/* We got a DP short pulse (Link Loss, DP CTS, etc...).
		 * Do nothing!! */
879
		DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
880 881 882 883
				aconnector->connector_id);
		return;
	}

884
	DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
885 886 887 888 889 890 891 892 893 894 895 896 897 898
		aconnector->connector_id, aconnector->dc_sink, sink);

	mutex_lock(&dev->mode_config.mutex);

	/* 1. Update status of the drm connector
	 * 2. Send an event and let userspace tell us what to do */
	if (sink) {
		/* TODO: check if we still need the S3 mode update workaround.
		 * If yes, put it here. */
		if (aconnector->dc_sink)
			amdgpu_dm_remove_sink_from_freesync_module(
							connector);

		aconnector->dc_sink = sink;
899
		if (sink->dc_edid.length == 0) {
900
			aconnector->edid = NULL;
901
		} else {
902 903 904 905
			aconnector->edid =
				(struct edid *) sink->dc_edid.raw_edid;


906
			drm_connector_update_edid_property(connector,
907 908 909 910 911 912
					aconnector->edid);
		}
		amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);

	} else {
		amdgpu_dm_remove_sink_from_freesync_module(connector);
913
		drm_connector_update_edid_property(connector, NULL);
914 915
		aconnector->num_modes = 0;
		aconnector->dc_sink = NULL;
916
		aconnector->edid = NULL;
917 918 919 920 921 922 923
	}

	mutex_unlock(&dev->mode_config.mutex);
}

static void handle_hpd_irq(void *param)
{
924
	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
925 926 927 928 929 930 931
	struct drm_connector *connector = &aconnector->base;
	struct drm_device *dev = connector->dev;

	/* In case of failure or MST no need to update connector status or notify the OS
	 * since (for MST case) MST does this in it's own context.
	 */
	mutex_lock(&aconnector->hpd_lock);
932 933 934 935

	if (aconnector->fake_enable)
		aconnector->fake_enable = false;

936
	if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
937 938 939 940 941 942 943 944 945 946 947 948 949 950
		amdgpu_dm_update_connector_after_detect(aconnector);


		drm_modeset_lock_all(dev);
		dm_restore_drm_connector_state(dev, connector);
		drm_modeset_unlock_all(dev);

		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
			drm_kms_helper_hotplug_event(dev);
	}
	mutex_unlock(&aconnector->hpd_lock);

}

951
static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986
{
	uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
	uint8_t dret;
	bool new_irq_handled = false;
	int dpcd_addr;
	int dpcd_bytes_to_read;

	const int max_process_count = 30;
	int process_count = 0;

	const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);

	if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
		dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
		/* DPCD 0x200 - 0x201 for downstream IRQ */
		dpcd_addr = DP_SINK_COUNT;
	} else {
		dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
		/* DPCD 0x2002 - 0x2005 for downstream IRQ */
		dpcd_addr = DP_SINK_COUNT_ESI;
	}

	dret = drm_dp_dpcd_read(
		&aconnector->dm_dp_aux.aux,
		dpcd_addr,
		esi,
		dpcd_bytes_to_read);

	while (dret == dpcd_bytes_to_read &&
		process_count < max_process_count) {
		uint8_t retry;
		dret = 0;

		process_count++;

987
		DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019
		/* handle HPD short pulse irq */
		if (aconnector->mst_mgr.mst_state)
			drm_dp_mst_hpd_irq(
				&aconnector->mst_mgr,
				esi,
				&new_irq_handled);

		if (new_irq_handled) {
			/* ACK at DPCD to notify down stream */
			const int ack_dpcd_bytes_to_write =
				dpcd_bytes_to_read - 1;

			for (retry = 0; retry < 3; retry++) {
				uint8_t wret;

				wret = drm_dp_dpcd_write(
					&aconnector->dm_dp_aux.aux,
					dpcd_addr + 1,
					&esi[1],
					ack_dpcd_bytes_to_write);
				if (wret == ack_dpcd_bytes_to_write)
					break;
			}

			/* check if there is new irq to be handle */
			dret = drm_dp_dpcd_read(
				&aconnector->dm_dp_aux.aux,
				dpcd_addr,
				esi,
				dpcd_bytes_to_read);

			new_irq_handled = false;
1020
		} else {
1021
			break;
1022
		}
1023 1024 1025
	}

	if (process_count == max_process_count)
1026
		DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1027 1028 1029 1030
}

static void handle_hpd_rx_irq(void *param)
{
1031
	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1032 1033
	struct drm_connector *connector = &aconnector->base;
	struct drm_device *dev = connector->dev;
1034
	struct dc_link *dc_link = aconnector->dc_link;
1035 1036 1037 1038 1039 1040
	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;

	/* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
	 * conflict, after implement i2c helper, this mutex should be
	 * retired.
	 */
1041
	if (dc_link->type != dc_connection_mst_branch)
1042 1043
		mutex_lock(&aconnector->hpd_lock);

1044
	if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1045 1046
			!is_mst_root_connector) {
		/* Downstream Port status changed. */
1047
		if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1048 1049 1050 1051

			if (aconnector->fake_enable)
				aconnector->fake_enable = false;

1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062
			amdgpu_dm_update_connector_after_detect(aconnector);


			drm_modeset_lock_all(dev);
			dm_restore_drm_connector_state(dev, connector);
			drm_modeset_unlock_all(dev);

			drm_kms_helper_hotplug_event(dev);
		}
	}
	if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1063
	    (dc_link->type == dc_connection_mst_branch))
1064 1065
		dm_handle_hpd_rx_irq(aconnector);

1066
	if (dc_link->type != dc_connection_mst_branch)
1067 1068 1069 1070 1071 1072 1073
		mutex_unlock(&aconnector->hpd_lock);
}

static void register_hpd_handlers(struct amdgpu_device *adev)
{
	struct drm_device *dev = adev->ddev;
	struct drm_connector *connector;
1074
	struct amdgpu_dm_connector *aconnector;
1075 1076 1077 1078 1079 1080 1081 1082 1083
	const struct dc_link *dc_link;
	struct dc_interrupt_params int_params = {0};

	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

	list_for_each_entry(connector,
			&dev->mode_config.connector_list, head)	{

1084
		aconnector = to_amdgpu_dm_connector(connector);
1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116
		dc_link = aconnector->dc_link;

		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
			int_params.irq_source = dc_link->irq_source_hpd;

			amdgpu_dm_irq_register_interrupt(adev, &int_params,
					handle_hpd_irq,
					(void *) aconnector);
		}

		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {

			/* Also register for DP short pulse (hpd_rx). */
			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
			int_params.irq_source =	dc_link->irq_source_hpd_rx;

			amdgpu_dm_irq_register_interrupt(adev, &int_params,
					handle_hpd_rx_irq,
					(void *) aconnector);
		}
	}
}

/* Register IRQ sources and initialize IRQ callbacks */
static int dce110_register_irq_handlers(struct amdgpu_device *adev)
{
	struct dc *dc = adev->dm.dc;
	struct common_irq_params *c_irq_params;
	struct dc_interrupt_params int_params = {0};
	int r;
	int i;
1117 1118
	unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;

1119
	if (adev->asic_type == CHIP_VEGA10 ||
1120
	    adev->asic_type == CHIP_VEGA12 ||
1121
	    adev->asic_type == CHIP_VEGA20 ||
1122
	    adev->asic_type == CHIP_RAVEN)
1123
		client_id = SOC15_IH_CLIENTID_DCE;
1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137

	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

	/* Actions of amdgpu_irq_add_id():
	 * 1. Register a set() function with base driver.
	 *    Base driver will call set() function to enable/disable an
	 *    interrupt in DC hardware.
	 * 2. Register amdgpu_dm_irq_handler().
	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
	 *    coming from DC hardware.
	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
	 *    for acknowledging and handling. */

1138
	/* Use VBLANK interrupt */
1139
	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1140
		r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1141 1142 1143 1144 1145 1146 1147
		if (r) {
			DRM_ERROR("Failed to add crtc irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
1148
			dc_interrupt_to_irq_source(dc, i, 0);
1149

1150
		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1151 1152 1153 1154 1155 1156 1157 1158

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_crtc_high_irq, c_irq_params);
	}

1159
	/* Use GRPH_PFLIP interrupt */
1160 1161
	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1162
		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182
		if (r) {
			DRM_ERROR("Failed to add page flip irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_pflip_high_irq, c_irq_params);

	}

	/* HPD */
1183 1184
	r = amdgpu_irq_add_id(adev, client_id,
			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1185 1186 1187 1188 1189 1190 1191 1192 1193 1194
	if (r) {
		DRM_ERROR("Failed to add hpd irq id!\n");
		return r;
	}

	register_hpd_handlers(adev);

	return 0;
}

1195
#ifdef CONFIG_X86
1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
/* Register IRQ sources and initialize IRQ callbacks */
static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
{
	struct dc *dc = adev->dm.dc;
	struct common_irq_params *c_irq_params;
	struct dc_interrupt_params int_params = {0};
	int r;
	int i;

	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

	/* Actions of amdgpu_irq_add_id():
	 * 1. Register a set() function with base driver.
	 *    Base driver will call set() function to enable/disable an
	 *    interrupt in DC hardware.
	 * 2. Register amdgpu_dm_irq_handler().
	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
	 *    coming from DC hardware.
	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
	 *    for acknowledging and handling.
	 * */

	/* Use VSTARTUP interrupt */
	for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
			i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
			i++) {
1223
		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246

		if (r) {
			DRM_ERROR("Failed to add crtc irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_crtc_high_irq, c_irq_params);
	}

	/* Use GRPH_PFLIP interrupt */
	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
			i++) {
1247
		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267
		if (r) {
			DRM_ERROR("Failed to add page flip irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_pflip_high_irq, c_irq_params);

	}

	/* HPD */
1268
	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
			&adev->hpd_irq);
	if (r) {
		DRM_ERROR("Failed to add hpd irq id!\n");
		return r;
	}

	register_hpd_handlers(adev);

	return 0;
}
#endif

1281 1282 1283 1284 1285 1286 1287
static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
{
	int r;

	adev->mode_info.mode_config_initialized = true;

	adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1288
	adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1289 1290 1291 1292 1293 1294 1295 1296 1297

	adev->ddev->mode_config.max_width = 16384;
	adev->ddev->mode_config.max_height = 16384;

	adev->ddev->mode_config.preferred_depth = 24;
	adev->ddev->mode_config.prefer_shadow = 1;
	/* indicate support of immediate flip */
	adev->ddev->mode_config.async_page_flip = true;

1298
	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1299

1300
	r = amdgpu_display_modeset_create_props(adev);
1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
	if (r)
		return r;

	return 0;
}

#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
{
	struct amdgpu_display_manager *dm = bl_get_data(bd);

	if (dc_link_set_backlight_level(dm->backlight_link,
			bd->props.brightness, 0, 0))
		return 0;
	else
		return 1;
}

static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
{
	return bd->props.brightness;
}

static const struct backlight_ops amdgpu_dm_backlight_ops = {
	.get_brightness = amdgpu_dm_backlight_get_brightness,
	.update_status	= amdgpu_dm_backlight_update_status,
};

1331 1332
static void
amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348
{
	char bl_name[16];
	struct backlight_properties props = { 0 };

	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
	props.type = BACKLIGHT_RAW;

	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
			dm->adev->ddev->primary->index);

	dm->backlight_dev = backlight_device_register(bl_name,
			dm->adev->ddev->dev,
			dm,
			&amdgpu_dm_backlight_ops,
			&props);

1349
	if (IS_ERR(dm->backlight_dev))
1350 1351
		DRM_ERROR("DM: Backlight registration failed!\n");
	else
1352
		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1353 1354 1355 1356
}

#endif

1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393
static int initialize_plane(struct amdgpu_display_manager *dm,
			     struct amdgpu_mode_info *mode_info,
			     int plane_id)
{
	struct amdgpu_plane *plane;
	unsigned long possible_crtcs;
	int ret = 0;

	plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
	mode_info->planes[plane_id] = plane;

	if (!plane) {
		DRM_ERROR("KMS: Failed to allocate plane\n");
		return -ENOMEM;
	}
	plane->base.type = mode_info->plane_type[plane_id];

	/*
	 * HACK: IGT tests expect that each plane can only have one
	 * one possible CRTC. For now, set one CRTC for each
	 * plane that is not an underlay, but still allow multiple
	 * CRTCs for underlay planes.
	 */
	possible_crtcs = 1 << plane_id;
	if (plane_id >= dm->dc->caps.max_streams)
		possible_crtcs = 0xff;

	ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);

	if (ret) {
		DRM_ERROR("KMS: Failed to initialize plane\n");
		return ret;
	}

	return ret;
}

1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415

static void register_backlight_device(struct amdgpu_display_manager *dm,
				      struct dc_link *link)
{
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
	    link->type != dc_connection_none) {
		/* Event if registration failed, we should continue with
		 * DM initialization because not having a backlight control
		 * is better then a black screen.
		 */
		amdgpu_dm_register_backlight_device(dm);

		if (dm->backlight_dev)
			dm->backlight_link = link;
	}
#endif
}


1416 1417 1418 1419 1420 1421 1422
/* In this architecture, the association
 * connector -> encoder -> crtc
 * id not really requried. The crtc and connector will hold the
 * display_index as an abstraction to use with DAL component
 *
 * Returns 0 on success
 */
1423
static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1424 1425
{
	struct amdgpu_display_manager *dm = &adev->dm;
1426
	int32_t i;
1427
	struct amdgpu_dm_connector *aconnector = NULL;
1428
	struct amdgpu_encoder *aencoder = NULL;
1429
	struct amdgpu_mode_info *mode_info = &adev->mode_info;
1430
	uint32_t link_cnt;
1431
	int32_t total_overlay_planes, total_primary_planes;
1432 1433 1434 1435

	link_cnt = dm->dc->caps.max_links;
	if (amdgpu_dm_mode_config_init(dm->adev)) {
		DRM_ERROR("DM: Failed to initialize mode config\n");
1436
		return -1;
1437 1438
	}

1439 1440 1441
	/* Identify the number of planes to be initialized */
	total_overlay_planes = dm->dc->caps.max_slave_planes;
	total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1442

1443 1444 1445 1446
	/* First initialize overlay planes, index starting after primary planes */
	for (i = (total_overlay_planes - 1); i >= 0; i--) {
		if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
			DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1447
			goto fail;
1448
		}
1449
	}
1450

1451 1452 1453 1454
	/* Initialize primary planes */
	for (i = (total_primary_planes - 1); i >= 0; i--) {
		if (initialize_plane(dm, mode_info, i)) {
			DRM_ERROR("KMS: Failed to initialize primary plane\n");
1455
			goto fail;
1456 1457
		}
	}
1458

1459 1460
	for (i = 0; i < dm->dc->caps.max_streams; i++)
		if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1461
			DRM_ERROR("KMS: Failed to initialize crtc\n");
1462
			goto fail;
1463 1464
		}

1465
	dm->display_indexes_num = dm->dc->caps.max_streams;
1466 1467 1468

	/* loops over all connectors on the board */
	for (i = 0; i < link_cnt; i++) {
1469
		struct dc_link *link = NULL;
1470 1471 1472 1473 1474 1475 1476 1477 1478 1479

		if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
			DRM_ERROR(
				"KMS: Cannot support more than %d display indexes\n",
					AMDGPU_DM_MAX_DISPLAY_INDEX);
			continue;
		}

		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
		if (!aconnector)
1480
			goto fail;
1481 1482

		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1483
		if (!aencoder)
1484
			goto fail;
1485 1486 1487

		if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
			DRM_ERROR("KMS: Failed to initialize encoder\n");
1488
			goto fail;
1489 1490 1491 1492
		}

		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
			DRM_ERROR("KMS: Failed to initialize connector\n");
1493
			goto fail;
1494 1495
		}

1496 1497 1498
		link = dc_get_link_at_index(dm->dc, i);

		if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1499
			amdgpu_dm_update_connector_after_detect(aconnector);
1500 1501 1502 1503
			register_backlight_device(dm, link);
		}


1504 1505 1506 1507 1508 1509
	}

	/* Software is initialized. Now we can register interrupt handlers. */
	switch (adev->asic_type) {
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
1510 1511 1512
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_MULLINS:
1513 1514 1515 1516 1517 1518
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_CARRIZO:
	case CHIP_STONEY:
	case CHIP_POLARIS11:
	case CHIP_POLARIS10:
1519
	case CHIP_POLARIS12:
1520
	case CHIP_VEGAM:
1521
	case CHIP_VEGA10:
1522
	case CHIP_VEGA12:
1523
	case CHIP_VEGA20:
1524 1525
		if (dce110_register_irq_handlers(dm->adev)) {
			DRM_ERROR("DM: Failed to initialize IRQ\n");
1526
			goto fail;
1527 1528
		}
		break;
1529
#ifdef CONFIG_X86
1530 1531 1532
	case CHIP_RAVEN:
		if (dcn10_register_irq_handlers(dm->adev)) {
			DRM_ERROR("DM: Failed to initialize IRQ\n");
1533
			goto fail;
1534 1535 1536
		}
		break;
#endif
1537
	default:
1538
		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1539
		goto fail;
1540 1541
	}

1542 1543 1544
	if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
		dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;

1545
	return 0;
1546
fail:
1547 1548
	kfree(aencoder);
	kfree(aconnector);
1549
	for (i = 0; i < dm->dc->caps.max_planes; i++)
1550
		kfree(mode_info->planes[i]);
1551 1552 1553
	return -1;
}

1554
static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572
{
	drm_mode_config_cleanup(dm->ddev);
	return;
}

/******************************************************************************
 * amdgpu_display_funcs functions
 *****************************************************************************/

/**
 * dm_bandwidth_update - program display watermarks
 *
 * @adev: amdgpu_device pointer
 *
 * Calculate and program the display watermarks and line buffer allocation.
 */
static void dm_bandwidth_update(struct amdgpu_device *adev)
{
1573
	/* TODO: implement later */
1574 1575 1576 1577 1578 1579
}

static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
				struct drm_file *filp)
{
	struct mod_freesync_params freesync_params;
1580
	uint8_t num_streams;
1581 1582 1583 1584 1585 1586 1587
	uint8_t i;

	struct amdgpu_device *adev = dev->dev_private;
	int r = 0;

	/* Get freesync enable flag from DRM */

1588
	num_streams = dc_get_current_stream_count(adev->dm.dc);
1589

1590
	for (i = 0; i < num_streams; i++) {
1591
		struct dc_stream_state *stream;
1592
		stream = dc_get_stream_at_index(adev->dm.dc, i);
1593 1594

		mod_freesync_update_state(adev->dm.freesync_module,
1595
					  &stream, 1, &freesync_params);
1596 1597 1598 1599 1600
	}

	return r;
}

1601
static const struct amdgpu_display_funcs dm_display_funcs = {
1602 1603
	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1604 1605
	.backlight_set_level = NULL, /* never called for DC */
	.backlight_get_level = NULL, /* never called for DC */
1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618
	.hpd_sense = NULL,/* called unconditionally */
	.hpd_set_polarity = NULL, /* called unconditionally */
	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
	.page_flip_get_scanoutpos =
		dm_crtc_get_scanoutpos,/* called unconditionally */
	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
	.notify_freesync = amdgpu_notify_freesync,

};

#if defined(CONFIG_DEBUG_KERNEL_DC)

1619 1620 1621 1622
static ssize_t s3_debug_store(struct device *device,
			      struct device_attribute *attr,
			      const char *buf,
			      size_t count)
1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
{
	int ret;
	int s3_state;
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
	struct amdgpu_device *adev = drm_dev->dev_private;

	ret = kstrtoint(buf, 0, &s3_state);

	if (ret == 0) {
		if (s3_state) {
			dm_resume(adev);
			drm_kms_helper_hotplug_event(adev->ddev);
		} else
			dm_suspend(adev);
	}

	return ret == 0 ? count : 0;
}

DEVICE_ATTR_WO(s3_debug);

#endif

static int dm_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	switch (adev->asic_type) {
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
1657
		adev->mode_info.plane_type = dm_plane_type_default;
1658
		break;
1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671
	case CHIP_KAVERI:
		adev->mode_info.num_crtc = 4;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 7;
		adev->mode_info.plane_type = dm_plane_type_default;
		break;
	case CHIP_KABINI:
	case CHIP_MULLINS:
		adev->mode_info.num_crtc = 2;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
		adev->mode_info.plane_type = dm_plane_type_default;
		break;
1672 1673 1674 1675 1676
	case CHIP_FIJI:
	case CHIP_TONGA:
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 7;
1677
		adev->mode_info.plane_type = dm_plane_type_default;
1678 1679 1680 1681 1682
		break;
	case CHIP_CARRIZO:
		adev->mode_info.num_crtc = 3;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 9;
1683
		adev->mode_info.plane_type = dm_plane_type_carizzo;
1684 1685 1686 1687 1688
		break;
	case CHIP_STONEY:
		adev->mode_info.num_crtc = 2;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 9;
1689
		adev->mode_info.plane_type = dm_plane_type_stoney;
1690 1691
		break;
	case CHIP_POLARIS11:
1692
	case CHIP_POLARIS12:
1693 1694 1695
		adev->mode_info.num_crtc = 5;
		adev->mode_info.num_hpd = 5;
		adev->mode_info.num_dig = 5;
1696
		adev->mode_info.plane_type = dm_plane_type_default;
1697 1698
		break;
	case CHIP_POLARIS10:
1699
	case CHIP_VEGAM:
1700 1701 1702
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
1703
		adev->mode_info.plane_type = dm_plane_type_default;
1704
		break;
1705
	case CHIP_VEGA10:
1706
	case CHIP_VEGA12:
1707
	case CHIP_VEGA20:
1708 1709 1710
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
1711
		adev->mode_info.plane_type = dm_plane_type_default;
1712
		break;
1713
#ifdef CONFIG_X86
1714 1715 1716 1717
	case CHIP_RAVEN:
		adev->mode_info.num_crtc = 4;
		adev->mode_info.num_hpd = 4;
		adev->mode_info.num_dig = 4;
1718
		adev->mode_info.plane_type = dm_plane_type_default;
1719 1720
		break;
#endif
1721
	default:
1722
		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1723 1724 1725
		return -EINVAL;
	}

1726 1727
	amdgpu_dm_set_irq_funcs(adev);

1728 1729 1730
	if (adev->mode_info.funcs == NULL)
		adev->mode_info.funcs = &dm_display_funcs;

1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742
	/* Note: Do NOT change adev->audio_endpt_rreg and
	 * adev->audio_endpt_wreg because they are initialised in
	 * amdgpu_device_init() */
#if defined(CONFIG_DEBUG_KERNEL_DC)
	device_create_file(
		adev->ddev->dev,
		&dev_attr_s3_debug);
#endif

	return 0;
}

1743
static bool modeset_required(struct drm_crtc_state *crtc_state,
1744 1745
			     struct dc_stream_state *new_stream,
			     struct dc_stream_state *old_stream)
1746
{
1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763
	if (!drm_atomic_crtc_needs_modeset(crtc_state))
		return false;

	if (!crtc_state->enable)
		return false;

	return crtc_state->active;
}

static bool modereset_required(struct drm_crtc_state *crtc_state)
{
	if (!drm_atomic_crtc_needs_modeset(crtc_state))
		return false;

	return !crtc_state->enable || !crtc_state->active;
}

1764
static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1765 1766 1767 1768 1769 1770 1771 1772 1773
{
	drm_encoder_cleanup(encoder);
	kfree(encoder);
}

static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
	.destroy = amdgpu_dm_encoder_destroy,
};

1774 1775
static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
					struct dc_plane_state *plane_state)
1776
{
1777 1778
	plane_state->src_rect.x = state->src_x >> 16;
	plane_state->src_rect.y = state->src_y >> 16;
1779
	/*we ignore for now mantissa and do not to deal with floating pixels :(*/
1780
	plane_state->src_rect.width = state->src_w >> 16;
1781

1782
	if (plane_state->src_rect.width == 0)
1783 1784
		return false;

1785 1786
	plane_state->src_rect.height = state->src_h >> 16;
	if (plane_state->src_rect.height == 0)
1787 1788
		return false;

1789 1790
	plane_state->dst_rect.x = state->crtc_x;
	plane_state->dst_rect.y = state->crtc_y;
1791 1792 1793 1794

	if (state->crtc_w == 0)
		return false;

1795
	plane_state->dst_rect.width = state->crtc_w;
1796 1797 1798 1799

	if (state->crtc_h == 0)
		return false;

1800
	plane_state->dst_rect.height = state->crtc_h;
1801

1802
	plane_state->clip_rect = plane_state->dst_rect;
1803 1804 1805

	switch (state->rotation & DRM_MODE_ROTATE_MASK) {
	case DRM_MODE_ROTATE_0:
1806
		plane_state->rotation = ROTATION_ANGLE_0;
1807 1808
		break;
	case DRM_MODE_ROTATE_90:
1809
		plane_state->rotation = ROTATION_ANGLE_90;
1810 1811
		break;
	case DRM_MODE_ROTATE_180:
1812
		plane_state->rotation = ROTATION_ANGLE_180;
1813 1814
		break;
	case DRM_MODE_ROTATE_270:
1815
		plane_state->rotation = ROTATION_ANGLE_270;
1816 1817
		break;
	default:
1818
		plane_state->rotation = ROTATION_ANGLE_0;
1819 1820 1821
		break;
	}

1822 1823
	return true;
}
1824
static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1825
		       uint64_t *tiling_flags)
1826
{
1827
	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1828
	int r = amdgpu_bo_reserve(rbo, false);
1829

1830
	if (unlikely(r)) {
1831 1832 1833
		// Don't show error msg. when return -ERESTARTSYS
		if (r != -ERESTARTSYS)
			DRM_ERROR("Unable to reserve buffer: %d\n", r);
1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844
		return r;
	}

	if (tiling_flags)
		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);

	amdgpu_bo_unreserve(rbo);

	return r;
}

1845 1846
static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
					 struct dc_plane_state *plane_state,
1847
					 const struct amdgpu_framebuffer *amdgpu_fb)
1848 1849 1850 1851 1852 1853 1854 1855 1856
{
	uint64_t tiling_flags;
	unsigned int awidth;
	const struct drm_framebuffer *fb = &amdgpu_fb->base;
	int ret = 0;
	struct drm_format_name_buf format_name;

	ret = get_fb_info(
		amdgpu_fb,
1857
		&tiling_flags);
1858 1859 1860 1861 1862 1863

	if (ret)
		return ret;

	switch (fb->format->format) {
	case DRM_FORMAT_C8:
1864
		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
1865 1866
		break;
	case DRM_FORMAT_RGB565:
1867
		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
1868 1869 1870
		break;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
1871
		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
1872 1873 1874
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
1875
		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
1876 1877 1878
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
1879
		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
1880 1881
		break;
	case DRM_FORMAT_NV21:
1882
		plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
1883 1884
		break;
	case DRM_FORMAT_NV12:
1885
		plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
1886 1887 1888
		break;
	default:
		DRM_ERROR("Unsupported screen format %s\n",
1889
			  drm_get_format_name(fb->format->format, &format_name));
1890 1891 1892
		return -EINVAL;
	}

1893 1894 1895 1896 1897 1898 1899
	if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
		plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
		plane_state->plane_size.grph.surface_size.x = 0;
		plane_state->plane_size.grph.surface_size.y = 0;
		plane_state->plane_size.grph.surface_size.width = fb->width;
		plane_state->plane_size.grph.surface_size.height = fb->height;
		plane_state->plane_size.grph.surface_pitch =
1900 1901
				fb->pitches[0] / fb->format->cpp[0];
		/* TODO: unhardcode */
1902
		plane_state->color_space = COLOR_SPACE_SRGB;
1903 1904 1905

	} else {
		awidth = ALIGN(fb->width, 64);
1906 1907 1908 1909 1910
		plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
		plane_state->plane_size.video.luma_size.x = 0;
		plane_state->plane_size.video.luma_size.y = 0;
		plane_state->plane_size.video.luma_size.width = awidth;
		plane_state->plane_size.video.luma_size.height = fb->height;
1911
		/* TODO: unhardcode */
1912
		plane_state->plane_size.video.luma_pitch = awidth;
1913

1914 1915 1916 1917 1918
		plane_state->plane_size.video.chroma_size.x = 0;
		plane_state->plane_size.video.chroma_size.y = 0;
		plane_state->plane_size.video.chroma_size.width = awidth;
		plane_state->plane_size.video.chroma_size.height = fb->height;
		plane_state->plane_size.video.chroma_pitch = awidth / 2;
1919 1920

		/* TODO: unhardcode */
1921
		plane_state->color_space = COLOR_SPACE_YCBCR709;
1922 1923
	}

1924
	memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
1925

1926 1927 1928
	/* Fill GFX8 params */
	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
		unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
1929 1930 1931 1932 1933 1934 1935 1936

		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

		/* XXX fix me for VI */
1937 1938
		plane_state->tiling_info.gfx8.num_banks = num_banks;
		plane_state->tiling_info.gfx8.array_mode =
1939
				DC_ARRAY_2D_TILED_THIN1;
1940 1941 1942 1943 1944
		plane_state->tiling_info.gfx8.tile_split = tile_split;
		plane_state->tiling_info.gfx8.bank_width = bankw;
		plane_state->tiling_info.gfx8.bank_height = bankh;
		plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
		plane_state->tiling_info.gfx8.tile_mode =
1945 1946 1947
				DC_ADDR_SURF_MICRO_TILING_DISPLAY;
	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
			== DC_ARRAY_1D_TILED_THIN1) {
1948
		plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
1949 1950
	}

1951
	plane_state->tiling_info.gfx8.pipe_config =
1952 1953 1954
			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

	if (adev->asic_type == CHIP_VEGA10 ||
1955
	    adev->asic_type == CHIP_VEGA12 ||
1956
	    adev->asic_type == CHIP_VEGA20 ||
1957 1958
	    adev->asic_type == CHIP_RAVEN) {
		/* Fill GFX9 params */
1959
		plane_state->tiling_info.gfx9.num_pipes =
1960
			adev->gfx.config.gb_addr_config_fields.num_pipes;
1961
		plane_state->tiling_info.gfx9.num_banks =
1962
			adev->gfx.config.gb_addr_config_fields.num_banks;
1963
		plane_state->tiling_info.gfx9.pipe_interleave =
1964
			adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
1965
		plane_state->tiling_info.gfx9.num_shader_engines =
1966
			adev->gfx.config.gb_addr_config_fields.num_se;
1967
		plane_state->tiling_info.gfx9.max_compressed_frags =
1968
			adev->gfx.config.gb_addr_config_fields.max_compress_frags;
1969
		plane_state->tiling_info.gfx9.num_rb_per_se =
1970
			adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
1971
		plane_state->tiling_info.gfx9.swizzle =
1972
			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1973
		plane_state->tiling_info.gfx9.shaderEnable = 1;
1974 1975
	}

1976 1977 1978
	plane_state->visible = true;
	plane_state->scaling_quality.h_taps_c = 0;
	plane_state->scaling_quality.v_taps_c = 0;
1979

1980 1981 1982 1983
	/* is this needed? is plane_state zeroed at allocation? */
	plane_state->scaling_quality.h_taps = 0;
	plane_state->scaling_quality.v_taps = 0;
	plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
1984 1985 1986 1987 1988

	return ret;

}

1989 1990 1991
static int fill_plane_attributes(struct amdgpu_device *adev,
				 struct dc_plane_state *dc_plane_state,
				 struct drm_plane_state *plane_state,
1992
				 struct drm_crtc_state *crtc_state)
1993 1994 1995 1996 1997 1998
{
	const struct amdgpu_framebuffer *amdgpu_fb =
		to_amdgpu_framebuffer(plane_state->fb);
	const struct drm_crtc *crtc = plane_state->crtc;
	int ret = 0;

1999
	if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2000 2001 2002 2003
		return -EINVAL;

	ret = fill_plane_attributes_from_fb(
		crtc->dev->dev_private,
2004
		dc_plane_state,
2005
		amdgpu_fb);
2006 2007 2008 2009

	if (ret)
		return ret;

2010 2011 2012 2013 2014
	/*
	 * Always set input transfer function, since plane state is refreshed
	 * every time.
	 */
	ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2015 2016 2017 2018
	if (ret) {
		dc_transfer_func_release(dc_plane_state->in_transfer_func);
		dc_plane_state->in_transfer_func = NULL;
	}
2019 2020 2021 2022 2023 2024

	return ret;
}

/*****************************************************************************/

2025 2026 2027
static void update_stream_scaling_settings(const struct drm_display_mode *mode,
					   const struct dm_connector_state *dm_state,
					   struct dc_stream_state *stream)
2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043
{
	enum amdgpu_rmx_type rmx_type;

	struct rect src = { 0 }; /* viewport in composition space*/
	struct rect dst = { 0 }; /* stream addressable area */

	/* no mode. nothing to be done */
	if (!mode)
		return;

	/* Full screen scaling by default */
	src.width = mode->hdisplay;
	src.height = mode->vdisplay;
	dst.width = stream->timing.h_addressable;
	dst.height = stream->timing.v_addressable;

2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058
	if (dm_state) {
		rmx_type = dm_state->scaling;
		if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
			if (src.width * dst.height <
					src.height * dst.width) {
				/* height needs less upscaling/more downscaling */
				dst.width = src.width *
						dst.height / src.height;
			} else {
				/* width needs less upscaling/more downscaling */
				dst.height = src.height *
						dst.width / src.width;
			}
		} else if (rmx_type == RMX_CENTER) {
			dst = src;
2059 2060
		}

2061 2062
		dst.x = (stream->timing.h_addressable - dst.width) / 2;
		dst.y = (stream->timing.v_addressable - dst.height) / 2;
2063

2064 2065 2066 2067 2068 2069
		if (dm_state->underscan_enable) {
			dst.x += dm_state->underscan_hborder / 2;
			dst.y += dm_state->underscan_vborder / 2;
			dst.width -= dm_state->underscan_hborder;
			dst.height -= dm_state->underscan_vborder;
		}
2070 2071 2072 2073 2074
	}

	stream->src = src;
	stream->dst = dst;

2075
	DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2076 2077 2078 2079
			dst.x, dst.y, dst.width, dst.height);

}

2080 2081
static enum dc_color_depth
convert_color_depth_from_display_info(const struct drm_connector *connector)
2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108
{
	uint32_t bpc = connector->display_info.bpc;

	switch (bpc) {
	case 0:
		/* Temporary Work around, DRM don't parse color depth for
		 * EDID revision before 1.4
		 * TODO: Fix edid parsing
		 */
		return COLOR_DEPTH_888;
	case 6:
		return COLOR_DEPTH_666;
	case 8:
		return COLOR_DEPTH_888;
	case 10:
		return COLOR_DEPTH_101010;
	case 12:
		return COLOR_DEPTH_121212;
	case 14:
		return COLOR_DEPTH_141414;
	case 16:
		return COLOR_DEPTH_161616;
	default:
		return COLOR_DEPTH_UNDEFINED;
	}
}

2109 2110
static enum dc_aspect_ratio
get_aspect_ratio(const struct drm_display_mode *mode_in)
2111
{
2112 2113
	/* 1-1 mapping, since both enums follow the HDMI spec. */
	return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
2114 2115
}

2116 2117
static enum dc_color_space
get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158
{
	enum dc_color_space color_space = COLOR_SPACE_SRGB;

	switch (dc_crtc_timing->pixel_encoding)	{
	case PIXEL_ENCODING_YCBCR422:
	case PIXEL_ENCODING_YCBCR444:
	case PIXEL_ENCODING_YCBCR420:
	{
		/*
		 * 27030khz is the separation point between HDTV and SDTV
		 * according to HDMI spec, we use YCbCr709 and YCbCr601
		 * respectively
		 */
		if (dc_crtc_timing->pix_clk_khz > 27030) {
			if (dc_crtc_timing->flags.Y_ONLY)
				color_space =
					COLOR_SPACE_YCBCR709_LIMITED;
			else
				color_space = COLOR_SPACE_YCBCR709;
		} else {
			if (dc_crtc_timing->flags.Y_ONLY)
				color_space =
					COLOR_SPACE_YCBCR601_LIMITED;
			else
				color_space = COLOR_SPACE_YCBCR601;
		}

	}
	break;
	case PIXEL_ENCODING_RGB:
		color_space = COLOR_SPACE_SRGB;
		break;

	default:
		WARN_ON(1);
		break;
	}

	return color_space;
}

2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198
static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
{
	if (timing_out->display_color_depth <= COLOR_DEPTH_888)
		return;

	timing_out->display_color_depth--;
}

static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
						const struct drm_display_info *info)
{
	int normalized_clk;
	if (timing_out->display_color_depth <= COLOR_DEPTH_888)
		return;
	do {
		normalized_clk = timing_out->pix_clk_khz;
		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
			normalized_clk /= 2;
		/* Adjusting pix clock following on HDMI spec based on colour depth */
		switch (timing_out->display_color_depth) {
		case COLOR_DEPTH_101010:
			normalized_clk = (normalized_clk * 30) / 24;
			break;
		case COLOR_DEPTH_121212:
			normalized_clk = (normalized_clk * 36) / 24;
			break;
		case COLOR_DEPTH_161616:
			normalized_clk = (normalized_clk * 48) / 24;
			break;
		default:
			return;
		}
		if (normalized_clk <= info->max_tmds_clock)
			return;
		reduce_mode_colour_depth(timing_out);

	} while (timing_out->display_color_depth > COLOR_DEPTH_888);

}
2199 2200
/*****************************************************************************/

2201 2202 2203 2204
static void
fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
					     const struct drm_display_mode *mode_in,
					     const struct drm_connector *connector)
2205 2206
{
	struct dc_crtc_timing *timing_out = &stream->timing;
2207
	const struct drm_display_info *info = &connector->display_info;
2208

2209 2210 2211 2212 2213 2214 2215
	memset(timing_out, 0, sizeof(struct dc_crtc_timing));

	timing_out->h_border_left = 0;
	timing_out->h_border_right = 0;
	timing_out->v_border_top = 0;
	timing_out->v_border_bottom = 0;
	/* TODO: un-hardcode */
2216 2217 2218 2219
	if (drm_mode_is_420_only(info, mode_in)
			&& stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
	else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252
			&& stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
	else
		timing_out->pixel_encoding = PIXEL_ENCODING_RGB;

	timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
	timing_out->display_color_depth = convert_color_depth_from_display_info(
			connector);
	timing_out->scan_type = SCANNING_TYPE_NODATA;
	timing_out->hdmi_vic = 0;
	timing_out->vic = drm_match_cea_mode(mode_in);

	timing_out->h_addressable = mode_in->crtc_hdisplay;
	timing_out->h_total = mode_in->crtc_htotal;
	timing_out->h_sync_width =
		mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
	timing_out->h_front_porch =
		mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
	timing_out->v_total = mode_in->crtc_vtotal;
	timing_out->v_addressable = mode_in->crtc_vdisplay;
	timing_out->v_front_porch =
		mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
	timing_out->v_sync_width =
		mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
	timing_out->pix_clk_khz = mode_in->crtc_clock;
	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
	if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
		timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
	if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
		timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;

	stream->output_color_space = get_output_color_space(timing_out);

2253 2254
	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2255 2256
	if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
		adjust_colour_depth_from_display_info(timing_out, info);
2257 2258
}

2259 2260 2261
static void fill_audio_info(struct audio_info *audio_info,
			    const struct drm_connector *drm_connector,
			    const struct dc_sink *dc_sink)
2262 2263 2264 2265 2266 2267 2268 2269 2270 2271
{
	int i = 0;
	int cea_revision = 0;
	const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;

	audio_info->manufacture_id = edid_caps->manufacturer_id;
	audio_info->product_id = edid_caps->product_id;

	cea_revision = drm_connector->display_info.cea_rev;

2272 2273 2274
	strncpy(audio_info->display_name,
		edid_caps->display_name,
		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
2275

2276
	if (cea_revision >= 3) {
2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294
		audio_info->mode_count = edid_caps->audio_mode_count;

		for (i = 0; i < audio_info->mode_count; ++i) {
			audio_info->modes[i].format_code =
					(enum audio_format_code)
					(edid_caps->audio_modes[i].format_code);
			audio_info->modes[i].channel_count =
					edid_caps->audio_modes[i].channel_count;
			audio_info->modes[i].sample_rates.all =
					edid_caps->audio_modes[i].sample_rate;
			audio_info->modes[i].sample_size =
					edid_caps->audio_modes[i].sample_size;
		}
	}

	audio_info->flags.all = edid_caps->speaker_flags;

	/* TODO: We only check for the progressive mode, check for interlace mode too */
2295
	if (drm_connector->latency_present[0]) {
2296 2297 2298 2299 2300 2301 2302 2303
		audio_info->video_latency = drm_connector->video_latency[0];
		audio_info->audio_latency = drm_connector->audio_latency[0];
	}

	/* TODO: For DP, video and audio latency should be calculated from DPCD caps */

}

2304 2305 2306
static void
copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
				      struct drm_display_mode *dst_mode)
2307 2308 2309 2310 2311 2312
{
	dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
	dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
	dst_mode->crtc_clock = src_mode->crtc_clock;
	dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
	dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2313
	dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2314 2315 2316 2317 2318 2319 2320 2321 2322 2323
	dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
	dst_mode->crtc_htotal = src_mode->crtc_htotal;
	dst_mode->crtc_hskew = src_mode->crtc_hskew;
	dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
	dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
	dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
	dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
	dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
}

2324 2325 2326 2327
static void
decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
					const struct drm_display_mode *native_mode,
					bool scale_enabled)
2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339
{
	if (scale_enabled) {
		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
	} else if (native_mode->clock == drm_mode->clock &&
			native_mode->htotal == drm_mode->htotal &&
			native_mode->vtotal == drm_mode->vtotal) {
		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
	} else {
		/* no scaling nor amdgpu inserted, no need to patch */
	}
}

2340 2341
static struct dc_sink *
create_fake_sink(struct amdgpu_dm_connector *aconnector)
2342 2343
{
	struct dc_sink_init_data sink_init_data = { 0 };
2344
	struct dc_sink *sink = NULL;
2345 2346 2347 2348
	sink_init_data.link = aconnector->dc_link;
	sink_init_data.sink_signal = aconnector->dc_link->connector_signal;

	sink = dc_sink_create(&sink_init_data);
2349
	if (!sink) {
2350
		DRM_ERROR("Failed to create sink!\n");
2351
		return NULL;
2352
	}
2353
	sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2354

2355
	return sink;
2356 2357
}

2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384
static void set_multisync_trigger_params(
		struct dc_stream_state *stream)
{
	if (stream->triggered_crtc_reset.enabled) {
		stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
		stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
	}
}

static void set_master_stream(struct dc_stream_state *stream_set[],
			      int stream_count)
{
	int j, highest_rfr = 0, master_stream = 0;

	for (j = 0;  j < stream_count; j++) {
		if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
			int refresh_rate = 0;

			refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
				(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
			if (refresh_rate > highest_rfr) {
				highest_rfr = refresh_rate;
				master_stream = j;
			}
		}
	}
	for (j = 0;  j < stream_count; j++) {
2385
		if (stream_set[j])
2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407
			stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
	}
}

static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
{
	int i = 0;

	if (context->stream_count < 2)
		return;
	for (i = 0; i < context->stream_count ; i++) {
		if (!context->streams[i])
			continue;
		/* TODO: add a function to read AMD VSDB bits and will set
		 * crtc_sync_master.multi_sync_enabled flag
		 * For now its set to false
		 */
		set_multisync_trigger_params(context->streams[i]);
	}
	set_master_stream(context->streams, context->stream_count);
}

2408 2409 2410 2411
static struct dc_stream_state *
create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
		       const struct drm_display_mode *drm_mode,
		       const struct dm_connector_state *dm_state)
2412 2413
{
	struct drm_display_mode *preferred_mode = NULL;
2414
	struct drm_connector *drm_connector;
2415
	struct dc_stream_state *stream = NULL;
2416 2417
	struct drm_display_mode mode = *drm_mode;
	bool native_mode_found = false;
2418
	struct dc_sink *sink = NULL;
2419
	if (aconnector == NULL) {
2420
		DRM_ERROR("aconnector is NULL!\n");
2421
		return stream;
2422 2423 2424
	}

	drm_connector = &aconnector->base;
2425

2426 2427
	if (!aconnector->dc_sink) {
		/*
2428 2429
		 * Create dc_sink when necessary to MST
		 * Don't apply fake_sink to MST
2430
		 */
2431 2432
		if (aconnector->mst_port) {
			dm_dp_mst_dc_sink_create(drm_connector);
2433
			return stream;
2434
		}
2435

2436 2437
		sink = create_fake_sink(aconnector);
		if (!sink)
2438
			return stream;
2439 2440
	} else {
		sink = aconnector->dc_sink;
2441
	}
2442

2443
	stream = dc_create_stream_for_sink(sink);
2444

2445
	if (stream == NULL) {
2446
		DRM_ERROR("Failed to create stream for sink!\n");
2447
		goto finish;
2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462
	}

	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
		/* Search for preferred mode */
		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
			native_mode_found = true;
			break;
		}
	}
	if (!native_mode_found)
		preferred_mode = list_first_entry_or_null(
				&aconnector->base.modes,
				struct drm_display_mode,
				head);

2463
	if (preferred_mode == NULL) {
2464 2465 2466 2467 2468
		/* This may not be an error, the use case is when we we have no
		 * usermode calls to reset and set mode upon hotplug. In this
		 * case, we call set mode ourselves to restore the previous mode
		 * and the modelist may not be filled in in time.
		 */
2469
		DRM_DEBUG_DRIVER("No preferred mode found\n");
2470 2471 2472
	} else {
		decide_crtc_timing_for_drm_display_mode(
				&mode, preferred_mode,
2473
				dm_state ? (dm_state->scaling != RMX_OFF) : false);
2474 2475
	}

2476 2477 2478
	if (!dm_state)
		drm_mode_set_crtcinfo(&mode, 0);

2479 2480 2481 2482 2483 2484 2485
	fill_stream_properties_from_drm_display_mode(stream,
			&mode, &aconnector->base);
	update_stream_scaling_settings(&mode, dm_state, stream);

	fill_audio_info(
		&stream->audio_info,
		drm_connector,
2486
		sink);
2487

2488 2489
	update_stream_signal(stream);

2490 2491
	if (dm_state && dm_state->freesync_capable)
		stream->ignore_msa_timing_param = true;
2492 2493 2494
finish:
	if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
		dc_sink_release(sink);
2495

2496 2497 2498
	return stream;
}

2499
static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2500 2501 2502 2503 2504 2505
{
	drm_crtc_cleanup(crtc);
	kfree(crtc);
}

static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2506
				  struct drm_crtc_state *state)
2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546
{
	struct dm_crtc_state *cur = to_dm_crtc_state(state);

	/* TODO Destroy dc_stream objects are stream object is flattened */
	if (cur->stream)
		dc_stream_release(cur->stream);


	__drm_atomic_helper_crtc_destroy_state(state);


	kfree(state);
}

static void dm_crtc_reset_state(struct drm_crtc *crtc)
{
	struct dm_crtc_state *state;

	if (crtc->state)
		dm_crtc_destroy_state(crtc, crtc->state);

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (WARN_ON(!state))
		return;

	crtc->state = &state->base;
	crtc->state->crtc = crtc;

}

static struct drm_crtc_state *
dm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct dm_crtc_state *state, *cur;

	cur = to_dm_crtc_state(crtc->state);

	if (WARN_ON(!crtc->state))
		return NULL;

2547
	state = kzalloc(sizeof(*state), GFP_KERNEL);
2548 2549
	if (!state)
		return NULL;
2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	if (cur->stream) {
		state->stream = cur->stream;
		dc_stream_retain(state->stream);
	}

	/* TODO Duplicate dc_stream after objects are stream object is flattened */

	return &state->base;
}

2563 2564 2565 2566 2567 2568 2569 2570

static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
{
	enum dc_irq_source irq_source;
	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
	struct amdgpu_device *adev = crtc->dev->dev_private;

	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2571
	return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583
}

static int dm_enable_vblank(struct drm_crtc *crtc)
{
	return dm_set_vblank(crtc, true);
}

static void dm_disable_vblank(struct drm_crtc *crtc)
{
	dm_set_vblank(crtc, false);
}

2584 2585 2586 2587 2588 2589 2590 2591 2592
/* Implemented only the options currently availible for the driver */
static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
	.reset = dm_crtc_reset_state,
	.destroy = amdgpu_dm_crtc_destroy,
	.gamma_set = drm_atomic_helper_legacy_gamma_set,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.atomic_duplicate_state = dm_crtc_duplicate_state,
	.atomic_destroy_state = dm_crtc_destroy_state,
2593
	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
2594 2595
	.enable_vblank = dm_enable_vblank,
	.disable_vblank = dm_disable_vblank,
2596 2597 2598 2599 2600 2601
};

static enum drm_connector_status
amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
{
	bool connected;
2602
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2603 2604 2605 2606 2607 2608

	/* Notes:
	 * 1. This interface is NOT called in context of HPD irq.
	 * 2. This interface *is called* in context of user-mode ioctl. Which
	 * makes it a bad place for *any* MST-related activit. */

2609 2610
	if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
	    !aconnector->fake_enable)
2611 2612 2613 2614 2615 2616 2617 2618
		connected = (aconnector->dc_sink != NULL);
	else
		connected = (aconnector->base.force == DRM_FORCE_ON);

	return (connected ? connector_status_connected :
			connector_status_disconnected);
}

2619 2620 2621 2622
int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
					    struct drm_connector_state *connector_state,
					    struct drm_property *property,
					    uint64_t val)
2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670
{
	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct dm_connector_state *dm_old_state =
		to_dm_connector_state(connector->state);
	struct dm_connector_state *dm_new_state =
		to_dm_connector_state(connector_state);

	int ret = -EINVAL;

	if (property == dev->mode_config.scaling_mode_property) {
		enum amdgpu_rmx_type rmx_type;

		switch (val) {
		case DRM_MODE_SCALE_CENTER:
			rmx_type = RMX_CENTER;
			break;
		case DRM_MODE_SCALE_ASPECT:
			rmx_type = RMX_ASPECT;
			break;
		case DRM_MODE_SCALE_FULLSCREEN:
			rmx_type = RMX_FULL;
			break;
		case DRM_MODE_SCALE_NONE:
		default:
			rmx_type = RMX_OFF;
			break;
		}

		if (dm_old_state->scaling == rmx_type)
			return 0;

		dm_new_state->scaling = rmx_type;
		ret = 0;
	} else if (property == adev->mode_info.underscan_hborder_property) {
		dm_new_state->underscan_hborder = val;
		ret = 0;
	} else if (property == adev->mode_info.underscan_vborder_property) {
		dm_new_state->underscan_vborder = val;
		ret = 0;
	} else if (property == adev->mode_info.underscan_property) {
		dm_new_state->underscan_enable = val;
		ret = 0;
	}

	return ret;
}

2671 2672 2673 2674
int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
					    const struct drm_connector_state *state,
					    struct drm_property *property,
					    uint64_t *val)
2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711
{
	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct dm_connector_state *dm_state =
		to_dm_connector_state(state);
	int ret = -EINVAL;

	if (property == dev->mode_config.scaling_mode_property) {
		switch (dm_state->scaling) {
		case RMX_CENTER:
			*val = DRM_MODE_SCALE_CENTER;
			break;
		case RMX_ASPECT:
			*val = DRM_MODE_SCALE_ASPECT;
			break;
		case RMX_FULL:
			*val = DRM_MODE_SCALE_FULLSCREEN;
			break;
		case RMX_OFF:
		default:
			*val = DRM_MODE_SCALE_NONE;
			break;
		}
		ret = 0;
	} else if (property == adev->mode_info.underscan_hborder_property) {
		*val = dm_state->underscan_hborder;
		ret = 0;
	} else if (property == adev->mode_info.underscan_vborder_property) {
		*val = dm_state->underscan_vborder;
		ret = 0;
	} else if (property == adev->mode_info.underscan_property) {
		*val = dm_state->underscan_enable;
		ret = 0;
	}
	return ret;
}

2712
static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2713
{
2714
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2715 2716 2717
	const struct dc_link *link = aconnector->dc_link;
	struct amdgpu_device *adev = connector->dev->dev_private;
	struct amdgpu_display_manager *dm = &adev->dm;
2718

2719 2720 2721
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

2722
	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2723 2724 2725 2726
	    link->type != dc_connection_none &&
	    dm->backlight_dev) {
		backlight_device_unregister(dm->backlight_dev);
		dm->backlight_dev = NULL;
2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738
	}
#endif
	drm_connector_unregister(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
{
	struct dm_connector_state *state =
		to_dm_connector_state(connector->state);

2739 2740 2741
	if (connector->state)
		__drm_atomic_helper_connector_destroy_state(connector->state);

2742 2743 2744 2745 2746 2747 2748 2749 2750 2751
	kfree(state);

	state = kzalloc(sizeof(*state), GFP_KERNEL);

	if (state) {
		state->scaling = RMX_OFF;
		state->underscan_enable = false;
		state->underscan_hborder = 0;
		state->underscan_vborder = 0;

2752
		__drm_atomic_helper_connector_reset(connector, &state->base);
2753 2754 2755
	}
}

2756 2757
struct drm_connector_state *
amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
2758 2759 2760 2761 2762 2763 2764 2765 2766
{
	struct dm_connector_state *state =
		to_dm_connector_state(connector->state);

	struct dm_connector_state *new_state =
			kmemdup(state, sizeof(*state), GFP_KERNEL);

	if (new_state) {
		__drm_atomic_helper_connector_duplicate_state(connector,
2767
							      &new_state->base);
2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
		return &new_state->base;
	}

	return NULL;
}

static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
	.reset = amdgpu_dm_connector_funcs_reset,
	.detect = amdgpu_dm_connector_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = amdgpu_dm_connector_destroy,
	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
	.atomic_get_property = amdgpu_dm_connector_atomic_get_property
};

static struct drm_encoder *best_encoder(struct drm_connector *connector)
{
	int enc_id = connector->encoder_ids[0];
	struct drm_mode_object *obj;
	struct drm_encoder *encoder;

2791
	DRM_DEBUG_DRIVER("Finding the best encoder\n");
2792 2793 2794

	/* pick the encoder ids */
	if (enc_id) {
2795
		obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811
		if (!obj) {
			DRM_ERROR("Couldn't find a matching encoder for our connector\n");
			return NULL;
		}
		encoder = obj_to_encoder(obj);
		return encoder;
	}
	DRM_ERROR("No encoder id\n");
	return NULL;
}

static int get_modes(struct drm_connector *connector)
{
	return amdgpu_dm_connector_get_modes(connector);
}

2812
static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
2813 2814 2815 2816 2817
{
	struct dc_sink_init_data init_params = {
			.link = aconnector->dc_link,
			.sink_signal = SIGNAL_TYPE_VIRTUAL
	};
2818
	struct edid *edid;
2819

2820
	if (!aconnector->base.edid_blob_ptr) {
2821 2822 2823 2824 2825 2826 2827 2828
		DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
				aconnector->base.name);

		aconnector->base.force = DRM_FORCE_OFF;
		aconnector->base.override_edid = false;
		return;
	}

2829 2830
	edid = (struct edid *) aconnector->base.edid_blob_ptr->data;

2831 2832 2833 2834 2835 2836 2837 2838
	aconnector->edid = edid;

	aconnector->dc_em_sink = dc_link_add_remote_sink(
		aconnector->dc_link,
		(uint8_t *)edid,
		(edid->extensions + 1) * EDID_LENGTH,
		&init_params);

2839
	if (aconnector->base.force == DRM_FORCE_ON)
2840 2841 2842 2843 2844
		aconnector->dc_sink = aconnector->dc_link->local_sink ?
		aconnector->dc_link->local_sink :
		aconnector->dc_em_sink;
}

2845
static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861
{
	struct dc_link *link = (struct dc_link *)aconnector->dc_link;

	/* In case of headless boot with force on for DP managed connector
	 * Those settings have to be != 0 to get initial modeset
	 */
	if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
		link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
		link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
	}


	aconnector->base.override_edid = true;
	create_eml_sink(aconnector);
}

2862
enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2863
				   struct drm_display_mode *mode)
2864 2865 2866 2867 2868
{
	int result = MODE_ERROR;
	struct dc_sink *dc_sink;
	struct amdgpu_device *adev = connector->dev->dev_private;
	/* TODO: Unhardcode stream count */
2869
	struct dc_stream_state *stream;
2870
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2871
	enum dc_status dc_result = DC_OK;
2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883

	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
		return result;

	/* Only run this the first time mode_valid is called to initilialize
	 * EDID mgmt
	 */
	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
		!aconnector->dc_em_sink)
		handle_edid_mgmt(aconnector);

2884
	dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
2885

2886
	if (dc_sink == NULL) {
2887 2888 2889 2890
		DRM_ERROR("dc_sink is NULL!\n");
		goto fail;
	}

2891
	stream = create_stream_for_sink(aconnector, mode, NULL);
2892
	if (stream == NULL) {
2893 2894 2895 2896
		DRM_ERROR("Failed to create stream for sink!\n");
		goto fail;
	}

2897 2898 2899
	dc_result = dc_validate_stream(adev->dm.dc, stream);

	if (dc_result == DC_OK)
2900
		result = MODE_OK;
2901
	else
2902
		DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
2903 2904
			      mode->vdisplay,
			      mode->hdisplay,
2905 2906
			      mode->clock,
			      dc_result);
2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917

	dc_stream_release(stream);

fail:
	/* TODO: error handling*/
	return result;
}

static const struct drm_connector_helper_funcs
amdgpu_dm_connector_helper_funcs = {
	/*
2918 2919 2920 2921 2922
	 * If hotplug a second bigger display in FB Con mode, bigger resolution
	 * modes will be filtered by drm_mode_validate_size(), and those modes
	 * is missing after user start lightdm. So we need to renew modes list.
	 * in get_modes call back, not just return the modes count
	 */
2923 2924 2925 2926 2927 2928 2929 2930 2931
	.get_modes = get_modes,
	.mode_valid = amdgpu_dm_connector_mode_valid,
	.best_encoder = best_encoder
};

static void dm_crtc_helper_disable(struct drm_crtc *crtc)
{
}

2932 2933
static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
2934 2935 2936 2937 2938 2939
{
	struct amdgpu_device *adev = crtc->dev->dev_private;
	struct dc *dc = adev->dm.dc;
	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
	int ret = -EINVAL;

2940 2941
	if (unlikely(!dm_crtc_state->stream &&
		     modeset_required(state, NULL, dm_crtc_state->stream))) {
2942 2943 2944 2945 2946 2947 2948 2949
		WARN_ON(1);
		return ret;
	}

	/* In some use cases, like reset, no stream  is attached */
	if (!dm_crtc_state->stream)
		return 0;

2950
	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
2951 2952 2953 2954 2955
		return 0;

	return ret;
}

2956 2957 2958
static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
				      const struct drm_display_mode *mode,
				      struct drm_display_mode *adjusted_mode)
2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973
{
	return true;
}

static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
	.disable = dm_crtc_helper_disable,
	.atomic_check = dm_crtc_helper_atomic_check,
	.mode_fixup = dm_crtc_helper_mode_fixup
};

static void dm_encoder_helper_disable(struct drm_encoder *encoder)
{

}

2974 2975 2976
static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
					  struct drm_crtc_state *crtc_state,
					  struct drm_connector_state *conn_state)
2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993
{
	return 0;
}

const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
	.disable = dm_encoder_helper_disable,
	.atomic_check = dm_encoder_helper_atomic_check
};

static void dm_drm_plane_reset(struct drm_plane *plane)
{
	struct dm_plane_state *amdgpu_state = NULL;

	if (plane->state)
		plane->funcs->atomic_destroy_state(plane, plane->state);

	amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2994 2995
	WARN_ON(amdgpu_state == NULL);
	
2996 2997 2998 2999
	if (amdgpu_state) {
		plane->state = &amdgpu_state->base;
		plane->state->plane = plane;
		plane->state->rotation = DRM_MODE_ROTATE_0;
3000
	}
3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014
}

static struct drm_plane_state *
dm_drm_plane_duplicate_state(struct drm_plane *plane)
{
	struct dm_plane_state *dm_plane_state, *old_dm_plane_state;

	old_dm_plane_state = to_dm_plane_state(plane->state);
	dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
	if (!dm_plane_state)
		return NULL;

	__drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);

3015 3016 3017
	if (old_dm_plane_state->dc_state) {
		dm_plane_state->dc_state = old_dm_plane_state->dc_state;
		dc_plane_state_retain(dm_plane_state->dc_state);
3018 3019 3020 3021 3022 3023
	}

	return &dm_plane_state->base;
}

void dm_drm_plane_destroy_state(struct drm_plane *plane,
3024
				struct drm_plane_state *state)
3025 3026 3027
{
	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);

3028 3029
	if (dm_plane_state->dc_state)
		dc_plane_state_release(dm_plane_state->dc_state);
3030

3031
	drm_atomic_helper_plane_destroy_state(plane, state);
3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042
}

static const struct drm_plane_funcs dm_plane_funcs = {
	.update_plane	= drm_atomic_helper_update_plane,
	.disable_plane	= drm_atomic_helper_disable_plane,
	.destroy	= drm_plane_cleanup,
	.reset = dm_drm_plane_reset,
	.atomic_duplicate_state = dm_drm_plane_duplicate_state,
	.atomic_destroy_state = dm_drm_plane_destroy_state,
};

3043 3044
static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
				      struct drm_plane_state *new_state)
3045 3046 3047
{
	struct amdgpu_framebuffer *afb;
	struct drm_gem_object *obj;
3048
	struct amdgpu_device *adev;
3049
	struct amdgpu_bo *rbo;
3050
	uint64_t chroma_addr = 0;
3051 3052
	struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
	unsigned int awidth;
3053 3054
	uint32_t domain;
	int r;
3055 3056 3057 3058 3059

	dm_plane_state_old = to_dm_plane_state(plane->state);
	dm_plane_state_new = to_dm_plane_state(new_state);

	if (!new_state->fb) {
3060
		DRM_DEBUG_DRIVER("No FB bound\n");
3061 3062 3063 3064
		return 0;
	}

	afb = to_amdgpu_framebuffer(new_state->fb);
3065
	obj = new_state->fb->obj[0];
3066
	rbo = gem_to_amdgpu_bo(obj);
3067
	adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3068 3069 3070 3071
	r = amdgpu_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		return r;

3072
	if (plane->type != DRM_PLANE_TYPE_CURSOR)
3073
		domain = amdgpu_display_supported_domains(adev);
3074 3075
	else
		domain = AMDGPU_GEM_DOMAIN_VRAM;
3076

3077
	r = amdgpu_bo_pin(rbo, domain);
3078
	if (unlikely(r != 0)) {
3079 3080
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3081
		amdgpu_bo_unreserve(rbo);
3082 3083 3084
		return r;
	}

3085 3086 3087 3088 3089
	r = amdgpu_ttm_alloc_gart(&rbo->tbo);
	if (unlikely(r != 0)) {
		amdgpu_bo_unpin(rbo);
		amdgpu_bo_unreserve(rbo);
		DRM_ERROR("%p bind failed\n", rbo);
3090 3091
		return r;
	}
3092 3093
	amdgpu_bo_unreserve(rbo);

3094
	afb->address = amdgpu_bo_gpu_offset(rbo);
3095 3096 3097

	amdgpu_bo_ref(rbo);

3098 3099 3100
	if (dm_plane_state_new->dc_state &&
			dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3101

3102 3103 3104
		if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
			plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
			plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3105 3106
		} else {
			awidth = ALIGN(new_state->fb->width, 64);
3107
			plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3108
			plane_state->address.video_progressive.luma_addr.low_part
3109
							= lower_32_bits(afb->address);
3110 3111
			plane_state->address.video_progressive.luma_addr.high_part
							= upper_32_bits(afb->address);
3112
			chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3113
			plane_state->address.video_progressive.chroma_addr.low_part
3114 3115 3116
							= lower_32_bits(chroma_addr);
			plane_state->address.video_progressive.chroma_addr.high_part
							= upper_32_bits(chroma_addr);
3117 3118 3119 3120 3121 3122
		}
	}

	return 0;
}

3123 3124
static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
				       struct drm_plane_state *old_state)
3125 3126 3127 3128 3129 3130 3131
{
	struct amdgpu_bo *rbo;
	int r;

	if (!old_state->fb)
		return;

3132
	rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3133 3134 3135 3136
	r = amdgpu_bo_reserve(rbo, false);
	if (unlikely(r)) {
		DRM_ERROR("failed to reserve rbo before unpin\n");
		return;
3137 3138 3139 3140 3141
	}

	amdgpu_bo_unpin(rbo);
	amdgpu_bo_unreserve(rbo);
	amdgpu_bo_unref(&rbo);
3142 3143
}

3144 3145
static int dm_plane_atomic_check(struct drm_plane *plane,
				 struct drm_plane_state *state)
3146 3147 3148 3149 3150
{
	struct amdgpu_device *adev = plane->dev->dev_private;
	struct dc *dc = adev->dm.dc;
	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);

3151
	if (!dm_plane_state->dc_state)
3152
		return 0;
3153

3154 3155 3156
	if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
		return -EINVAL;

3157
	if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3158 3159 3160 3161 3162
		return 0;

	return -EINVAL;
}

3163 3164 3165
static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
	.prepare_fb = dm_plane_helper_prepare_fb,
	.cleanup_fb = dm_plane_helper_cleanup_fb,
3166
	.atomic_check = dm_plane_atomic_check,
3167 3168 3169 3170 3171 3172 3173 3174
};

/*
 * TODO: these are currently initialized to rgb formats only.
 * For future use cases we should either initialize them dynamically based on
 * plane capabilities, or initialize this array to all formats, so internal drm
 * check will succeed, and let DC to implement proper check
 */
D
Dave Airlie 已提交
3175
static const uint32_t rgb_formats[] = {
3176 3177 3178 3179 3180 3181 3182 3183 3184 3185
	DRM_FORMAT_RGB888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_RGBA8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_ARGB2101010,
	DRM_FORMAT_ABGR2101010,
};

D
Dave Airlie 已提交
3186
static const uint32_t yuv_formats[] = {
3187 3188 3189 3190 3191 3192 3193 3194
	DRM_FORMAT_NV12,
	DRM_FORMAT_NV21,
};

static const u32 cursor_formats[] = {
	DRM_FORMAT_ARGB8888
};

3195 3196 3197
static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
				struct amdgpu_plane *aplane,
				unsigned long possible_crtcs)
3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235
{
	int res = -EPERM;

	switch (aplane->base.type) {
	case DRM_PLANE_TYPE_PRIMARY:
		res = drm_universal_plane_init(
				dm->adev->ddev,
				&aplane->base,
				possible_crtcs,
				&dm_plane_funcs,
				rgb_formats,
				ARRAY_SIZE(rgb_formats),
				NULL, aplane->base.type, NULL);
		break;
	case DRM_PLANE_TYPE_OVERLAY:
		res = drm_universal_plane_init(
				dm->adev->ddev,
				&aplane->base,
				possible_crtcs,
				&dm_plane_funcs,
				yuv_formats,
				ARRAY_SIZE(yuv_formats),
				NULL, aplane->base.type, NULL);
		break;
	case DRM_PLANE_TYPE_CURSOR:
		res = drm_universal_plane_init(
				dm->adev->ddev,
				&aplane->base,
				possible_crtcs,
				&dm_plane_funcs,
				cursor_formats,
				ARRAY_SIZE(cursor_formats),
				NULL, aplane->base.type, NULL);
		break;
	}

	drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);

3236 3237 3238 3239 3240
	/* Create (reset) the plane state */
	if (aplane->base.funcs->reset)
		aplane->base.funcs->reset(&aplane->base);


3241 3242 3243
	return res;
}

3244 3245 3246
static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
			       struct drm_plane *plane,
			       uint32_t crtc_index)
3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275
{
	struct amdgpu_crtc *acrtc = NULL;
	struct amdgpu_plane *cursor_plane;

	int res = -ENOMEM;

	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
	if (!cursor_plane)
		goto fail;

	cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
	res = amdgpu_dm_plane_init(dm, cursor_plane, 0);

	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
	if (!acrtc)
		goto fail;

	res = drm_crtc_init_with_planes(
			dm->ddev,
			&acrtc->base,
			plane,
			&cursor_plane->base,
			&amdgpu_dm_crtc_funcs, NULL);

	if (res)
		goto fail;

	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);

3276 3277 3278 3279
	/* Create (reset) the plane state */
	if (acrtc->base.funcs->reset)
		acrtc->base.funcs->reset(&acrtc->base);

3280 3281 3282 3283 3284 3285 3286
	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;

	acrtc->crtc_id = crtc_index;
	acrtc->base.enabled = false;

	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3287 3288
	drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
				   true, MAX_COLOR_LUT_ENTRIES);
3289
	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
3290 3291 3292 3293

	return 0;

fail:
3294 3295
	kfree(acrtc);
	kfree(cursor_plane);
3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340
	return res;
}


static int to_drm_connector_type(enum signal_type st)
{
	switch (st) {
	case SIGNAL_TYPE_HDMI_TYPE_A:
		return DRM_MODE_CONNECTOR_HDMIA;
	case SIGNAL_TYPE_EDP:
		return DRM_MODE_CONNECTOR_eDP;
	case SIGNAL_TYPE_RGB:
		return DRM_MODE_CONNECTOR_VGA;
	case SIGNAL_TYPE_DISPLAY_PORT:
	case SIGNAL_TYPE_DISPLAY_PORT_MST:
		return DRM_MODE_CONNECTOR_DisplayPort;
	case SIGNAL_TYPE_DVI_DUAL_LINK:
	case SIGNAL_TYPE_DVI_SINGLE_LINK:
		return DRM_MODE_CONNECTOR_DVID;
	case SIGNAL_TYPE_VIRTUAL:
		return DRM_MODE_CONNECTOR_VIRTUAL;

	default:
		return DRM_MODE_CONNECTOR_Unknown;
	}
}

static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
{
	const struct drm_connector_helper_funcs *helper =
		connector->helper_private;
	struct drm_encoder *encoder;
	struct amdgpu_encoder *amdgpu_encoder;

	encoder = helper->best_encoder(connector);

	if (encoder == NULL)
		return;

	amdgpu_encoder = to_amdgpu_encoder(encoder);

	amdgpu_encoder->native_mode.clock = 0;

	if (!list_empty(&connector->probed_modes)) {
		struct drm_display_mode *preferred_mode = NULL;
3341

3342
		list_for_each_entry(preferred_mode,
3343 3344 3345 3346 3347
				    &connector->probed_modes,
				    head) {
			if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
				amdgpu_encoder->native_mode = *preferred_mode;

3348 3349 3350 3351 3352 3353
			break;
		}

	}
}

3354 3355 3356 3357
static struct drm_display_mode *
amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
			     char *name,
			     int hdisplay, int vdisplay)
3358 3359 3360 3361 3362 3363 3364 3365
{
	struct drm_device *dev = encoder->dev;
	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
	struct drm_display_mode *mode = NULL;
	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;

	mode = drm_mode_duplicate(dev, native_mode);

3366
	if (mode == NULL)
3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378
		return NULL;

	mode->hdisplay = hdisplay;
	mode->vdisplay = vdisplay;
	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
	strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);

	return mode;

}

static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3379
						 struct drm_connector *connector)
3380 3381 3382 3383
{
	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
	struct drm_display_mode *mode = NULL;
	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3384 3385
	struct amdgpu_dm_connector *amdgpu_dm_connector =
				to_amdgpu_dm_connector(connector);
3386 3387 3388 3389 3390 3391
	int i;
	int n;
	struct mode_size {
		char name[DRM_DISPLAY_MODE_LEN];
		int w;
		int h;
3392
	} common_modes[] = {
3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405
		{  "640x480",  640,  480},
		{  "800x600",  800,  600},
		{ "1024x768", 1024,  768},
		{ "1280x720", 1280,  720},
		{ "1280x800", 1280,  800},
		{"1280x1024", 1280, 1024},
		{ "1440x900", 1440,  900},
		{"1680x1050", 1680, 1050},
		{"1600x1200", 1600, 1200},
		{"1920x1080", 1920, 1080},
		{"1920x1200", 1920, 1200}
	};

3406
	n = ARRAY_SIZE(common_modes);
3407 3408 3409 3410 3411 3412

	for (i = 0; i < n; i++) {
		struct drm_display_mode *curmode = NULL;
		bool mode_existed = false;

		if (common_modes[i].w > native_mode->hdisplay ||
3413 3414 3415 3416
		    common_modes[i].h > native_mode->vdisplay ||
		   (common_modes[i].w == native_mode->hdisplay &&
		    common_modes[i].h == native_mode->vdisplay))
			continue;
3417 3418 3419

		list_for_each_entry(curmode, &connector->probed_modes, head) {
			if (common_modes[i].w == curmode->hdisplay &&
3420
			    common_modes[i].h == curmode->vdisplay) {
3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432
				mode_existed = true;
				break;
			}
		}

		if (mode_existed)
			continue;

		mode = amdgpu_dm_create_common_mode(encoder,
				common_modes[i].name, common_modes[i].w,
				common_modes[i].h);
		drm_mode_probed_add(connector, mode);
3433
		amdgpu_dm_connector->num_modes++;
3434 3435 3436
	}
}

3437 3438
static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
					      struct edid *edid)
3439
{
3440 3441
	struct amdgpu_dm_connector *amdgpu_dm_connector =
			to_amdgpu_dm_connector(connector);
3442 3443 3444 3445

	if (edid) {
		/* empty probed_modes */
		INIT_LIST_HEAD(&connector->probed_modes);
3446
		amdgpu_dm_connector->num_modes =
3447 3448 3449
				drm_add_edid_modes(connector, edid);

		amdgpu_dm_get_native_mode(connector);
3450
	} else {
3451
		amdgpu_dm_connector->num_modes = 0;
3452
	}
3453 3454
}

3455
static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3456 3457 3458
{
	const struct drm_connector_helper_funcs *helper =
			connector->helper_private;
3459 3460
	struct amdgpu_dm_connector *amdgpu_dm_connector =
			to_amdgpu_dm_connector(connector);
3461
	struct drm_encoder *encoder;
3462
	struct edid *edid = amdgpu_dm_connector->edid;
3463 3464

	encoder = helper->best_encoder(connector);
3465

3466 3467 3468 3469 3470 3471
	if (!edid || !drm_edid_is_valid(edid)) {
		drm_add_modes_noedid(connector, 640, 480);
	} else {
		amdgpu_dm_connector_ddc_get_modes(connector, edid);
		amdgpu_dm_connector_add_common_modes(encoder, connector);
	}
3472
	amdgpu_dm_fbc_init(connector);
3473

3474
	return amdgpu_dm_connector->num_modes;
3475 3476
}

3477 3478 3479 3480 3481
void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
				     struct amdgpu_dm_connector *aconnector,
				     int connector_type,
				     struct dc_link *link,
				     int link_index)
3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493
{
	struct amdgpu_device *adev = dm->ddev->dev_private;

	aconnector->connector_id = link_index;
	aconnector->dc_link = link;
	aconnector->base.interlace_allowed = false;
	aconnector->base.doublescan_allowed = false;
	aconnector->base.stereo_allowed = false;
	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
	mutex_init(&aconnector->hpd_lock);

3494 3495 3496
	/* configure support HPD hot plug connector_>polled default value is 0
	 * which means HPD hot plug not supported
	 */
3497 3498 3499
	switch (connector_type) {
	case DRM_MODE_CONNECTOR_HDMIA:
		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3500 3501
		aconnector->base.ycbcr_420_allowed =
			link->link_enc->features.ycbcr420_supported ? true : false;
3502 3503 3504
		break;
	case DRM_MODE_CONNECTOR_DisplayPort:
		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3505 3506
		aconnector->base.ycbcr_420_allowed =
			link->link_enc->features.ycbcr420_supported ? true : false;
3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530
		break;
	case DRM_MODE_CONNECTOR_DVID:
		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
		break;
	default:
		break;
	}

	drm_object_attach_property(&aconnector->base.base,
				dm->ddev->mode_config.scaling_mode_property,
				DRM_MODE_SCALE_NONE);

	drm_object_attach_property(&aconnector->base.base,
				adev->mode_info.underscan_property,
				UNDERSCAN_OFF);
	drm_object_attach_property(&aconnector->base.base,
				adev->mode_info.underscan_hborder_property,
				0);
	drm_object_attach_property(&aconnector->base.base,
				adev->mode_info.underscan_vborder_property,
				0);

}

3531 3532
static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
			      struct i2c_msg *msgs, int num)
3533 3534 3535 3536 3537 3538 3539
{
	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
	struct ddc_service *ddc_service = i2c->ddc_service;
	struct i2c_command cmd;
	int i;
	int result = -EIO;

3540
	cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565

	if (!cmd.payloads)
		return result;

	cmd.number_of_payloads = num;
	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
	cmd.speed = 100;

	for (i = 0; i < num; i++) {
		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
		cmd.payloads[i].address = msgs[i].addr;
		cmd.payloads[i].length = msgs[i].len;
		cmd.payloads[i].data = msgs[i].buf;
	}

	if (dal_i2caux_submit_i2c_command(
			ddc_service->ctx->i2caux,
			ddc_service->ddc_pin,
			&cmd))
		result = num;

	kfree(cmd.payloads);
	return result;
}

3566
static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3567 3568 3569 3570 3571 3572 3573 3574 3575
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
	.master_xfer = amdgpu_dm_i2c_xfer,
	.functionality = amdgpu_dm_i2c_func,
};

3576 3577 3578 3579
static struct amdgpu_i2c_adapter *
create_i2c(struct ddc_service *ddc_service,
	   int link_index,
	   int *res)
3580 3581 3582 3583
{
	struct amdgpu_device *adev = ddc_service->ctx->driver_context;
	struct amdgpu_i2c_adapter *i2c;

3584
	i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
3585 3586
	if (!i2c)
		return NULL;
3587 3588 3589 3590
	i2c->base.owner = THIS_MODULE;
	i2c->base.class = I2C_CLASS_DDC;
	i2c->base.dev.parent = &adev->pdev->dev;
	i2c->base.algo = &amdgpu_dm_i2c_algo;
3591
	snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
3592 3593 3594 3595 3596 3597
	i2c_set_adapdata(&i2c->base, i2c);
	i2c->ddc_service = ddc_service;

	return i2c;
}

3598

3599
/* Note: this function assumes that dc_link_detect() was called for the
3600 3601
 * dc_link which will be represented by this aconnector.
 */
3602 3603 3604 3605
static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
				    struct amdgpu_dm_connector *aconnector,
				    uint32_t link_index,
				    struct amdgpu_encoder *aencoder)
3606 3607 3608 3609 3610 3611
{
	int res = 0;
	int connector_type;
	struct dc *dc = dm->dc;
	struct dc_link *link = dc_get_link_at_index(dc, link_index);
	struct amdgpu_i2c_adapter *i2c;
3612 3613

	link->priv = aconnector;
3614

3615
	DRM_DEBUG_DRIVER("%s()\n", __func__);
3616 3617

	i2c = create_i2c(link->ddc, link->link_index, &res);
3618 3619 3620 3621 3622
	if (!i2c) {
		DRM_ERROR("Failed to create i2c adapter data\n");
		return -ENOMEM;
	}

3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648
	aconnector->i2c = i2c;
	res = i2c_add_adapter(&i2c->base);

	if (res) {
		DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
		goto out_free;
	}

	connector_type = to_drm_connector_type(link->connector_signal);

	res = drm_connector_init(
			dm->ddev,
			&aconnector->base,
			&amdgpu_dm_connector_funcs,
			connector_type);

	if (res) {
		DRM_ERROR("connector_init failed\n");
		aconnector->connector_id = -1;
		goto out_free;
	}

	drm_connector_helper_add(
			&aconnector->base,
			&amdgpu_dm_connector_helper_funcs);

3649 3650 3651
	if (aconnector->base.funcs->reset)
		aconnector->base.funcs->reset(&aconnector->base);

3652 3653 3654 3655 3656 3657 3658
	amdgpu_dm_connector_init_helper(
		dm,
		aconnector,
		connector_type,
		link,
		link_index);

3659
	drm_connector_attach_encoder(
3660 3661 3662
		&aconnector->base, &aencoder->base);

	drm_connector_register(&aconnector->base);
3663 3664 3665 3666 3667 3668 3669
#if defined(CONFIG_DEBUG_FS)
	res = connector_debugfs_init(aconnector);
	if (res) {
		DRM_ERROR("Failed to create debugfs for connector");
		goto out_free;
	}
#endif
3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701

	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
		|| connector_type == DRM_MODE_CONNECTOR_eDP)
		amdgpu_dm_initialize_dp_connector(dm, aconnector);

out_free:
	if (res) {
		kfree(i2c);
		aconnector->i2c = NULL;
	}
	return res;
}

int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
{
	switch (adev->mode_info.num_crtc) {
	case 1:
		return 0x1;
	case 2:
		return 0x3;
	case 3:
		return 0x7;
	case 4:
		return 0xf;
	case 5:
		return 0x1f;
	case 6:
	default:
		return 0x3f;
	}
}

3702 3703 3704
static int amdgpu_dm_encoder_init(struct drm_device *dev,
				  struct amdgpu_encoder *aencoder,
				  uint32_t link_index)
3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725
{
	struct amdgpu_device *adev = dev->dev_private;

	int res = drm_encoder_init(dev,
				   &aencoder->base,
				   &amdgpu_dm_encoder_funcs,
				   DRM_MODE_ENCODER_TMDS,
				   NULL);

	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);

	if (!res)
		aencoder->encoder_id = link_index;
	else
		aencoder->encoder_id = -1;

	drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);

	return res;
}

3726 3727 3728
static void manage_dm_interrupts(struct amdgpu_device *adev,
				 struct amdgpu_crtc *acrtc,
				 bool enable)
3729 3730 3731 3732 3733 3734
{
	/*
	 * this is not correct translation but will work as soon as VBLANK
	 * constant is the same as PFLIP
	 */
	int irq_type =
3735
		amdgpu_display_crtc_idx_to_irq_type(
3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754
			adev,
			acrtc->crtc_id);

	if (enable) {
		drm_crtc_vblank_on(&acrtc->base);
		amdgpu_irq_get(
			adev,
			&adev->pageflip_irq,
			irq_type);
	} else {

		amdgpu_irq_put(
			adev,
			&adev->pageflip_irq,
			irq_type);
		drm_crtc_vblank_off(&acrtc->base);
	}
}

3755 3756 3757
static bool
is_scaling_state_different(const struct dm_connector_state *dm_state,
			   const struct dm_connector_state *old_dm_state)
3758 3759 3760 3761 3762 3763 3764 3765 3766
{
	if (dm_state->scaling != old_dm_state->scaling)
		return true;
	if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
		if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
			return true;
	} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
		if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
			return true;
3767 3768 3769
	} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
		   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
		return true;
3770 3771 3772
	return false;
}

3773 3774 3775
static void remove_stream(struct amdgpu_device *adev,
			  struct amdgpu_crtc *acrtc,
			  struct dc_stream_state *stream)
3776 3777 3778 3779 3780 3781 3782 3783 3784
{
	/* this is the update mode case */
	if (adev->dm.freesync_module)
		mod_freesync_remove_stream(adev->dm.freesync_module, stream);

	acrtc->otg_inst = -1;
	acrtc->enabled = false;
}

3785 3786
static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
			       struct dc_cursor_position *position)
3787
{
3788
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829
	int x, y;
	int xorigin = 0, yorigin = 0;

	if (!crtc || !plane->state->fb) {
		position->enable = false;
		position->x = 0;
		position->y = 0;
		return 0;
	}

	if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
	    (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
		DRM_ERROR("%s: bad cursor width or height %d x %d\n",
			  __func__,
			  plane->state->crtc_w,
			  plane->state->crtc_h);
		return -EINVAL;
	}

	x = plane->state->crtc_x;
	y = plane->state->crtc_y;
	/* avivo cursor are offset into the total surface */
	x += crtc->primary->state->src_x >> 16;
	y += crtc->primary->state->src_y >> 16;
	if (x < 0) {
		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
		x = 0;
	}
	if (y < 0) {
		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
		y = 0;
	}
	position->enable = true;
	position->x = x;
	position->y = y;
	position->x_hotspot = xorigin;
	position->y_hotspot = yorigin;

	return 0;
}

3830 3831
static void handle_cursor_update(struct drm_plane *plane,
				 struct drm_plane_state *old_plane_state)
3832
{
3833 3834 3835 3836 3837 3838 3839 3840 3841
	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
	struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
	struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
	uint64_t address = afb ? afb->address : 0;
	struct dc_cursor_position position;
	struct dc_cursor_attributes attributes;
	int ret;

3842 3843 3844
	if (!plane->state->fb && !old_plane_state->fb)
		return;

3845
	DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
3846 3847 3848 3849
			 __func__,
			 amdgpu_crtc->crtc_id,
			 plane->state->crtc_w,
			 plane->state->crtc_h);
3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860

	ret = get_cursor_position(plane, crtc, &position);
	if (ret)
		return;

	if (!position.enable) {
		/* turn off cursor */
		if (crtc_state && crtc_state->stream)
			dc_stream_set_cursor_position(crtc_state->stream,
						      &position);
		return;
3861 3862
	}

3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875
	amdgpu_crtc->cursor_width = plane->state->crtc_w;
	amdgpu_crtc->cursor_height = plane->state->crtc_h;

	attributes.address.high_part = upper_32_bits(address);
	attributes.address.low_part  = lower_32_bits(address);
	attributes.width             = plane->state->crtc_w;
	attributes.height            = plane->state->crtc_h;
	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
	attributes.rotation_angle    = 0;
	attributes.attribute_flags.value = 0;

	attributes.pitch = attributes.width;

3876 3877 3878 3879
	if (crtc_state->stream) {
		if (!dc_stream_set_cursor_attributes(crtc_state->stream,
							 &attributes))
			DRM_ERROR("DC failed to set cursor attributes\n");
3880 3881 3882 3883

		if (!dc_stream_set_cursor_position(crtc_state->stream,
						   &position))
			DRM_ERROR("DC failed to set cursor position\n");
3884
	}
3885
}
3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909

static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
{

	assert_spin_locked(&acrtc->base.dev->event_lock);
	WARN_ON(acrtc->event);

	acrtc->event = acrtc->base.state->event;

	/* Set the flip status */
	acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;

	/* Mark this event as consumed */
	acrtc->base.state->event = NULL;

	DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
						 acrtc->crtc_id);
}

/*
 * Executes flip
 *
 * Waits on all BO's fences and for proper vblank count
 */
3910 3911
static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
			      struct drm_framebuffer *fb,
3912 3913
			      uint32_t target,
			      struct dc_state *state)
3914 3915 3916 3917 3918 3919
{
	unsigned long flags;
	uint32_t target_vblank;
	int r, vpos, hpos;
	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3920
	struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
3921
	struct amdgpu_device *adev = crtc->dev->dev_private;
3922
	bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3923
	struct dc_flip_addrs addr = { {0} };
3924
	/* TODO eliminate or rename surface_update */
3925 3926 3927 3928 3929
	struct dc_surface_update surface_updates[1] = { {0} };
	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);


	/* Prepare wait for target vblank early - before the fence-waits */
3930
	target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
3931 3932
			amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);

3933
	/* TODO This might fail and hence better not used, wait
3934 3935 3936
	 * explicitly on fences instead
	 * and in general should be called for
	 * blocking commit to as per framework helpers
3937
	 */
3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953
	r = amdgpu_bo_reserve(abo, true);
	if (unlikely(r != 0)) {
		DRM_ERROR("failed to reserve buffer before flip\n");
		WARN_ON(1);
	}

	/* Wait for all fences on this FB */
	WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
								    MAX_SCHEDULE_TIMEOUT) < 0);

	amdgpu_bo_unreserve(abo);

	/* Wait until we're out of the vertical blank period before the one
	 * targeted by the flip
	 */
	while ((acrtc->enabled &&
3954 3955 3956
		(amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
						    0, &vpos, &hpos, NULL,
						    NULL, &crtc->hwmode)
3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977
		 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
		(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
		(int)(target_vblank -
		  amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
		usleep_range(1000, 1100);
	}

	/* Flip */
	spin_lock_irqsave(&crtc->dev->event_lock, flags);

	WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
	WARN_ON(!acrtc_state->stream);

	addr.address.grph.addr.low_part = lower_32_bits(afb->address);
	addr.address.grph.addr.high_part = upper_32_bits(afb->address);
	addr.flip_immediate = async_flip;


	if (acrtc->base.state->event)
		prepare_flip_isr(acrtc);

3978 3979
	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);

3980
	surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
3981 3982
	surface_updates->flip_addr = &addr;

3983 3984 3985 3986 3987 3988 3989
	dc_commit_updates_for_stream(adev->dm.dc,
					     surface_updates,
					     1,
					     acrtc_state->stream,
					     NULL,
					     &surface_updates->surface,
					     state);
3990 3991 3992 3993 3994 3995 3996

	DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
			 __func__,
			 addr.address.grph.addr.high_part,
			 addr.address.grph.addr.low_part);
}

3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086
/*
 * TODO this whole function needs to go
 *
 * dc_surface_update is needlessly complex. See if we can just replace this
 * with a dc_plane_state and follow the atomic model a bit more closely here.
 */
static bool commit_planes_to_stream(
		struct dc *dc,
		struct dc_plane_state **plane_states,
		uint8_t new_plane_count,
		struct dm_crtc_state *dm_new_crtc_state,
		struct dm_crtc_state *dm_old_crtc_state,
		struct dc_state *state)
{
	/* no need to dynamically allocate this. it's pretty small */
	struct dc_surface_update updates[MAX_SURFACES];
	struct dc_flip_addrs *flip_addr;
	struct dc_plane_info *plane_info;
	struct dc_scaling_info *scaling_info;
	int i;
	struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
	struct dc_stream_update *stream_update =
			kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);

	if (!stream_update) {
		BREAK_TO_DEBUGGER();
		return false;
	}

	flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
			    GFP_KERNEL);
	plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
			     GFP_KERNEL);
	scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
			       GFP_KERNEL);

	if (!flip_addr || !plane_info || !scaling_info) {
		kfree(flip_addr);
		kfree(plane_info);
		kfree(scaling_info);
		kfree(stream_update);
		return false;
	}

	memset(updates, 0, sizeof(updates));

	stream_update->src = dc_stream->src;
	stream_update->dst = dc_stream->dst;
	stream_update->out_transfer_func = dc_stream->out_transfer_func;

	for (i = 0; i < new_plane_count; i++) {
		updates[i].surface = plane_states[i];
		updates[i].gamma =
			(struct dc_gamma *)plane_states[i]->gamma_correction;
		updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
		flip_addr[i].address = plane_states[i]->address;
		flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
		plane_info[i].color_space = plane_states[i]->color_space;
		plane_info[i].format = plane_states[i]->format;
		plane_info[i].plane_size = plane_states[i]->plane_size;
		plane_info[i].rotation = plane_states[i]->rotation;
		plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
		plane_info[i].stereo_format = plane_states[i]->stereo_format;
		plane_info[i].tiling_info = plane_states[i]->tiling_info;
		plane_info[i].visible = plane_states[i]->visible;
		plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
		plane_info[i].dcc = plane_states[i]->dcc;
		scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
		scaling_info[i].src_rect = plane_states[i]->src_rect;
		scaling_info[i].dst_rect = plane_states[i]->dst_rect;
		scaling_info[i].clip_rect = plane_states[i]->clip_rect;

		updates[i].flip_addr = &flip_addr[i];
		updates[i].plane_info = &plane_info[i];
		updates[i].scaling_info = &scaling_info[i];
	}

	dc_commit_updates_for_stream(
			dc,
			updates,
			new_plane_count,
			dc_stream, stream_update, plane_states, state);

	kfree(flip_addr);
	kfree(plane_info);
	kfree(scaling_info);
	kfree(stream_update);
	return true;
}

4087
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
4088 4089 4090 4091
				    struct drm_device *dev,
				    struct amdgpu_display_manager *dm,
				    struct drm_crtc *pcrtc,
				    bool *wait_for_vblank)
4092 4093 4094
{
	uint32_t i;
	struct drm_plane *plane;
4095
	struct drm_plane_state *old_plane_state, *new_plane_state;
4096
	struct dc_stream_state *dc_stream_attach;
4097
	struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
4098
	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
4099 4100 4101
	struct drm_crtc_state *new_pcrtc_state =
			drm_atomic_get_new_crtc_state(state, pcrtc);
	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4102 4103
	struct dm_crtc_state *dm_old_crtc_state =
			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
4104
	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4105 4106 4107 4108
	int planes_count = 0;
	unsigned long flags;

	/* update planes when needed */
4109 4110
	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
		struct drm_crtc *crtc = new_plane_state->crtc;
4111
		struct drm_crtc_state *new_crtc_state;
4112
		struct drm_framebuffer *fb = new_plane_state->fb;
4113
		bool pflip_needed;
4114
		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
4115 4116 4117 4118 4119 4120

		if (plane->type == DRM_PLANE_TYPE_CURSOR) {
			handle_cursor_update(plane, old_plane_state);
			continue;
		}

4121 4122 4123 4124 4125
		if (!fb || !crtc || pcrtc != crtc)
			continue;

		new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
		if (!new_crtc_state->active)
4126 4127 4128 4129 4130 4131
			continue;

		pflip_needed = !state->allow_modeset;

		spin_lock_irqsave(&crtc->dev->event_lock, flags);
		if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
4132 4133 4134
			DRM_ERROR("%s: acrtc %d, already busy\n",
				  __func__,
				  acrtc_attach->crtc_id);
4135
			/* In commit tail framework this cannot happen */
4136 4137 4138 4139
			WARN_ON(1);
		}
		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);

4140
		if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
4141
			WARN_ON(!dm_new_plane_state->dc_state);
4142

4143
			plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
4144 4145 4146 4147

			dc_stream_attach = acrtc_state->stream;
			planes_count++;

4148
		} else if (new_crtc_state->planes_changed) {
4149 4150 4151 4152 4153
			/* Assume even ONE crtc with immediate flip means
			 * entire can't wait for VBLANK
			 * TODO Check if it's correct
			 */
			*wait_for_vblank =
4154
					new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
4155 4156 4157 4158 4159 4160 4161 4162 4163
				false : true;

			/* TODO: Needs rework for multiplane flip */
			if (plane->type == DRM_PLANE_TYPE_PRIMARY)
				drm_crtc_vblank_get(crtc);

			amdgpu_dm_do_flip(
				crtc,
				fb,
4164
				(uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
4165
				dm_state->context);
4166 4167 4168 4169 4170 4171 4172
		}

	}

	if (planes_count) {
		unsigned long flags;

4173
		if (new_pcrtc_state->event) {
4174 4175 4176 4177 4178 4179 4180 4181

			drm_crtc_vblank_get(pcrtc);

			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
			prepare_flip_isr(acrtc_attach);
			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
		}

4182 4183

		if (false == commit_planes_to_stream(dm->dc,
4184 4185
							plane_states_constructed,
							planes_count,
4186 4187
							acrtc_state,
							dm_old_crtc_state,
4188
							dm_state->context))
4189
			dm_error("%s: Failed to attach plane!\n", __func__);
4190 4191 4192 4193 4194
	} else {
		/*TODO BUG Here should go disable planes on CRTC. */
	}
}

4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207
/**
 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
 * @crtc_state: the DRM CRTC state
 * @stream_state: the DC stream state.
 *
 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
 */
static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
						struct dc_stream_state *stream_state)
{
	stream_state->mode_changed = crtc_state->mode_changed;
}
4208

4209 4210 4211
static int amdgpu_dm_atomic_commit(struct drm_device *dev,
				   struct drm_atomic_state *state,
				   bool nonblock)
4212 4213
{
	struct drm_crtc *crtc;
4214
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4215 4216 4217 4218 4219 4220 4221 4222 4223 4224
	struct amdgpu_device *adev = dev->dev_private;
	int i;

	/*
	 * We evade vblanks and pflips on crtc that
	 * should be changed. We do it here to flush & disable
	 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
	 * it will update crtc->dm_crtc_state->stream pointer which is used in
	 * the ISRs.
	 */
4225
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4226
		struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4227 4228
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

4229
		if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
4230 4231
			manage_dm_interrupts(adev, acrtc, false);
	}
4232 4233
	/* Add check here for SoC's that support hardware cursor plane, to
	 * unset legacy_cursor_update */
4234 4235 4236 4237 4238 4239

	return drm_atomic_helper_commit(dev, state, nonblock);

	/*TODO Handle EINTR, reenable IRQ*/
}

4240
static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4241 4242 4243 4244 4245 4246
{
	struct drm_device *dev = state->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_display_manager *dm = &adev->dm;
	struct dm_atomic_state *dm_state;
	uint32_t i, j;
4247
	struct drm_crtc *crtc;
4248
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4249 4250 4251
	unsigned long flags;
	bool wait_for_vblank = true;
	struct drm_connector *connector;
4252
	struct drm_connector_state *old_con_state, *new_con_state;
4253
	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4254
	int crtc_disable_count = 0;
4255 4256 4257 4258 4259 4260

	drm_atomic_helper_update_legacy_modeset_state(dev, state);

	dm_state = to_dm_atomic_state(state);

	/* update changed items */
4261
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4262
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4263

4264 4265
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4266

4267
		DRM_DEBUG_DRIVER(
4268 4269 4270 4271
			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
			"connectors_changed:%d\n",
			acrtc->crtc_id,
4272 4273 4274 4275 4276 4277
			new_crtc_state->enable,
			new_crtc_state->active,
			new_crtc_state->planes_changed,
			new_crtc_state->mode_changed,
			new_crtc_state->active_changed,
			new_crtc_state->connectors_changed);
4278

4279 4280 4281 4282 4283 4284
		/* Copy all transient state flags into dc state */
		if (dm_new_crtc_state->stream) {
			amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
							    dm_new_crtc_state->stream);
		}

4285 4286 4287 4288
		/* handles headless hotplug case, updating new_state and
		 * aconnector as needed
		 */

4289
		if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
4290

4291
			DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4292

4293
			if (!dm_new_crtc_state->stream) {
4294
				/*
4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308
				 * this could happen because of issues with
				 * userspace notifications delivery.
				 * In this case userspace tries to set mode on
				 * display which is disconnect in fact.
				 * dc_sink in NULL in this case on aconnector.
				 * We expect reset mode will come soon.
				 *
				 * This can also happen when unplug is done
				 * during resume sequence ended
				 *
				 * In this case, we want to pretend we still
				 * have a sink to keep the pipe running so that
				 * hw state is consistent with the sw state
				 */
4309
				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4310 4311 4312 4313
						__func__, acrtc->base.base.id);
				continue;
			}

4314 4315
			if (dm_old_crtc_state->stream)
				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4316

4317 4318
			pm_runtime_get_noresume(dev->dev);

4319
			acrtc->enabled = true;
4320 4321 4322
			acrtc->hw_mode = new_crtc_state->mode;
			crtc->hwmode = new_crtc_state->mode;
		} else if (modereset_required(new_crtc_state)) {
4323
			DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4324 4325

			/* i.e. reset mode */
4326 4327
			if (dm_old_crtc_state->stream)
				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4328 4329 4330 4331 4332 4333 4334 4335
		}
	} /* for_each_crtc_in_state() */

	/*
	 * Add streams after required streams from new and replaced streams
	 * are removed from freesync module
	 */
	if (adev->dm.freesync_module) {
4336 4337
		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
					      new_crtc_state, i) {
4338
			struct amdgpu_dm_connector *aconnector = NULL;
4339 4340
			struct dm_connector_state *dm_new_con_state = NULL;
			struct amdgpu_crtc *acrtc = NULL;
4341
			bool modeset_needed;
4342

4343
			dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358
			dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
			modeset_needed = modeset_required(
					new_crtc_state,
					dm_new_crtc_state->stream,
					dm_old_crtc_state->stream);
			/* We add stream to freesync if:
			 * 1. Said stream is not null, and
			 * 2. A modeset is requested. This means that the
			 *    stream was removed previously, and needs to be
			 *    replaced.
			 */
			if (dm_new_crtc_state->stream == NULL ||
					!modeset_needed)
				continue;

4359
			acrtc = to_amdgpu_crtc(crtc);
4360

4361 4362 4363
			aconnector =
				amdgpu_dm_find_first_crtc_matching_connector(
					state, crtc);
4364
			if (!aconnector) {
4365 4366 4367 4368 4369
				DRM_DEBUG_DRIVER("Atomic commit: Failed to "
						 "find connector for acrtc "
						 "id:%d skipping freesync "
						 "init\n",
						 acrtc->crtc_id);
4370 4371 4372 4373
				continue;
			}

			mod_freesync_add_stream(adev->dm.freesync_module,
4374 4375 4376 4377 4378 4379
						dm_new_crtc_state->stream,
						&aconnector->caps);
			new_con_state = drm_atomic_get_new_connector_state(
					state, &aconnector->base);
			dm_new_con_state = to_dm_connector_state(new_con_state);

4380 4381 4382 4383
			mod_freesync_set_user_enable(adev->dm.freesync_module,
						     &dm_new_crtc_state->stream,
						     1,
						     &dm_new_con_state->user_enable);
4384
		}
4385 4386
	}

4387 4388
	if (dm_state->context) {
		dm_enable_per_frame_crtc_master_sync(dm_state->context);
4389
		WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
4390
	}
4391

4392
	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4393
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4394

4395
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4396

4397
		if (dm_new_crtc_state->stream != NULL) {
4398
			const struct dc_stream_status *status =
4399
					dc_stream_get_status(dm_new_crtc_state->stream);
4400 4401

			if (!status)
4402
				DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
4403 4404 4405 4406 4407
			else
				acrtc->otg_inst = status->primary_otg_inst;
		}
	}

L
Leo (Sunpeng) Li 已提交
4408
	/* Handle scaling and underscan changes*/
4409
	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4410 4411 4412
		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4413 4414
		struct dc_stream_status *status = NULL;

4415
		if (acrtc) {
4416
			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4417 4418
			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
		}
4419

4420
		/* Skip any modesets/resets */
4421
		if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
4422 4423 4424
			continue;

		/* Skip any thing not scale or underscan changes */
4425
		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4426 4427
			continue;

4428
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4429

4430 4431
		update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
				dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
4432

4433 4434 4435
		if (!dm_new_crtc_state->stream)
			continue;

4436
		status = dc_stream_get_status(dm_new_crtc_state->stream);
4437
		WARN_ON(!status);
4438
		WARN_ON(!status->plane_count);
4439 4440

		/*TODO How it works with MPO ?*/
4441
		if (!commit_planes_to_stream(
4442
				dm->dc,
4443 4444
				status->plane_states,
				status->plane_count,
4445 4446
				dm_new_crtc_state,
				to_dm_crtc_state(old_crtc_state),
4447
				dm_state->context))
4448 4449 4450
			dm_error("%s: Failed to update stream scaling!\n", __func__);
	}

4451 4452
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
			new_crtc_state, i) {
4453 4454 4455
		/*
		 * loop to enable interrupts on newly arrived crtc
		 */
4456 4457
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
		bool modeset_needed;
4458

4459 4460 4461
		if (old_crtc_state->active && !new_crtc_state->active)
			crtc_disable_count++;

4462
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4463 4464 4465 4466 4467 4468 4469 4470
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
		modeset_needed = modeset_required(
				new_crtc_state,
				dm_new_crtc_state->stream,
				dm_old_crtc_state->stream);

		if (dm_new_crtc_state->stream == NULL || !modeset_needed)
			continue;
4471 4472 4473

		if (adev->dm.freesync_module)
			mod_freesync_notify_mode_change(
4474 4475
				adev->dm.freesync_module,
				&dm_new_crtc_state->stream, 1);
4476 4477 4478 4479 4480

		manage_dm_interrupts(adev, acrtc, true);
	}

	/* update planes when needed per crtc*/
4481
	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
4482
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4483

4484
		if (dm_new_crtc_state->stream)
4485
			amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
4486 4487 4488 4489 4490 4491 4492 4493
	}


	/*
	 * send vblank event on all events not handled in flip and
	 * mark consumed event for drm_atomic_helper_commit_hw_done
	 */
	spin_lock_irqsave(&adev->ddev->event_lock, flags);
4494
	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4495

4496 4497
		if (new_crtc_state->event)
			drm_send_event_locked(dev, &new_crtc_state->event->base);
4498

4499
		new_crtc_state->event = NULL;
4500 4501 4502 4503 4504 4505 4506
	}
	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);

	/* Signal HW programming completion */
	drm_atomic_helper_commit_hw_done(state);

	if (wait_for_vblank)
4507
		drm_atomic_helper_wait_for_flip_done(dev, state);
4508 4509

	drm_atomic_helper_cleanup_planes(dev, state);
4510 4511 4512 4513 4514

	/* Finally, drop a runtime PM reference for each newly disabled CRTC,
	 * so we can put the GPU into runtime suspend if we're not driving any
	 * displays anymore
	 */
4515 4516
	for (i = 0; i < crtc_disable_count; i++)
		pm_runtime_put_autosuspend(dev->dev);
4517
	pm_runtime_mark_last_busy(dev->dev);
4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582
}


static int dm_force_atomic_commit(struct drm_connector *connector)
{
	int ret = 0;
	struct drm_device *ddev = connector->dev;
	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
	struct drm_plane *plane = disconnected_acrtc->base.primary;
	struct drm_connector_state *conn_state;
	struct drm_crtc_state *crtc_state;
	struct drm_plane_state *plane_state;

	if (!state)
		return -ENOMEM;

	state->acquire_ctx = ddev->mode_config.acquire_ctx;

	/* Construct an atomic state to restore previous display setting */

	/*
	 * Attach connectors to drm_atomic_state
	 */
	conn_state = drm_atomic_get_connector_state(state, connector);

	ret = PTR_ERR_OR_ZERO(conn_state);
	if (ret)
		goto err;

	/* Attach crtc to drm_atomic_state*/
	crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);

	ret = PTR_ERR_OR_ZERO(crtc_state);
	if (ret)
		goto err;

	/* force a restore */
	crtc_state->mode_changed = true;

	/* Attach plane to drm_atomic_state */
	plane_state = drm_atomic_get_plane_state(state, plane);

	ret = PTR_ERR_OR_ZERO(plane_state);
	if (ret)
		goto err;


	/* Call commit internally with the state we just constructed */
	ret = drm_atomic_commit(state);
	if (!ret)
		return 0;

err:
	DRM_ERROR("Restoring old state failed with %i\n", ret);
	drm_atomic_state_put(state);

	return ret;
}

/*
 * This functions handle all cases when set mode does not come upon hotplug.
 * This include when the same display is unplugged then plugged back into the
 * same port and when we are running without usermode desktop manager supprot
 */
4583 4584
void dm_restore_drm_connector_state(struct drm_device *dev,
				    struct drm_connector *connector)
4585
{
4586
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4587 4588 4589 4590 4591 4592 4593
	struct amdgpu_crtc *disconnected_acrtc;
	struct dm_crtc_state *acrtc_state;

	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
		return;

	disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4594 4595
	if (!disconnected_acrtc)
		return;
4596

4597 4598
	acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
	if (!acrtc_state->stream)
4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613
		return;

	/*
	 * If the previous sink is not released and different from the current,
	 * we deduce we are in a state where we can not rely on usermode call
	 * to turn on the display, so we do it here
	 */
	if (acrtc_state->stream->sink != aconnector->dc_sink)
		dm_force_atomic_commit(&aconnector->base);
}

/*`
 * Grabs all modesetting locks to serialize against any blocking commits,
 * Waits for completion of all non blocking commits.
 */
4614 4615
static int do_aquire_global_lock(struct drm_device *dev,
				 struct drm_atomic_state *state)
4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650
{
	struct drm_crtc *crtc;
	struct drm_crtc_commit *commit;
	long ret;

	/* Adding all modeset locks to aquire_ctx will
	 * ensure that when the framework release it the
	 * extra locks we are locking here will get released to
	 */
	ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
	if (ret)
		return ret;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		spin_lock(&crtc->commit_lock);
		commit = list_first_entry_or_null(&crtc->commit_list,
				struct drm_crtc_commit, commit_entry);
		if (commit)
			drm_crtc_commit_get(commit);
		spin_unlock(&crtc->commit_lock);

		if (!commit)
			continue;

		/* Make sure all pending HW programming completed and
		 * page flips done
		 */
		ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);

		if (ret > 0)
			ret = wait_for_completion_interruptible_timeout(
					&commit->flip_done, 10*HZ);

		if (ret == 0)
			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4651
				  "timed out\n", crtc->base.id, crtc->name);
4652 4653 4654 4655 4656 4657 4658

		drm_crtc_commit_put(commit);
	}

	return ret < 0 ? ret : 0;
}

4659 4660 4661 4662
static int dm_update_crtcs_state(struct dc *dc,
				 struct drm_atomic_state *state,
				 bool enable,
				 bool *lock_and_validation_needed)
4663 4664
{
	struct drm_crtc *crtc;
4665
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4666
	int i;
4667
	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4668
	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4669
	struct dc_stream_state *new_stream;
4670
	int ret = 0;
4671

4672 4673
	/*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
	/* update changed items */
4674
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4675
		struct amdgpu_crtc *acrtc = NULL;
4676
		struct amdgpu_dm_connector *aconnector = NULL;
4677 4678
		struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
		struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
4679
		struct drm_plane_state *new_plane_state = NULL;
4680

4681 4682
		new_stream = NULL;

4683 4684
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4685
		acrtc = to_amdgpu_crtc(crtc);
4686

4687 4688 4689 4690 4691 4692 4693
		new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);

		if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
			ret = -EINVAL;
			goto fail;
		}

4694
		aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
4695

4696
		/* TODO This hack should go away */
4697 4698
		if (aconnector && enable) {
			// Make sure fake sink is created in plug-in scenario
4699
			drm_new_conn_state = drm_atomic_get_new_connector_state(state,
4700
 								    &aconnector->base);
4701 4702
			drm_old_conn_state = drm_atomic_get_old_connector_state(state,
								    &aconnector->base);
4703

4704 4705
			if (IS_ERR(drm_new_conn_state)) {
				ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
4706 4707
				break;
			}
4708

4709 4710
			dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
			dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
4711

4712
			new_stream = create_stream_for_sink(aconnector,
4713
							     &new_crtc_state->mode,
4714
							    dm_new_conn_state);
4715

4716 4717 4718 4719 4720 4721
			/*
			 * we can have no stream on ACTION_SET if a display
			 * was disconnected during S3, in this case it not and
			 * error, the OS will be updated after detection, and
			 * do the right thing on next atomic commit
			 */
4722

4723
			if (!new_stream) {
4724
				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4725 4726
						__func__, acrtc->base.base.id);
				break;
4727
			}
4728

4729 4730 4731 4732 4733 4734
			if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
			    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
				new_crtc_state->mode_changed = false;
				DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
						 new_crtc_state->mode_changed);
			}
4735
		}
4736

4737
		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4738
			goto next_crtc;
4739

4740
		DRM_DEBUG_DRIVER(
4741 4742 4743 4744
			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
			"connectors_changed:%d\n",
			acrtc->crtc_id,
4745 4746 4747 4748 4749 4750
			new_crtc_state->enable,
			new_crtc_state->active,
			new_crtc_state->planes_changed,
			new_crtc_state->mode_changed,
			new_crtc_state->active_changed,
			new_crtc_state->connectors_changed);
4751

4752 4753 4754
		/* Remove stream for any changed/disabled CRTC */
		if (!enable) {

4755
			if (!dm_old_crtc_state->stream)
4756
				goto next_crtc;
4757

4758
			DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
4759
					crtc->base.id);
4760

4761
			/* i.e. reset mode */
4762
			if (dc_remove_stream_from_ctx(
4763 4764
					dc,
					dm_state->context,
4765
					dm_old_crtc_state->stream) != DC_OK) {
4766
				ret = -EINVAL;
4767
				goto fail;
4768 4769
			}

4770 4771
			dc_stream_release(dm_old_crtc_state->stream);
			dm_new_crtc_state->stream = NULL;
4772 4773 4774 4775

			*lock_and_validation_needed = true;

		} else {/* Add stream for any updated/enabled CRTC */
4776 4777 4778 4779 4780 4781
			/*
			 * Quick fix to prevent NULL pointer on new_stream when
			 * added MST connectors not found in existing crtc_state in the chained mode
			 * TODO: need to dig out the root cause of that
			 */
			if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
4782
				goto next_crtc;
4783

4784
			if (modereset_required(new_crtc_state))
4785
				goto next_crtc;
4786

4787
			if (modeset_required(new_crtc_state, new_stream,
4788
					     dm_old_crtc_state->stream)) {
4789

4790
				WARN_ON(dm_new_crtc_state->stream);
4791

4792
				dm_new_crtc_state->stream = new_stream;
4793

4794 4795
				dc_stream_retain(new_stream);

4796
				DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
4797
							crtc->base.id);
4798

4799
				if (dc_add_stream_to_ctx(
4800 4801
						dc,
						dm_state->context,
4802
						dm_new_crtc_state->stream) != DC_OK) {
4803
					ret = -EINVAL;
4804
					goto fail;
4805 4806
				}

4807
				*lock_and_validation_needed = true;
4808
			}
4809
		}
4810

4811
next_crtc:
4812 4813 4814
		/* Release extra reference */
		if (new_stream)
			 dc_stream_release(new_stream);
4815 4816 4817 4818 4819

		/*
		 * We want to do dc stream updates that do not require a
		 * full modeset below.
		 */
4820 4821
		if (!(enable && aconnector && new_crtc_state->enable &&
		      new_crtc_state->active))
4822 4823 4824
			continue;
		/*
		 * Given above conditions, the dc state cannot be NULL because:
4825 4826 4827 4828 4829
		 * 1. We're in the process of enabling CRTCs (just been added
		 *    to the dc context, or already is on the context)
		 * 2. Has a valid connector attached, and
		 * 3. Is currently active and enabled.
		 * => The dc stream state currently exists.
4830 4831 4832
		 */
		BUG_ON(dm_new_crtc_state->stream == NULL);

4833 4834 4835 4836 4837
		/* Scaling or underscan settings */
		if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
			update_stream_scaling_settings(
				&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);

4838 4839 4840 4841 4842 4843
		/*
		 * Color management settings. We also update color properties
		 * when a modeset is needed, to ensure it gets reprogrammed.
		 */
		if (dm_new_crtc_state->base.color_mgmt_changed ||
		    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4844 4845 4846 4847 4848
			ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
			if (ret)
				goto fail;
			amdgpu_dm_set_ctm(dm_new_crtc_state);
		}
4849
	}
4850

4851
	return ret;
4852 4853 4854 4855 4856

fail:
	if (new_stream)
		dc_stream_release(new_stream);
	return ret;
4857
}
4858

4859 4860 4861 4862
static int dm_update_planes_state(struct dc *dc,
				  struct drm_atomic_state *state,
				  bool enable,
				  bool *lock_and_validation_needed)
4863 4864
{
	struct drm_crtc *new_plane_crtc, *old_plane_crtc;
4865
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4866 4867
	struct drm_plane *plane;
	struct drm_plane_state *old_plane_state, *new_plane_state;
4868
	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
4869
	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4870
	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
4871 4872 4873 4874
	int i ;
	/* TODO return page_flip_needed() function */
	bool pflip_needed  = !state->allow_modeset;
	int ret = 0;
4875

4876

4877 4878
	/* Add new planes, in reverse order as DC expectation */
	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
4879 4880
		new_plane_crtc = new_plane_state->crtc;
		old_plane_crtc = old_plane_state->crtc;
4881 4882
		dm_new_plane_state = to_dm_plane_state(new_plane_state);
		dm_old_plane_state = to_dm_plane_state(old_plane_state);
4883 4884 4885 4886

		/*TODO Implement atomic check for cursor plane */
		if (plane->type == DRM_PLANE_TYPE_CURSOR)
			continue;
4887

4888 4889
		/* Remove any changed/removed planes */
		if (!enable) {
4890 4891
			if (pflip_needed &&
			    plane->type != DRM_PLANE_TYPE_OVERLAY)
4892
				continue;
4893

4894 4895 4896
			if (!old_plane_crtc)
				continue;

4897 4898
			old_crtc_state = drm_atomic_get_old_crtc_state(
					state, old_plane_crtc);
4899
			dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4900

4901
			if (!dm_old_crtc_state->stream)
4902 4903
				continue;

4904
			DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
4905
					plane->base.id, old_plane_crtc->base.id);
4906

4907 4908
			if (!dc_remove_plane_from_context(
					dc,
4909 4910
					dm_old_crtc_state->stream,
					dm_old_plane_state->dc_state,
4911 4912 4913 4914
					dm_state->context)) {

				ret = EINVAL;
				return ret;
4915 4916
			}

4917

4918 4919
			dc_plane_state_release(dm_old_plane_state->dc_state);
			dm_new_plane_state->dc_state = NULL;
4920

4921
			*lock_and_validation_needed = true;
4922

4923
		} else { /* Add new planes */
4924
			struct dc_plane_state *dc_new_plane_state;
4925

4926 4927
			if (drm_atomic_plane_disabling(plane->state, new_plane_state))
				continue;
4928

4929 4930
			if (!new_plane_crtc)
				continue;
4931

4932
			new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
4933
			dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4934

4935
			if (!dm_new_crtc_state->stream)
4936 4937
				continue;

4938 4939
			if (pflip_needed &&
			    plane->type != DRM_PLANE_TYPE_OVERLAY)
4940
				continue;
4941

4942
			WARN_ON(dm_new_plane_state->dc_state);
4943

4944
			dc_new_plane_state = dc_create_plane_state(dc);
4945 4946
			if (!dc_new_plane_state)
				return -ENOMEM;
4947

4948 4949 4950
			DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
					plane->base.id, new_plane_crtc->base.id);

4951 4952
			ret = fill_plane_attributes(
				new_plane_crtc->dev->dev_private,
4953
				dc_new_plane_state,
4954
				new_plane_state,
4955
				new_crtc_state);
4956 4957
			if (ret) {
				dc_plane_state_release(dc_new_plane_state);
4958
				return ret;
4959
			}
4960

4961 4962 4963 4964 4965 4966 4967
			/*
			 * Any atomic check errors that occur after this will
			 * not need a release. The plane state will be attached
			 * to the stream, and therefore part of the atomic
			 * state. It'll be released when the atomic state is
			 * cleaned.
			 */
4968 4969
			if (!dc_add_plane_to_context(
					dc,
4970
					dm_new_crtc_state->stream,
4971
					dc_new_plane_state,
4972 4973
					dm_state->context)) {

4974
				dc_plane_state_release(dc_new_plane_state);
4975
				return -EINVAL;
4976
			}
4977

4978 4979
			dm_new_plane_state->dc_state = dc_new_plane_state;

4980 4981 4982 4983 4984
			/* Tell DC to do a full surface update every time there
			 * is a plane change. Inefficient, but works for now.
			 */
			dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;

4985
			*lock_and_validation_needed = true;
4986
		}
4987
	}
4988 4989


4990 4991 4992
	return ret;
}

4993 4994
static int amdgpu_dm_atomic_check(struct drm_device *dev,
				  struct drm_atomic_state *state)
4995 4996 4997 4998 4999
{
	struct amdgpu_device *adev = dev->dev_private;
	struct dc *dc = adev->dm.dc;
	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
	struct drm_connector *connector;
5000
	struct drm_connector_state *old_con_state, *new_con_state;
5001
	struct drm_crtc *crtc;
5002
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5003
	int ret, i;
5004

5005 5006 5007 5008 5009 5010 5011
	/*
	 * This bool will be set for true for any modeset/reset
	 * or plane update which implies non fast surface update.
	 */
	bool lock_and_validation_needed = false;

	ret = drm_atomic_helper_check_modeset(dev, state);
5012 5013
	if (ret)
		goto fail;
5014

5015 5016 5017 5018
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
		    !new_crtc_state->color_mgmt_changed)
			continue;
5019

5020 5021
		if (!new_crtc_state->enable)
			continue;
5022

5023 5024 5025
		ret = drm_atomic_add_affected_connectors(state, crtc);
		if (ret)
			return ret;
5026

5027 5028 5029
		ret = drm_atomic_add_affected_planes(state, crtc);
		if (ret)
			goto fail;
5030 5031
	}

5032 5033
	dm_state->context = dc_create_state();
	ASSERT(dm_state->context);
5034
	dc_resource_state_copy_construct_current(dc, dm_state->context);
5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059

	/* Remove exiting planes if they are modified */
	ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
	if (ret) {
		goto fail;
	}

	/* Disable all crtcs which require disable */
	ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
	if (ret) {
		goto fail;
	}

	/* Enable all crtcs which require enable */
	ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
	if (ret) {
		goto fail;
	}

	/* Add new/modified planes */
	ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
	if (ret) {
		goto fail;
	}

5060 5061 5062 5063
	/* Run this here since we want to validate the streams we created */
	ret = drm_atomic_helper_check_planes(dev, state);
	if (ret)
		goto fail;
5064

L
Leo (Sunpeng) Li 已提交
5065
	/* Check scaling and underscan changes*/
5066 5067 5068 5069
	/*TODO Removed scaling changes validation due to inability to commit
	 * new stream into context w\o causing full reset. Need to
	 * decide how to handle.
	 */
5070
	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5071 5072 5073
		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5074 5075

		/* Skip any modesets/resets */
5076 5077
		if (!acrtc || drm_atomic_crtc_needs_modeset(
				drm_atomic_get_new_crtc_state(state, &acrtc->base)))
5078 5079
			continue;

5080
		/* Skip any thing not scale or underscan changes */
5081
		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101
			continue;

		lock_and_validation_needed = true;
	}

	/*
	 * For full updates case when
	 * removing/adding/updating  streams on once CRTC while flipping
	 * on another CRTC,
	 * acquiring global lock  will guarantee that any such full
	 * update commit
	 * will wait for completion of any outstanding flip using DRMs
	 * synchronization events.
	 */

	if (lock_and_validation_needed) {

		ret = do_aquire_global_lock(dev, state);
		if (ret)
			goto fail;
5102

5103
		if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114
			ret = -EINVAL;
			goto fail;
		}
	}

	/* Must be success */
	WARN_ON(ret);
	return ret;

fail:
	if (ret == -EDEADLK)
5115
		DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
5116
	else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
5117
		DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
5118
	else
5119
		DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
5120 5121 5122 5123

	return ret;
}

5124 5125
static bool is_dp_capable_without_timing_msa(struct dc *dc,
					     struct amdgpu_dm_connector *amdgpu_dm_connector)
5126 5127 5128 5129
{
	uint8_t dpcd_data;
	bool capable = false;

5130
	if (amdgpu_dm_connector->dc_link &&
5131 5132
		dm_helpers_dp_read_dpcd(
				NULL,
5133
				amdgpu_dm_connector->dc_link,
5134 5135 5136 5137 5138 5139 5140 5141
				DP_DOWN_STREAM_PORT_COUNT,
				&dpcd_data,
				sizeof(dpcd_data))) {
		capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
	}

	return capable;
}
5142 5143
void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
					   struct edid *edid)
5144 5145 5146 5147 5148 5149
{
	int i;
	bool edid_check_required;
	struct detailed_timing *timing;
	struct detailed_non_pixel *data;
	struct detailed_data_monitor_range *range;
5150 5151
	struct amdgpu_dm_connector *amdgpu_dm_connector =
			to_amdgpu_dm_connector(connector);
5152
	struct dm_connector_state *dm_con_state;
5153 5154 5155

	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
5156

5157 5158 5159 5160 5161 5162 5163
	if (!connector->state) {
		DRM_ERROR("%s - Connector has no state", __func__);
		return;
	}

	dm_con_state = to_dm_connector_state(connector->state);

5164
	edid_check_required = false;
5165
	if (!amdgpu_dm_connector->dc_sink) {
5166 5167 5168 5169 5170 5171 5172 5173 5174
		DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
		return;
	}
	if (!adev->dm.freesync_module)
		return;
	/*
	 * if edid non zero restrict freesync only for dp and edp
	 */
	if (edid) {
5175 5176
		if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
			|| amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
5177 5178
			edid_check_required = is_dp_capable_without_timing_msa(
						adev->dm.dc,
5179
						amdgpu_dm_connector);
5180 5181
		}
	}
5182
	dm_con_state->freesync_capable = false;
5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203
	if (edid_check_required == true && (edid->version > 1 ||
	   (edid->version == 1 && edid->revision > 1))) {
		for (i = 0; i < 4; i++) {

			timing	= &edid->detailed_timings[i];
			data	= &timing->data.other_data;
			range	= &data->data.range;
			/*
			 * Check if monitor has continuous frequency mode
			 */
			if (data->type != EDID_DETAIL_MONITOR_RANGE)
				continue;
			/*
			 * Check for flag range limits only. If flag == 1 then
			 * no additional timing information provided.
			 * Default GTF, GTF Secondary curve and CVT are not
			 * supported
			 */
			if (range->flags != 1)
				continue;

5204 5205 5206
			amdgpu_dm_connector->min_vfreq = range->min_vfreq;
			amdgpu_dm_connector->max_vfreq = range->max_vfreq;
			amdgpu_dm_connector->pixel_clock_mhz =
5207 5208 5209 5210
				range->pixel_clock_mhz * 10;
			break;
		}

5211 5212 5213 5214 5215 5216 5217
		if (amdgpu_dm_connector->max_vfreq -
				amdgpu_dm_connector->min_vfreq > 10) {
			amdgpu_dm_connector->caps.supported = true;
			amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
					amdgpu_dm_connector->min_vfreq * 1000000;
			amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
					amdgpu_dm_connector->max_vfreq * 1000000;
5218
			dm_con_state->freesync_capable = true;
5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229
		}
	}

	/*
	 * TODO figure out how to notify user-mode or DRM of freesync caps
	 * once we figure out how to deal with freesync in an upstreamable
	 * fashion
	 */

}

5230
void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
5231 5232 5233 5234 5235 5236
{
	/*
	 * TODO fill in once we figure out how to deal with freesync in
	 * an upstreamable fashion
	 */
}