gf100.c 48.2 KB
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/*
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 * Copyright 2012 Red Hat Inc.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
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#include "gf100.h"
#include "ctxgf100.h"
#include "fuc/os.h"

#include <core/client.h>
#include <core/handle.h>
#include <core/option.h>
#include <engine/fifo.h>
#include <subdev/fb.h>
#include <subdev/mc.h>
#include <subdev/timer.h>

#include <nvif/class.h>
#include <nvif/unpack.h>
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/*******************************************************************************
 * Zero Bandwidth Clear
 ******************************************************************************/

static void
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gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
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{
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	struct nvkm_device *device = gr->base.engine.subdev.device;
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	if (gr->zbc_color[zbc].format) {
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		nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
		nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
		nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
		nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
	}
	nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
	nvkm_wr32(device, 0x405820, zbc);
	nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
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}

static int
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gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
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		       const u32 ds[4], const u32 l2[4])
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{
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	struct nvkm_ltc *ltc = nvkm_ltc(gr);
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	int zbc = -ENOSPC, i;

	for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
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		if (gr->zbc_color[i].format) {
			if (gr->zbc_color[i].format != format)
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				continue;
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			if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
				   gr->zbc_color[i].ds)))
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				continue;
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			if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
				   gr->zbc_color[i].l2))) {
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				WARN_ON(1);
				return -EINVAL;
			}
			return i;
		} else {
			zbc = (zbc < 0) ? i : zbc;
		}
	}

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	if (zbc < 0)
		return zbc;

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	memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
	memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
	gr->zbc_color[zbc].format = format;
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	ltc->zbc_color_get(ltc, zbc, l2);
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	gf100_gr_zbc_clear_color(gr, zbc);
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	return zbc;
}

static void
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gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
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{
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	struct nvkm_device *device = gr->base.engine.subdev.device;
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	if (gr->zbc_depth[zbc].format)
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		nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
	nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
	nvkm_wr32(device, 0x405820, zbc);
	nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
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}

static int
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gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
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		       const u32 ds, const u32 l2)
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{
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	struct nvkm_ltc *ltc = nvkm_ltc(gr);
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	int zbc = -ENOSPC, i;

	for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
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		if (gr->zbc_depth[i].format) {
			if (gr->zbc_depth[i].format != format)
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				continue;
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			if (gr->zbc_depth[i].ds != ds)
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				continue;
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			if (gr->zbc_depth[i].l2 != l2) {
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				WARN_ON(1);
				return -EINVAL;
			}
			return i;
		} else {
			zbc = (zbc < 0) ? i : zbc;
		}
	}

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	if (zbc < 0)
		return zbc;

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	gr->zbc_depth[zbc].format = format;
	gr->zbc_depth[zbc].ds = ds;
	gr->zbc_depth[zbc].l2 = l2;
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	ltc->zbc_depth_get(ltc, zbc, l2);
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	gf100_gr_zbc_clear_depth(gr, zbc);
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	return zbc;
}

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/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

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static int
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gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
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{
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	struct gf100_gr *gr = (void *)object->engine;
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	union {
		struct fermi_a_zbc_color_v0 v0;
	} *args = data;
	int ret;

	if (nvif_unpack(args->v0, 0, 0, false)) {
		switch (args->v0.format) {
		case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
		case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
		case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
		case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
		case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
		case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
		case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
		case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
		case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
		case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
		case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
		case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
		case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
		case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
		case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
		case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
		case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
		case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
		case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
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			ret = gf100_gr_zbc_color_get(gr, args->v0.format,
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							   args->v0.ds,
							   args->v0.l2);
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			if (ret >= 0) {
				args->v0.index = ret;
				return 0;
			}
			break;
		default:
			return -EINVAL;
		}
	}

	return ret;
}

static int
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gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
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{
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	struct gf100_gr *gr = (void *)object->engine;
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	union {
		struct fermi_a_zbc_depth_v0 v0;
	} *args = data;
	int ret;

	if (nvif_unpack(args->v0, 0, 0, false)) {
		switch (args->v0.format) {
		case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
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			ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
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							   args->v0.ds,
							   args->v0.l2);
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			return (ret >= 0) ? 0 : -ENOSPC;
		default:
			return -EINVAL;
		}
	}

	return ret;
}

static int
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gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
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{
	switch (mthd) {
	case FERMI_A_ZBC_COLOR:
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		return gf100_fermi_mthd_zbc_color(object, data, size);
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	case FERMI_A_ZBC_DEPTH:
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		return gf100_fermi_mthd_zbc_depth(object, data, size);
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	default:
		break;
	}
	return -EINVAL;
}

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struct nvkm_ofuncs
gf100_fermi_ofuncs = {
	.ctor = _nvkm_object_ctor,
	.dtor = nvkm_object_destroy,
	.init = nvkm_object_init,
	.fini = nvkm_object_fini,
	.mthd = gf100_fermi_mthd,
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};

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static int
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gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd,
			       void *pdata, u32 size)
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{
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	struct gf100_gr *gr = (void *)object->engine;
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	struct nvkm_device *device = gr->base.engine.subdev.device;
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	if (size >= sizeof(u32)) {
		u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
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		nvkm_wr32(device, 0x419e44, data);
		nvkm_wr32(device, 0x419e4c, data);
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		return 0;
	}
	return -EINVAL;
}

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struct nvkm_omthds
gf100_gr_9097_omthds[] = {
	{ 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
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	{}
};

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struct nvkm_omthds
gf100_gr_90c0_omthds[] = {
	{ 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
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	{}
};

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struct nvkm_oclass
gf100_gr_sclass[] = {
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	{ FERMI_TWOD_A, &nvkm_object_ofuncs },
	{ FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs },
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	{ FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
	{ FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
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	{}
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/
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int
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gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
		      struct nvkm_oclass *oclass, void *args, u32 size,
		      struct nvkm_object **pobject)
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{
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	struct nvkm_vm *vm = nvkm_client(parent)->vm;
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	struct gf100_gr *gr = (void *)engine;
	struct gf100_gr_data *data = gr->mmio_data;
	struct gf100_gr_mmio *mmio = gr->mmio_list;
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	struct gf100_gr_chan *chan;
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	struct nvkm_gpuobj *image;
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	int ret, i;

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	/* allocate memory for context, and fill with default values */
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	ret = nvkm_gr_context_create(parent, engine, oclass, NULL,
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				     gr->size, 0x100,
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				     NVOBJ_FLAG_ZERO_ALLOC, &chan);
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	*pobject = nv_object(chan);
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	if (ret)
		return ret;

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	/* allocate memory for a "mmio list" buffer that's used by the HUB
	 * fuc to modify some per-context register settings on first load
	 * of the context.
	 */
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	ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,
			      &chan->mmio);
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	if (ret)
		return ret;

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	ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
				 NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
				 &chan->mmio_vma);
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	if (ret)
		return ret;

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	/* allocate buffers referenced by mmio list */
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	for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {
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		ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size,
				      data->align, 0, &chan->data[i].mem);
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		if (ret)
			return ret;
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		ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
					 &chan->data[i].vma);
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		if (ret)
			return ret;
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		data++;
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	}

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	/* finally, fill in the mmio list and point the context at it */
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	nvkm_kmap(chan->mmio);
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	for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
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		u32 addr = mmio->addr;
		u32 data = mmio->data;
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		if (mmio->buffer >= 0) {
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			u64 info = chan->data[mmio->buffer].vma.offset;
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			data |= info >> mmio->shift;
		}
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		nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
		nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
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		mmio++;
	}
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	nvkm_done(chan->mmio);
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	image = &chan->base.base.gpuobj;
	nvkm_kmap(image);
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	for (i = 0; i < gr->size; i += 4)
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		nvkm_wo32(image, i, gr->data[i / 4]);
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	if (!gr->firmware) {
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		nvkm_wo32(image, 0x00, chan->mmio_nr / 2);
		nvkm_wo32(image, 0x04, chan->mmio_vma.offset >> 8);
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	} else {
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		nvkm_wo32(image, 0xf4, 0);
		nvkm_wo32(image, 0xf8, 0);
		nvkm_wo32(image, 0x10, chan->mmio_nr / 2);
		nvkm_wo32(image, 0x14, lower_32_bits(chan->mmio_vma.offset));
		nvkm_wo32(image, 0x18, upper_32_bits(chan->mmio_vma.offset));
		nvkm_wo32(image, 0x1c, 1);
		nvkm_wo32(image, 0x20, 0);
		nvkm_wo32(image, 0x28, 0);
		nvkm_wo32(image, 0x2c, 0);
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	}
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	nvkm_done(image);
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	return 0;
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}

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void
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gf100_gr_context_dtor(struct nvkm_object *object)
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{
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	struct gf100_gr_chan *chan = (void *)object;
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	int i;

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	for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
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		nvkm_gpuobj_unmap(&chan->data[i].vma);
		nvkm_gpuobj_ref(NULL, &chan->data[i].mem);
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	}
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	nvkm_gpuobj_unmap(&chan->mmio_vma);
	nvkm_gpuobj_ref(NULL, &chan->mmio);
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	nvkm_gr_context_destroy(&chan->base);
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}

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/*******************************************************************************
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 * PGRAPH register lists
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 ******************************************************************************/

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const struct gf100_gr_init
gf100_gr_init_main_0[] = {
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	{ 0x400080,   1, 0x04, 0x003083c2 },
	{ 0x400088,   1, 0x04, 0x00006fe7 },
	{ 0x40008c,   1, 0x04, 0x00000000 },
	{ 0x400090,   1, 0x04, 0x00000030 },
	{ 0x40013c,   1, 0x04, 0x013901f7 },
	{ 0x400140,   1, 0x04, 0x00000100 },
	{ 0x400144,   1, 0x04, 0x00000000 },
	{ 0x400148,   1, 0x04, 0x00000110 },
	{ 0x400138,   1, 0x04, 0x00000000 },
	{ 0x400130,   2, 0x04, 0x00000000 },
	{ 0x400124,   1, 0x04, 0x00000002 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_fe_0[] = {
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	{ 0x40415c,   1, 0x04, 0x00000000 },
	{ 0x404170,   1, 0x04, 0x00000000 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_pri_0[] = {
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	{ 0x404488,   2, 0x04, 0x00000000 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_rstr2d_0[] = {
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	{ 0x407808,   1, 0x04, 0x00000000 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_pd_0[] = {
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	{ 0x406024,   1, 0x04, 0x00000000 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_ds_0[] = {
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	{ 0x405844,   1, 0x04, 0x00ffffff },
	{ 0x405850,   1, 0x04, 0x00000000 },
	{ 0x405908,   1, 0x04, 0x00000000 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_scc_0[] = {
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	{ 0x40803c,   1, 0x04, 0x00000000 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_prop_0[] = {
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	{ 0x4184a0,   1, 0x04, 0x00000000 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_gpc_unk_0[] = {
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	{ 0x418604,   1, 0x04, 0x00000000 },
	{ 0x418680,   1, 0x04, 0x00000000 },
	{ 0x418714,   1, 0x04, 0x80000000 },
	{ 0x418384,   1, 0x04, 0x00000000 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_setup_0[] = {
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	{ 0x418814,   3, 0x04, 0x00000000 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_crstr_0[] = {
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	{ 0x418b04,   1, 0x04, 0x00000000 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_setup_1[] = {
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	{ 0x4188c8,   1, 0x04, 0x80000000 },
	{ 0x4188cc,   1, 0x04, 0x00000000 },
	{ 0x4188d0,   1, 0x04, 0x00010000 },
	{ 0x4188d4,   1, 0x04, 0x00000001 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_zcull_0[] = {
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	{ 0x418910,   1, 0x04, 0x00010001 },
	{ 0x418914,   1, 0x04, 0x00000301 },
	{ 0x418918,   1, 0x04, 0x00800000 },
	{ 0x418980,   1, 0x04, 0x77777770 },
	{ 0x418984,   3, 0x04, 0x77777777 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_gpm_0[] = {
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	{ 0x418c04,   1, 0x04, 0x00000000 },
	{ 0x418c88,   1, 0x04, 0x00000000 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_gpc_unk_1[] = {
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	{ 0x418d00,   1, 0x04, 0x00000000 },
	{ 0x418f08,   1, 0x04, 0x00000000 },
	{ 0x418e00,   1, 0x04, 0x00000050 },
	{ 0x418e08,   1, 0x04, 0x00000000 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_gcc_0[] = {
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	{ 0x41900c,   1, 0x04, 0x00000000 },
	{ 0x419018,   1, 0x04, 0x00000000 },
	{}
};

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const struct gf100_gr_init
gf100_gr_init_tpccs_0[] = {
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	{ 0x419d08,   2, 0x04, 0x00000000 },
	{ 0x419d10,   1, 0x04, 0x00000014 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_tex_0[] = {
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	{ 0x419ab0,   1, 0x04, 0x00000000 },
	{ 0x419ab8,   1, 0x04, 0x000000e7 },
	{ 0x419abc,   2, 0x04, 0x00000000 },
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	{}
};

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const struct gf100_gr_init
gf100_gr_init_pe_0[] = {
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	{ 0x41980c,   3, 0x04, 0x00000000 },
	{ 0x419844,   1, 0x04, 0x00000000 },
	{ 0x41984c,   1, 0x04, 0x00005bc5 },
	{ 0x419850,   4, 0x04, 0x00000000 },
534 535 536
	{}
};

537 538
const struct gf100_gr_init
gf100_gr_init_l1c_0[] = {
539 540 541 542 543 544
	{ 0x419c98,   1, 0x04, 0x00000000 },
	{ 0x419ca8,   1, 0x04, 0x80000000 },
	{ 0x419cb4,   1, 0x04, 0x00000000 },
	{ 0x419cb8,   1, 0x04, 0x00008bf4 },
	{ 0x419cbc,   1, 0x04, 0x28137606 },
	{ 0x419cc0,   2, 0x04, 0x00000000 },
545 546 547
	{}
};

548 549
const struct gf100_gr_init
gf100_gr_init_wwdx_0[] = {
550 551
	{ 0x419bd4,   1, 0x04, 0x00800000 },
	{ 0x419bdc,   1, 0x04, 0x00000000 },
552 553 554
	{}
};

555 556
const struct gf100_gr_init
gf100_gr_init_tpccs_1[] = {
557
	{ 0x419d2c,   1, 0x04, 0x00000000 },
558 559 560
	{}
};

561 562
const struct gf100_gr_init
gf100_gr_init_mpc_0[] = {
563
	{ 0x419c0c,   1, 0x04, 0x00000000 },
564 565 566
	{}
};

567 568
static const struct gf100_gr_init
gf100_gr_init_sm_0[] = {
569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584
	{ 0x419e00,   1, 0x04, 0x00000000 },
	{ 0x419ea0,   1, 0x04, 0x00000000 },
	{ 0x419ea4,   1, 0x04, 0x00000100 },
	{ 0x419ea8,   1, 0x04, 0x00001100 },
	{ 0x419eac,   1, 0x04, 0x11100702 },
	{ 0x419eb0,   1, 0x04, 0x00000003 },
	{ 0x419eb4,   4, 0x04, 0x00000000 },
	{ 0x419ec8,   1, 0x04, 0x06060618 },
	{ 0x419ed0,   1, 0x04, 0x0eff0e38 },
	{ 0x419ed4,   1, 0x04, 0x011104f1 },
	{ 0x419edc,   1, 0x04, 0x00000000 },
	{ 0x419f00,   1, 0x04, 0x00000000 },
	{ 0x419f2c,   1, 0x04, 0x00000000 },
	{}
};

585 586
const struct gf100_gr_init
gf100_gr_init_be_0[] = {
587 588 589 590 591 592 593 594 595 596
	{ 0x40880c,   1, 0x04, 0x00000000 },
	{ 0x408910,   9, 0x04, 0x00000000 },
	{ 0x408950,   1, 0x04, 0x00000000 },
	{ 0x408954,   1, 0x04, 0x0000ffff },
	{ 0x408984,   1, 0x04, 0x00000000 },
	{ 0x408988,   1, 0x04, 0x08040201 },
	{ 0x40898c,   1, 0x04, 0x80402010 },
	{}
};

597 598
const struct gf100_gr_init
gf100_gr_init_fe_1[] = {
599 600 601 602
	{ 0x4040f0,   1, 0x04, 0x00000000 },
	{}
};

603 604
const struct gf100_gr_init
gf100_gr_init_pe_1[] = {
605 606 607 608
	{ 0x419880,   1, 0x04, 0x00000002 },
	{}
};

609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637
static const struct gf100_gr_pack
gf100_gr_pack_mmio[] = {
	{ gf100_gr_init_main_0 },
	{ gf100_gr_init_fe_0 },
	{ gf100_gr_init_pri_0 },
	{ gf100_gr_init_rstr2d_0 },
	{ gf100_gr_init_pd_0 },
	{ gf100_gr_init_ds_0 },
	{ gf100_gr_init_scc_0 },
	{ gf100_gr_init_prop_0 },
	{ gf100_gr_init_gpc_unk_0 },
	{ gf100_gr_init_setup_0 },
	{ gf100_gr_init_crstr_0 },
	{ gf100_gr_init_setup_1 },
	{ gf100_gr_init_zcull_0 },
	{ gf100_gr_init_gpm_0 },
	{ gf100_gr_init_gpc_unk_1 },
	{ gf100_gr_init_gcc_0 },
	{ gf100_gr_init_tpccs_0 },
	{ gf100_gr_init_tex_0 },
	{ gf100_gr_init_pe_0 },
	{ gf100_gr_init_l1c_0 },
	{ gf100_gr_init_wwdx_0 },
	{ gf100_gr_init_tpccs_1 },
	{ gf100_gr_init_mpc_0 },
	{ gf100_gr_init_sm_0 },
	{ gf100_gr_init_be_0 },
	{ gf100_gr_init_fe_1 },
	{ gf100_gr_init_pe_1 },
M
Maarten Lankhorst 已提交
638 639 640
	{}
};

641 642 643 644
/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

645
void
B
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646
gf100_gr_zbc_init(struct gf100_gr *gr)
647 648 649 650 651 652 653 654 655
{
	const u32  zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
			      0x00000000, 0x00000000, 0x00000000, 0x00000000 };
	const u32   one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
			      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
	const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
			      0x00000000, 0x00000000, 0x00000000, 0x00000000 };
	const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
			      0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
B
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656
	struct nvkm_ltc *ltc = nvkm_ltc(gr);
657 658
	int index;

B
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659 660 661 662 663 664 665
	if (!gr->zbc_color[0].format) {
		gf100_gr_zbc_color_get(gr, 1,  & zero[0],   &zero[4]);
		gf100_gr_zbc_color_get(gr, 2,  &  one[0],    &one[4]);
		gf100_gr_zbc_color_get(gr, 4,  &f32_0[0],  &f32_0[4]);
		gf100_gr_zbc_color_get(gr, 4,  &f32_1[0],  &f32_1[4]);
		gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000);
		gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000);
666 667 668
	}

	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
B
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669
		gf100_gr_zbc_clear_color(gr, index);
670
	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
B
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671
		gf100_gr_zbc_clear_depth(gr, index);
672 673
}

674 675 676 677 678 679
/**
 * Wait until GR goes idle. GR is considered idle if it is disabled by the
 * MC (0x200) register, or GR is not busy and a context switch is not in
 * progress.
 */
int
B
Ben Skeggs 已提交
680
gf100_gr_wait_idle(struct gf100_gr *gr)
681
{
682 683
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
684 685 686 687 688 689 690 691
	unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
	bool gr_enabled, ctxsw_active, gr_busy;

	do {
		/*
		 * required to make sure FIFO_ENGINE_STATUS (0x2640) is
		 * up-to-date
		 */
692
		nvkm_rd32(device, 0x400700);
693

694 695 696
		gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
		ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;
		gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
697 698 699 700 701

		if (!gr_enabled || (!gr_busy && !ctxsw_active))
			return 0;
	} while (time_before(jiffies, end_jiffies));

702 703 704
	nvkm_error(subdev,
		   "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
		   gr_enabled, ctxsw_active, gr_busy);
705 706 707
	return -EAGAIN;
}

708
void
B
Ben Skeggs 已提交
709
gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
710
{
711
	struct nvkm_device *device = gr->base.engine.subdev.device;
712 713
	const struct gf100_gr_pack *pack;
	const struct gf100_gr_init *init;
714 715 716 717 718

	pack_for_each_init(init, pack, p) {
		u32 next = init->addr + init->count * init->pitch;
		u32 addr = init->addr;
		while (addr < next) {
719
			nvkm_wr32(device, addr, init->data);
720 721 722
			addr += init->pitch;
		}
	}
723 724 725
}

void
B
Ben Skeggs 已提交
726
gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
727
{
728
	struct nvkm_device *device = gr->base.engine.subdev.device;
729 730
	const struct gf100_gr_pack *pack;
	const struct gf100_gr_init *init;
731
	u32 data = 0;
732

733
	nvkm_wr32(device, 0x400208, 0x80000000);
734 735 736 737 738 739

	pack_for_each_init(init, pack, p) {
		u32 next = init->addr + init->count * init->pitch;
		u32 addr = init->addr;

		if ((pack == p && init == p->init) || data != init->data) {
740
			nvkm_wr32(device, 0x400204, init->data);
741 742
			data = init->data;
		}
743

744
		while (addr < next) {
745
			nvkm_wr32(device, 0x400200, addr);
746 747 748 749 750
			/**
			 * Wait for GR to go idle after submitting a
			 * GO_IDLE bundle
			 */
			if ((addr & 0xffff) == 0xe100)
B
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751
				gf100_gr_wait_idle(gr);
752 753 754 755
			nvkm_msec(device, 2000,
				if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
					break;
			);
756 757 758
			addr += init->pitch;
		}
	}
759

760
	nvkm_wr32(device, 0x400208, 0x00000000);
761 762 763
}

void
B
Ben Skeggs 已提交
764
gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
765
{
766
	struct nvkm_device *device = gr->base.engine.subdev.device;
767 768
	const struct gf100_gr_pack *pack;
	const struct gf100_gr_init *init;
769
	u32 data = 0;
770

771 772 773 774 775 776
	pack_for_each_init(init, pack, p) {
		u32 ctrl = 0x80000000 | pack->type;
		u32 next = init->addr + init->count * init->pitch;
		u32 addr = init->addr;

		if ((pack == p && init == p->init) || data != init->data) {
777
			nvkm_wr32(device, 0x40448c, init->data);
778 779 780 781
			data = init->data;
		}

		while (addr < next) {
782
			nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
783
			addr += init->pitch;
784 785 786 787 788
		}
	}
}

u64
B
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gf100_gr_units(struct nvkm_gr *obj)
790
{
B
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791
	struct gf100_gr *gr = container_of(obj, typeof(*gr), base);
792 793
	u64 cfg;

B
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794 795 796
	cfg  = (u32)gr->gpc_nr;
	cfg |= (u32)gr->tpc_total << 8;
	cfg |= (u64)gr->rop_nr << 32;
797 798

	return cfg;
799 800
}

801 802 803 804 805 806 807 808 809 810 811 812
static const struct nvkm_bitfield gk104_sked_error[] = {
	{ 0x00000080, "CONSTANT_BUFFER_SIZE" },
	{ 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
	{ 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
	{ 0x00000800, "WARP_CSTACK_SIZE" },
	{ 0x00001000, "TOTAL_TEMP_SIZE" },
	{ 0x00002000, "REGISTER_COUNT" },
	{ 0x00040000, "TOTAL_THREADS" },
	{ 0x00100000, "PROGRAM_OFFSET" },
	{ 0x00200000, "SHARED_MEMORY_SIZE" },
	{ 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
	{ 0x04000000, "TOTAL_REGISTER_COUNT" },
813 814 815
	{}
};

816 817 818 819 820 821 822
static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
	{ 0x00000002, "RT_PITCH_OVERRUN" },
	{ 0x00000010, "RT_WIDTH_OVERRUN" },
	{ 0x00000020, "RT_HEIGHT_OVERRUN" },
	{ 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
	{ 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
	{ 0x00000400, "RT_LINEAR_MISMATCH" },
823 824 825
	{}
};

826
static void
B
Ben Skeggs 已提交
827
gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
828
{
829 830 831
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
	char error[128];
832
	u32 trap[4];
833

834
	trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
835 836 837
	trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
	trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
	trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
838

839
	nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
840

841 842 843 844
	nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
			   "format = %x, storage type = %x\n",
		   gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
		   (trap[2] >> 8) & 0x3f, trap[3] & 0xff);
845
	nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
846 847
}

848
static const struct nvkm_enum gf100_mp_warp_error[] = {
849 850 851 852 853 854 855 856 857 858 859 860
	{ 0x00, "NO_ERROR" },
	{ 0x01, "STACK_MISMATCH" },
	{ 0x05, "MISALIGNED_PC" },
	{ 0x08, "MISALIGNED_GPR" },
	{ 0x09, "INVALID_OPCODE" },
	{ 0x0d, "GPR_OUT_OF_BOUNDS" },
	{ 0x0e, "MEM_OUT_OF_BOUNDS" },
	{ 0x0f, "UNALIGNED_MEM_ACCESS" },
	{ 0x11, "INVALID_PARAM" },
	{}
};

861
static const struct nvkm_bitfield gf100_mp_global_error[] = {
862 863 864 865 866 867
	{ 0x00000004, "MULTIPLE_WARP_ERRORS" },
	{ 0x00000008, "OUT_OF_STACK_SPACE" },
	{}
};

static void
B
Ben Skeggs 已提交
868
gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
869
{
870 871
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
872 873
	u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
	u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
874 875
	const struct nvkm_enum *warp;
	char glob[128];
876

877 878 879 880 881 882
	nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
	warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);

	nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
			   "global %08x [%s] warp %04x [%s]\n",
		   gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
883

884 885
	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
886 887
}

888
static void
B
Ben Skeggs 已提交
889
gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
890
{
891 892
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
893
	u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
894 895

	if (stat & 0x00000001) {
896
		u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
897
		nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
898
		nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
899 900 901 902
		stat &= ~0x00000001;
	}

	if (stat & 0x00000002) {
B
Ben Skeggs 已提交
903
		gf100_gr_trap_mp(gr, gpc, tpc);
904 905 906 907
		stat &= ~0x00000002;
	}

	if (stat & 0x00000004) {
908
		u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
909
		nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
910
		nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
911 912 913 914
		stat &= ~0x00000004;
	}

	if (stat & 0x00000008) {
915
		u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
916
		nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
917
		nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
918 919 920 921
		stat &= ~0x00000008;
	}

	if (stat) {
922
		nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
923 924 925 926
	}
}

static void
B
Ben Skeggs 已提交
927
gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
928
{
929 930
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
931
	u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
932 933 934
	int tpc;

	if (stat & 0x00000001) {
B
Ben Skeggs 已提交
935
		gf100_gr_trap_gpc_rop(gr, gpc);
936 937 938 939
		stat &= ~0x00000001;
	}

	if (stat & 0x00000002) {
940
		u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
941
		nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
942
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
943 944 945 946
		stat &= ~0x00000002;
	}

	if (stat & 0x00000004) {
947
		u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
948
		nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
949
		nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
950 951 952 953
		stat &= ~0x00000004;
	}

	if (stat & 0x00000008) {
954
		u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
955
		nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
956
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
957 958 959
		stat &= ~0x00000009;
	}

B
Ben Skeggs 已提交
960
	for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
961 962
		u32 mask = 0x00010000 << tpc;
		if (stat & mask) {
B
Ben Skeggs 已提交
963
			gf100_gr_trap_tpc(gr, gpc, tpc);
964
			nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
965 966 967 968 969
			stat &= ~mask;
		}
	}

	if (stat) {
970
		nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
971 972 973 974
	}
}

static void
B
Ben Skeggs 已提交
975
gf100_gr_trap_intr(struct gf100_gr *gr)
976
{
977 978
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
979
	u32 trap = nvkm_rd32(device, 0x400108);
980
	int rop, gpc;
981 982

	if (trap & 0x00000001) {
983
		u32 stat = nvkm_rd32(device, 0x404000);
984
		nvkm_error(subdev, "DISPATCH %08x\n", stat);
985 986
		nvkm_wr32(device, 0x404000, 0xc0000000);
		nvkm_wr32(device, 0x400108, 0x00000001);
987 988 989 990
		trap &= ~0x00000001;
	}

	if (trap & 0x00000002) {
991
		u32 stat = nvkm_rd32(device, 0x404600);
992
		nvkm_error(subdev, "M2MF %08x\n", stat);
993 994
		nvkm_wr32(device, 0x404600, 0xc0000000);
		nvkm_wr32(device, 0x400108, 0x00000002);
995 996 997 998
		trap &= ~0x00000002;
	}

	if (trap & 0x00000008) {
999
		u32 stat = nvkm_rd32(device, 0x408030);
1000
		nvkm_error(subdev, "CCACHE %08x\n", stat);
1001 1002
		nvkm_wr32(device, 0x408030, 0xc0000000);
		nvkm_wr32(device, 0x400108, 0x00000008);
1003 1004 1005 1006
		trap &= ~0x00000008;
	}

	if (trap & 0x00000010) {
1007
		u32 stat = nvkm_rd32(device, 0x405840);
1008
		nvkm_error(subdev, "SHADER %08x\n", stat);
1009 1010
		nvkm_wr32(device, 0x405840, 0xc0000000);
		nvkm_wr32(device, 0x400108, 0x00000010);
1011 1012 1013 1014
		trap &= ~0x00000010;
	}

	if (trap & 0x00000040) {
1015
		u32 stat = nvkm_rd32(device, 0x40601c);
1016
		nvkm_error(subdev, "UNK6 %08x\n", stat);
1017 1018
		nvkm_wr32(device, 0x40601c, 0xc0000000);
		nvkm_wr32(device, 0x400108, 0x00000040);
1019 1020 1021 1022
		trap &= ~0x00000040;
	}

	if (trap & 0x00000080) {
1023
		u32 stat = nvkm_rd32(device, 0x404490);
1024
		nvkm_error(subdev, "MACRO %08x\n", stat);
1025 1026
		nvkm_wr32(device, 0x404490, 0xc0000000);
		nvkm_wr32(device, 0x400108, 0x00000080);
1027 1028 1029
		trap &= ~0x00000080;
	}

1030
	if (trap & 0x00000100) {
1031 1032
		u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
		char sked[128];
1033

1034 1035
		nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat);
		nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked);
1036

1037
		if (stat)
1038 1039
			nvkm_wr32(device, 0x407020, 0x40000000);
		nvkm_wr32(device, 0x400108, 0x00000100);
1040 1041 1042
		trap &= ~0x00000100;
	}

1043
	if (trap & 0x01000000) {
1044
		u32 stat = nvkm_rd32(device, 0x400118);
B
Ben Skeggs 已提交
1045
		for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
1046 1047
			u32 mask = 0x00000001 << gpc;
			if (stat & mask) {
B
Ben Skeggs 已提交
1048
				gf100_gr_trap_gpc(gr, gpc);
1049
				nvkm_wr32(device, 0x400118, mask);
1050 1051 1052
				stat &= ~mask;
			}
		}
1053
		nvkm_wr32(device, 0x400108, 0x01000000);
1054 1055 1056 1057
		trap &= ~0x01000000;
	}

	if (trap & 0x02000000) {
B
Ben Skeggs 已提交
1058
		for (rop = 0; rop < gr->rop_nr; rop++) {
1059 1060
			u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
			u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
1061
			nvkm_error(subdev, "ROP%d %08x %08x\n",
1062
				 rop, statz, statc);
1063 1064
			nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
			nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
1065
		}
1066
		nvkm_wr32(device, 0x400108, 0x02000000);
1067 1068 1069 1070
		trap &= ~0x02000000;
	}

	if (trap) {
1071
		nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
1072
		nvkm_wr32(device, 0x400108, trap);
1073 1074 1075
	}
}

1076
static void
B
Ben Skeggs 已提交
1077
gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
1078
{
1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
	nvkm_error(subdev, "%06x - done %08x\n", base,
		   nvkm_rd32(device, base + 0x400));
	nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
		   nvkm_rd32(device, base + 0x800),
		   nvkm_rd32(device, base + 0x804),
		   nvkm_rd32(device, base + 0x808),
		   nvkm_rd32(device, base + 0x80c));
	nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
		   nvkm_rd32(device, base + 0x810),
		   nvkm_rd32(device, base + 0x814),
		   nvkm_rd32(device, base + 0x818),
		   nvkm_rd32(device, base + 0x81c));
1093 1094 1095
}

void
B
Ben Skeggs 已提交
1096
gf100_gr_ctxctl_debug(struct gf100_gr *gr)
1097
{
1098 1099
	struct nvkm_device *device = gr->base.engine.subdev.device;
	u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
1100 1101
	u32 gpc;

B
Ben Skeggs 已提交
1102
	gf100_gr_ctxctl_debug_unit(gr, 0x409000);
1103
	for (gpc = 0; gpc < gpcnr; gpc++)
B
Ben Skeggs 已提交
1104
		gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
1105 1106 1107
}

static void
B
Ben Skeggs 已提交
1108
gf100_gr_ctxctl_isr(struct gf100_gr *gr)
1109
{
1110 1111
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
1112
	u32 stat = nvkm_rd32(device, 0x409c18);
1113

1114
	if (stat & 0x00000001) {
1115
		u32 code = nvkm_rd32(device, 0x409814);
1116
		if (code == E_BAD_FWMTHD) {
1117 1118
			u32 class = nvkm_rd32(device, 0x409808);
			u32  addr = nvkm_rd32(device, 0x40980c);
1119 1120
			u32  subc = (addr & 0x00070000) >> 16;
			u32  mthd = (addr & 0x00003ffc);
1121
			u32  data = nvkm_rd32(device, 0x409810);
1122

1123 1124 1125
			nvkm_error(subdev, "FECS MTHD subc %d class %04x "
					   "mthd %04x data %08x\n",
				   subc, class, mthd, data);
1126

1127
			nvkm_wr32(device, 0x409c20, 0x00000001);
1128 1129
			stat &= ~0x00000001;
		} else {
1130
			nvkm_error(subdev, "FECS ucode error %d\n", code);
1131 1132
		}
	}
1133

1134
	if (stat & 0x00080000) {
1135
		nvkm_error(subdev, "FECS watchdog timeout\n");
B
Ben Skeggs 已提交
1136
		gf100_gr_ctxctl_debug(gr);
1137
		nvkm_wr32(device, 0x409c20, 0x00080000);
1138 1139 1140 1141
		stat &= ~0x00080000;
	}

	if (stat) {
1142
		nvkm_error(subdev, "FECS %08x\n", stat);
B
Ben Skeggs 已提交
1143
		gf100_gr_ctxctl_debug(gr);
1144
		nvkm_wr32(device, 0x409c20, stat);
1145
	}
1146 1147
}

1148
static void
1149
gf100_gr_intr(struct nvkm_subdev *subdev)
1150
{
1151 1152 1153
	struct gf100_gr *gr = (void *)subdev;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fifo *fifo = device->fifo;
1154 1155 1156
	struct nvkm_engine *engine = nv_engine(subdev);
	struct nvkm_object *engctx;
	struct nvkm_handle *handle;
1157 1158 1159
	u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
	u32 stat = nvkm_rd32(device, 0x400100);
	u32 addr = nvkm_rd32(device, 0x400704);
1160 1161
	u32 mthd = (addr & 0x00003ffc);
	u32 subc = (addr & 0x00070000) >> 16;
1162 1163
	u32 data = nvkm_rd32(device, 0x400708);
	u32 code = nvkm_rd32(device, 0x400110);
1164
	u32 class;
1165 1166
	int chid;

B
Ben Skeggs 已提交
1167
	if (nv_device(gr)->card_type < NV_E0 || subc < 4)
1168
		class = nvkm_rd32(device, 0x404200 + (subc * 4));
1169 1170 1171
	else
		class = 0x0000;

1172
	engctx = nvkm_engctx_get(engine, inst);
B
Ben Skeggs 已提交
1173
	chid   = fifo->chid(fifo, engctx);
1174

1175 1176 1177 1178 1179
	if (stat & 0x00000001) {
		/*
		 * notifier interrupt, only needed for cyclestats
		 * can be safely ignored
		 */
1180
		nvkm_wr32(device, 0x400100, 0x00000001);
1181 1182 1183
		stat &= ~0x00000001;
	}

1184
	if (stat & 0x00000010) {
1185
		handle = nvkm_handle_get_class(engctx, class);
1186
		if (!handle || nv_call(handle->object, mthd, data)) {
1187 1188 1189 1190
			nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
				   "subc %d class %04x mthd %04x data %08x\n",
				   chid, inst << 12, nvkm_client_name(engctx),
				   subc, class, mthd, data);
1191
		}
1192
		nvkm_handle_put(handle);
1193
		nvkm_wr32(device, 0x400100, 0x00000010);
1194 1195 1196 1197
		stat &= ~0x00000010;
	}

	if (stat & 0x00000020) {
1198 1199 1200 1201
		nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
			   "subc %d class %04x mthd %04x data %08x\n",
			   chid, inst << 12, nvkm_client_name(engctx), subc,
			   class, mthd, data);
1202
		nvkm_wr32(device, 0x400100, 0x00000020);
1203 1204 1205 1206
		stat &= ~0x00000020;
	}

	if (stat & 0x00100000) {
1207 1208 1209 1210 1211 1212
		const struct nvkm_enum *en =
			nvkm_enum_find(nv50_data_error_names, code);
		nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
				   "subc %d class %04x mthd %04x data %08x\n",
			   code, en ? en->name : "", chid, inst << 12,
			   nvkm_client_name(engctx), subc, class, mthd, data);
1213
		nvkm_wr32(device, 0x400100, 0x00100000);
1214 1215 1216 1217
		stat &= ~0x00100000;
	}

	if (stat & 0x00200000) {
1218 1219 1220
		nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
			   chid, inst << 12,
			   nvkm_client_name(engctx));
B
Ben Skeggs 已提交
1221
		gf100_gr_trap_intr(gr);
1222
		nvkm_wr32(device, 0x400100, 0x00200000);
1223 1224 1225 1226
		stat &= ~0x00200000;
	}

	if (stat & 0x00080000) {
B
Ben Skeggs 已提交
1227
		gf100_gr_ctxctl_isr(gr);
1228
		nvkm_wr32(device, 0x400100, 0x00080000);
1229 1230 1231 1232
		stat &= ~0x00080000;
	}

	if (stat) {
1233
		nvkm_error(subdev, "intr %08x\n", stat);
1234
		nvkm_wr32(device, 0x400100, stat);
1235 1236
	}

1237
	nvkm_wr32(device, 0x400500, 0x00010001);
1238
	nvkm_engctx_put(engctx);
1239 1240
}

1241
void
B
Ben Skeggs 已提交
1242
gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base,
1243
		 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
1244
{
1245
	struct nvkm_device *device = gr->base.engine.subdev.device;
1246
	int i;
1247

1248
	nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000);
1249
	for (i = 0; i < data->size / 4; i++)
1250
		nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]);
1251

1252
	nvkm_wr32(device, fuc_base + 0x0180, 0x01000000);
1253 1254
	for (i = 0; i < code->size / 4; i++) {
		if ((i & 0x3f) == 0)
1255 1256
			nvkm_wr32(device, fuc_base + 0x0188, i >> 6);
		nvkm_wr32(device, fuc_base + 0x0184, code->data[i]);
1257
	}
1258 1259 1260

	/* code must be padded to 0x40 words */
	for (; i & 0x3f; i++)
1261
		nvkm_wr32(device, fuc_base + 0x0184, 0);
1262 1263
}

1264
static void
B
Ben Skeggs 已提交
1265
gf100_gr_init_csdata(struct gf100_gr *gr,
1266 1267
		     const struct gf100_gr_pack *pack,
		     u32 falcon, u32 starstar, u32 base)
1268
{
1269
	struct nvkm_device *device = gr->base.engine.subdev.device;
1270 1271
	const struct gf100_gr_pack *iter;
	const struct gf100_gr_init *init;
1272
	u32 addr = ~0, prev = ~0, xfer = 0;
1273 1274
	u32 star, temp;

1275 1276 1277
	nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
	star = nvkm_rd32(device, falcon + 0x01c4);
	temp = nvkm_rd32(device, falcon + 0x01c4);
1278 1279
	if (temp > star)
		star = temp;
1280
	nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
1281

1282 1283 1284 1285 1286 1287 1288
	pack_for_each_init(init, iter, pack) {
		u32 head = init->addr - base;
		u32 tail = head + init->count * init->pitch;
		while (head < tail) {
			if (head != prev + 4 || xfer >= 32) {
				if (xfer) {
					u32 data = ((--xfer << 26) | addr);
1289
					nvkm_wr32(device, falcon + 0x01c4, data);
1290 1291 1292 1293
					star += 4;
				}
				addr = head;
				xfer = 0;
1294
			}
1295 1296 1297
			prev = head;
			xfer = xfer + 1;
			head = head + init->pitch;
1298
		}
1299
	}
1300

1301 1302 1303
	nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
	nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
	nvkm_wr32(device, falcon + 0x01c4, star + 4);
1304 1305
}

1306
int
B
Ben Skeggs 已提交
1307
gf100_gr_init_ctxctl(struct gf100_gr *gr)
1308
{
1309 1310
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
B
Ben Skeggs 已提交
1311 1312
	struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass;
	struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass;
1313
	int i;
1314

B
Ben Skeggs 已提交
1315
	if (gr->firmware) {
1316
		/* load fuc microcode */
B
Ben Skeggs 已提交
1317 1318 1319 1320 1321 1322
		nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
		gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c,
						 &gr->fuc409d);
		gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac,
						 &gr->fuc41ad);
		nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
1323

1324
		/* start both of them running */
1325 1326 1327 1328 1329
		nvkm_wr32(device, 0x409840, 0xffffffff);
		nvkm_wr32(device, 0x41a10c, 0x00000000);
		nvkm_wr32(device, 0x40910c, 0x00000000);
		nvkm_wr32(device, 0x41a100, 0x00000002);
		nvkm_wr32(device, 0x409100, 0x00000002);
1330 1331 1332 1333 1334
		if (nvkm_msec(device, 2000,
			if (nvkm_rd32(device, 0x409800) & 0x00000001)
				break;
		) < 0)
			return -EBUSY;
B
Ben Skeggs 已提交
1335

1336 1337 1338
		nvkm_wr32(device, 0x409840, 0xffffffff);
		nvkm_wr32(device, 0x409500, 0x7fffffff);
		nvkm_wr32(device, 0x409504, 0x00000021);
B
Ben Skeggs 已提交
1339

1340 1341 1342
		nvkm_wr32(device, 0x409840, 0xffffffff);
		nvkm_wr32(device, 0x409500, 0x00000000);
		nvkm_wr32(device, 0x409504, 0x00000010);
1343 1344 1345 1346
		if (nvkm_msec(device, 2000,
			if ((gr->size = nvkm_rd32(device, 0x409800)))
				break;
		) < 0)
1347
			return -EBUSY;
1348

1349 1350 1351
		nvkm_wr32(device, 0x409840, 0xffffffff);
		nvkm_wr32(device, 0x409500, 0x00000000);
		nvkm_wr32(device, 0x409504, 0x00000016);
1352 1353 1354 1355
		if (nvkm_msec(device, 2000,
			if (nvkm_rd32(device, 0x409800))
				break;
		) < 0)
1356 1357
			return -EBUSY;

1358 1359 1360
		nvkm_wr32(device, 0x409840, 0xffffffff);
		nvkm_wr32(device, 0x409500, 0x00000000);
		nvkm_wr32(device, 0x409504, 0x00000025);
1361 1362 1363 1364
		if (nvkm_msec(device, 2000,
			if (nvkm_rd32(device, 0x409800))
				break;
		) < 0)
1365 1366
			return -EBUSY;

B
Ben Skeggs 已提交
1367
		if (nv_device(gr)->chipset >= 0xe0) {
1368 1369 1370
			nvkm_wr32(device, 0x409800, 0x00000000);
			nvkm_wr32(device, 0x409500, 0x00000001);
			nvkm_wr32(device, 0x409504, 0x00000030);
1371 1372 1373 1374
			if (nvkm_msec(device, 2000,
				if (nvkm_rd32(device, 0x409800))
					break;
			) < 0)
1375 1376
				return -EBUSY;

1377 1378 1379 1380
			nvkm_wr32(device, 0x409810, 0xb00095c8);
			nvkm_wr32(device, 0x409800, 0x00000000);
			nvkm_wr32(device, 0x409500, 0x00000001);
			nvkm_wr32(device, 0x409504, 0x00000031);
1381 1382 1383 1384
			if (nvkm_msec(device, 2000,
				if (nvkm_rd32(device, 0x409800))
					break;
			) < 0)
1385 1386
				return -EBUSY;

1387 1388 1389 1390
			nvkm_wr32(device, 0x409810, 0x00080420);
			nvkm_wr32(device, 0x409800, 0x00000000);
			nvkm_wr32(device, 0x409500, 0x00000001);
			nvkm_wr32(device, 0x409504, 0x00000032);
1391 1392 1393 1394
			if (nvkm_msec(device, 2000,
				if (nvkm_rd32(device, 0x409800))
					break;
			) < 0)
1395 1396
				return -EBUSY;

1397 1398 1399
			nvkm_wr32(device, 0x409614, 0x00000070);
			nvkm_wr32(device, 0x409614, 0x00000770);
			nvkm_wr32(device, 0x40802c, 0x00000001);
1400 1401
		}

B
Ben Skeggs 已提交
1402 1403
		if (gr->data == NULL) {
			int ret = gf100_grctx_generate(gr);
1404
			if (ret) {
1405
				nvkm_error(subdev, "failed to construct context\n");
1406 1407 1408 1409 1410
				return ret;
			}
		}

		return 0;
1411 1412 1413
	} else
	if (!oclass->fecs.ucode) {
		return -ENOSYS;
1414
	}
1415

1416
	/* load HUB microcode */
B
Ben Skeggs 已提交
1417
	nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
1418
	nvkm_wr32(device, 0x4091c0, 0x01000000);
1419
	for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
1420
		nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]);
1421

1422
	nvkm_wr32(device, 0x409180, 0x01000000);
1423
	for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) {
1424
		if ((i & 0x3f) == 0)
1425 1426
			nvkm_wr32(device, 0x409188, i >> 6);
		nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]);
1427 1428 1429
	}

	/* load GPC microcode */
1430
	nvkm_wr32(device, 0x41a1c0, 0x01000000);
1431
	for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
1432
		nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
1433

1434
	nvkm_wr32(device, 0x41a180, 0x01000000);
1435
	for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) {
1436
		if ((i & 0x3f) == 0)
1437 1438
			nvkm_wr32(device, 0x41a188, i >> 6);
		nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]);
1439
	}
B
Ben Skeggs 已提交
1440
	nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
1441

1442
	/* load register lists */
B
Ben Skeggs 已提交
1443 1444 1445 1446
	gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000);
	gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000);
	gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800);
	gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00);
1447

1448
	/* start HUB ucode running, it'll init the GPCs */
1449 1450
	nvkm_wr32(device, 0x40910c, 0x00000000);
	nvkm_wr32(device, 0x409100, 0x00000002);
1451 1452 1453 1454
	if (nvkm_msec(device, 2000,
		if (nvkm_rd32(device, 0x409800) & 0x80000000)
			break;
	) < 0) {
B
Ben Skeggs 已提交
1455
		gf100_gr_ctxctl_debug(gr);
1456 1457 1458
		return -EBUSY;
	}

1459
	gr->size = nvkm_rd32(device, 0x409804);
B
Ben Skeggs 已提交
1460 1461
	if (gr->data == NULL) {
		int ret = gf100_grctx_generate(gr);
1462
		if (ret) {
1463
			nvkm_error(subdev, "failed to construct context\n");
1464 1465
			return ret;
		}
1466 1467 1468
	}

	return 0;
1469 1470
}

1471
int
1472
gf100_gr_init(struct nvkm_object *object)
1473
{
B
Ben Skeggs 已提交
1474
	struct gf100_gr *gr = (void *)object;
1475 1476
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct gf100_gr_oclass *oclass = (void *)object->oclass;
B
Ben Skeggs 已提交
1477
	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
1478 1479 1480 1481
	u32 data[TPC_MAX / 8] = {};
	u8  tpcnr[GPC_MAX];
	int gpc, tpc, rop;
	int ret, i;
1482

B
Ben Skeggs 已提交
1483
	ret = nvkm_gr_init(&gr->base);
1484 1485 1486
	if (ret)
		return ret;

1487 1488 1489 1490 1491 1492 1493 1494
	nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
	nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
1495

B
Ben Skeggs 已提交
1496
	gf100_gr_mmio(gr, oclass->mmio);
1497

B
Ben Skeggs 已提交
1498 1499
	memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
	for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
1500
		do {
B
Ben Skeggs 已提交
1501
			gpc = (gpc + 1) % gr->gpc_nr;
1502
		} while (!tpcnr[gpc]);
B
Ben Skeggs 已提交
1503
		tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
1504 1505 1506 1507

		data[i / 8] |= tpc << ((i % 8) * 4);
	}

1508 1509 1510 1511
	nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
	nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
	nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
	nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
1512

B
Ben Skeggs 已提交
1513
	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1514
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
B
Ben Skeggs 已提交
1515
			gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
1516
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
B
Ben Skeggs 已提交
1517
			gr->tpc_total);
1518
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
1519 1520
	}

B
Ben Skeggs 已提交
1521
	if (nv_device(gr)->chipset != 0xd7)
1522
		nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
M
Maarten Lankhorst 已提交
1523
	else
1524
		nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
B
Ben Skeggs 已提交
1525

1526
	nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
B
Ben Skeggs 已提交
1527

1528
	nvkm_wr32(device, 0x400500, 0x00010001);
B
Ben Skeggs 已提交
1529

1530 1531
	nvkm_wr32(device, 0x400100, 0xffffffff);
	nvkm_wr32(device, 0x40013c, 0xffffffff);
B
Ben Skeggs 已提交
1532

1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543
	nvkm_wr32(device, 0x409c24, 0x000f0000);
	nvkm_wr32(device, 0x404000, 0xc0000000);
	nvkm_wr32(device, 0x404600, 0xc0000000);
	nvkm_wr32(device, 0x408030, 0xc0000000);
	nvkm_wr32(device, 0x40601c, 0xc0000000);
	nvkm_wr32(device, 0x404490, 0xc0000000);
	nvkm_wr32(device, 0x406018, 0xc0000000);
	nvkm_wr32(device, 0x405840, 0xc0000000);
	nvkm_wr32(device, 0x405844, 0x00ffffff);
	nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
	nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
B
Ben Skeggs 已提交
1544 1545

	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1546 1547 1548 1549
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
B
Ben Skeggs 已提交
1550
		for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
1551 1552 1553 1554 1555 1556 1557
			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
			nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
1558
		}
1559 1560
		nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
1561 1562
	}

B
Ben Skeggs 已提交
1563
	for (rop = 0; rop < gr->rop_nr; rop++) {
1564 1565 1566 1567
		nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
		nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
		nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
		nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
1568
	}
1569

1570 1571 1572 1573 1574 1575
	nvkm_wr32(device, 0x400108, 0xffffffff);
	nvkm_wr32(device, 0x400138, 0xffffffff);
	nvkm_wr32(device, 0x400118, 0xffffffff);
	nvkm_wr32(device, 0x400130, 0xffffffff);
	nvkm_wr32(device, 0x40011c, 0xffffffff);
	nvkm_wr32(device, 0x400134, 0xffffffff);
1576

1577
	nvkm_wr32(device, 0x400054, 0x34ce3464);
1578

B
Ben Skeggs 已提交
1579
	gf100_gr_zbc_init(gr);
1580

B
Ben Skeggs 已提交
1581
	return gf100_gr_init_ctxctl(gr);
1582 1583
}

1584
void
1585
gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
1586 1587 1588 1589 1590 1591
{
	kfree(fuc->data);
	fuc->data = NULL;
}

int
B
Ben Skeggs 已提交
1592
gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
1593
		 struct gf100_gr_fuc *fuc)
1594
{
1595 1596
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
1597
	const struct firmware *fw;
1598 1599
	char f[64];
	char cname[16];
1600
	int ret;
1601 1602 1603 1604 1605 1606 1607 1608 1609 1610
	int i;

	/* Convert device name to lowercase */
	strncpy(cname, device->cname, sizeof(cname));
	cname[sizeof(cname) - 1] = '\0';
	i = strlen(cname);
	while (i) {
		--i;
		cname[i] = tolower(cname[i]);
	}
1611

1612
	snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname);
A
Alexandre Courbot 已提交
1613
	ret = request_firmware(&fw, f, nv_device_base(device));
1614
	if (ret) {
1615
		nvkm_error(subdev, "failed to load %s\n", fwname);
1616
		return ret;
1617 1618 1619 1620 1621 1622 1623 1624 1625
	}

	fuc->size = fw->size;
	fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
	release_firmware(fw);
	return (fuc->data != NULL) ? 0 : -ENOMEM;
}

void
1626
gf100_gr_dtor(struct nvkm_object *object)
1627
{
B
Ben Skeggs 已提交
1628
	struct gf100_gr *gr = (void *)object;
1629

B
Ben Skeggs 已提交
1630
	kfree(gr->data);
1631

B
Ben Skeggs 已提交
1632 1633 1634 1635
	gf100_gr_dtor_fw(&gr->fuc409c);
	gf100_gr_dtor_fw(&gr->fuc409d);
	gf100_gr_dtor_fw(&gr->fuc41ac);
	gf100_gr_dtor_fw(&gr->fuc41ad);
1636

B
Ben Skeggs 已提交
1637 1638
	nvkm_gpuobj_ref(NULL, &gr->unk4188b8);
	nvkm_gpuobj_ref(NULL, &gr->unk4188b4);
1639

B
Ben Skeggs 已提交
1640
	nvkm_gr_destroy(&gr->base);
1641 1642 1643
}

int
1644 1645 1646
gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	      struct nvkm_oclass *bclass, void *data, u32 size,
	      struct nvkm_object **pobject)
1647
{
1648
	struct gf100_gr_oclass *oclass = (void *)bclass;
1649
	struct nvkm_device *device = (void *)parent;
B
Ben Skeggs 已提交
1650
	struct gf100_gr *gr;
1651
	bool use_ext_fw, enable;
1652
	int ret, i, j;
1653

1654 1655
	use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
				  oclass->fecs.ucode == NULL);
1656 1657
	enable = use_ext_fw || oclass->fecs.ucode != NULL;

B
Ben Skeggs 已提交
1658 1659
	ret = nvkm_gr_create(parent, engine, bclass, enable, &gr);
	*pobject = nv_object(gr);
1660 1661 1662
	if (ret)
		return ret;

B
Ben Skeggs 已提交
1663 1664
	nv_subdev(gr)->unit = 0x08001000;
	nv_subdev(gr)->intr = gf100_gr_intr;
1665

B
Ben Skeggs 已提交
1666
	gr->base.units = gf100_gr_units;
1667

1668
	if (use_ext_fw) {
1669
		nvkm_info(&gr->base.engine.subdev, "using external firmware\n");
B
Ben Skeggs 已提交
1670 1671 1672 1673
		if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
		    gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
		    gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
		    gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
1674
			return -ENODEV;
B
Ben Skeggs 已提交
1675
		gr->firmware = true;
1676 1677
	}

B
Ben Skeggs 已提交
1678 1679
	ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,
			      &gr->unk4188b4);
1680 1681
	if (ret)
		return ret;
1682

B
Ben Skeggs 已提交
1683 1684
	ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,
			      &gr->unk4188b8);
1685
	if (ret)
1686 1687
		return ret;

1688 1689 1690 1691 1692 1693 1694 1695 1696
	nvkm_kmap(gr->unk4188b4);
	for (i = 0; i < 0x1000; i += 4)
		nvkm_wo32(gr->unk4188b4, i, 0x00000010);
	nvkm_done(gr->unk4188b4);

	nvkm_kmap(gr->unk4188b8);
	for (i = 0; i < 0x1000; i += 4)
		nvkm_wo32(gr->unk4188b8, i, 0x00000010);
	nvkm_done(gr->unk4188b8);
B
Ben Skeggs 已提交
1697

1698 1699
	gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
	gr->gpc_nr =  nvkm_rd32(device, 0x409604) & 0x0000001f;
B
Ben Skeggs 已提交
1700
	for (i = 0; i < gr->gpc_nr; i++) {
1701
		gr->tpc_nr[i]  = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
B
Ben Skeggs 已提交
1702 1703 1704
		gr->tpc_total += gr->tpc_nr[i];
		gr->ppc_nr[i]  = oclass->ppc_nr;
		for (j = 0; j < gr->ppc_nr[i]; j++) {
1705
			u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
B
Ben Skeggs 已提交
1706
			gr->ppc_tpc_nr[i][j] = hweight8(mask);
1707
		}
1708 1709 1710
	}

	/*XXX: these need figuring out... though it might not even matter */
B
Ben Skeggs 已提交
1711
	switch (nv_device(gr)->chipset) {
1712
	case 0xc0:
B
Ben Skeggs 已提交
1713 1714
		if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
			gr->magic_not_rop_nr = 0x07;
1715
		} else
B
Ben Skeggs 已提交
1716 1717
		if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
			gr->magic_not_rop_nr = 0x05;
1718
		} else
B
Ben Skeggs 已提交
1719 1720
		if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
			gr->magic_not_rop_nr = 0x06;
1721 1722 1723
		}
		break;
	case 0xc3: /* 450, 4/0/0/0, 2 */
B
Ben Skeggs 已提交
1724
		gr->magic_not_rop_nr = 0x03;
1725 1726
		break;
	case 0xc4: /* 460, 3/4/0/0, 4 */
B
Ben Skeggs 已提交
1727
		gr->magic_not_rop_nr = 0x01;
1728 1729
		break;
	case 0xc1: /* 2/0/0/0, 1 */
B
Ben Skeggs 已提交
1730
		gr->magic_not_rop_nr = 0x01;
1731 1732
		break;
	case 0xc8: /* 4/4/3/4, 5 */
B
Ben Skeggs 已提交
1733
		gr->magic_not_rop_nr = 0x06;
1734 1735
		break;
	case 0xce: /* 4/4/0/0, 4 */
B
Ben Skeggs 已提交
1736
		gr->magic_not_rop_nr = 0x03;
1737 1738
		break;
	case 0xcf: /* 4/0/0/0, 3 */
B
Ben Skeggs 已提交
1739
		gr->magic_not_rop_nr = 0x03;
1740
		break;
M
Maarten Lankhorst 已提交
1741
	case 0xd7:
1742
	case 0xd9: /* 1/0/0/0, 1 */
1743
	case 0xea: /* gk20a */
1744
	case 0x12b: /* gm20b */
B
Ben Skeggs 已提交
1745
		gr->magic_not_rop_nr = 0x01;
1746 1747 1748
		break;
	}

B
Ben Skeggs 已提交
1749 1750
	nv_engine(gr)->cclass = *oclass->cclass;
	nv_engine(gr)->sclass =  oclass->sclass;
1751 1752 1753
	return 0;
}

1754
#include "fuc/hubgf100.fuc3.h"
1755

1756 1757 1758 1759 1760 1761
struct gf100_gr_ucode
gf100_gr_fecs_ucode = {
	.code.data = gf100_grhub_code,
	.code.size = sizeof(gf100_grhub_code),
	.data.data = gf100_grhub_data,
	.data.size = sizeof(gf100_grhub_data),
1762 1763
};

1764
#include "fuc/gpcgf100.fuc3.h"
1765

1766 1767 1768 1769 1770 1771
struct gf100_gr_ucode
gf100_gr_gpccs_ucode = {
	.code.data = gf100_grgpc_code,
	.code.size = sizeof(gf100_grgpc_code),
	.data.data = gf100_grgpc_data,
	.data.size = sizeof(gf100_grgpc_data),
1772 1773
};

1774 1775
struct nvkm_oclass *
gf100_gr_oclass = &(struct gf100_gr_oclass) {
1776
	.base.handle = NV_ENGINE(GR, 0xc0),
1777 1778 1779 1780 1781
	.base.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = gf100_gr_ctor,
		.dtor = gf100_gr_dtor,
		.init = gf100_gr_init,
		.fini = _nvkm_gr_fini,
1782
	},
1783 1784 1785 1786 1787
	.cclass = &gf100_grctx_oclass,
	.sclass =  gf100_gr_sclass,
	.mmio = gf100_gr_pack_mmio,
	.fecs.ucode = &gf100_gr_fecs_ucode,
	.gpccs.ucode = &gf100_gr_gpccs_ucode,
1788
}.base;