sh_eth.c 44.2 KB
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/*
 *  SuperH Ethernet device driver
 *
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 *  Copyright (C) 2006-2008 Nobuhiro Iwamatsu
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 *  Copyright (C) 2008-2009 Renesas Solutions Corp.
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 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc.,
 *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/mdio-bitbang.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <linux/cache.h>
#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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Nobuhiro Iwamatsu 已提交
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#include <asm/cacheflush.h>
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#include "sh_eth.h"

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#define SH_ETH_DEF_MSG_ENABLE \
		(NETIF_MSG_LINK	| \
		NETIF_MSG_TIMER	| \
		NETIF_MSG_RX_ERR| \
		NETIF_MSG_TX_ERR)

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/* There is CPU dependent code */
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#if defined(CONFIG_CPU_SUBTYPE_SH7724)
#define SH_ETH_RESET_DEFAULT	1
static void sh_eth_set_duplex(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

static void sh_eth_set_rate(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
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		break;
	default:
		break;
	}
}

/* SH7724 */
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate,

	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
			  EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
	.tx_error_check	= EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
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	.rpadir		= 1,
	.rpadir_value	= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
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};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
#define SH_ETH_RESET_DEFAULT	1
static void sh_eth_set_duplex(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

static void sh_eth_set_rate(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, 0, RTRATE);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, 1, RTRATE);
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		break;
	default:
		break;
	}
}

/* SH7757 */
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.set_duplex		= sh_eth_set_duplex,
	.set_rate		= sh_eth_set_rate,

	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
	.rmcr_value	= 0x00000001,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
			  EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
	.tx_error_check	= EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.no_ade		= 1,
};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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#define SH_ETH_HAS_TSU	1
static void sh_eth_chip_reset(struct net_device *ndev)
{
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	struct sh_eth_private *mdp = netdev_priv(ndev);

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	/* reset device */
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	sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
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	mdelay(1);
}

static void sh_eth_reset(struct net_device *ndev)
{
	int cnt = 100;

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	sh_eth_write(ndev, EDSR_ENALL, EDSR);
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	sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
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	while (cnt > 0) {
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		if (!(sh_eth_read(ndev, EDMR) & 0x3))
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			break;
		mdelay(1);
		cnt--;
	}
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	if (cnt == 0)
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		printk(KERN_ERR "Device reset fail\n");

	/* Table Init */
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	sh_eth_write(ndev, 0x0, TDLAR);
	sh_eth_write(ndev, 0x0, TDFAR);
	sh_eth_write(ndev, 0x0, TDFXR);
	sh_eth_write(ndev, 0x0, TDFFR);
	sh_eth_write(ndev, 0x0, RDLAR);
	sh_eth_write(ndev, 0x0, RDFAR);
	sh_eth_write(ndev, 0x0, RDFXR);
	sh_eth_write(ndev, 0x0, RDFFR);
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}

static void sh_eth_set_duplex(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

static void sh_eth_set_rate(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, GECMR_10, GECMR);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, GECMR_100, GECMR);
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		break;
	case 1000: /* 1000BASE */
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		sh_eth_write(ndev, GECMR_1000, GECMR);
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		break;
	default:
		break;
	}
}

/* sh7763 */
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate,

	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
			  EESR_ECI,
	.tx_error_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
			  EESR_TFE,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
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	.tsu		= 1,
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};

#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
#define SH_ETH_RESET_DEFAULT	1
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
#define SH_ETH_RESET_DEFAULT	1
#define SH_ETH_HAS_TSU	1
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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	.tsu		= 1,
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};
#endif

static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
{
	if (!cd->ecsr_value)
		cd->ecsr_value = DEFAULT_ECSR_INIT;

	if (!cd->ecsipr_value)
		cd->ecsipr_value = DEFAULT_ECSIPR_INIT;

	if (!cd->fcftr_value)
		cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
				  DEFAULT_FIFO_F_D_RFD;

	if (!cd->fdr_value)
		cd->fdr_value = DEFAULT_FDR_INIT;

	if (!cd->rmcr_value)
		cd->rmcr_value = DEFAULT_RMCR_VALUE;

	if (!cd->tx_check)
		cd->tx_check = DEFAULT_TX_CHECK;

	if (!cd->eesr_err_check)
		cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;

	if (!cd->tx_error_check)
		cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
}

#if defined(SH_ETH_RESET_DEFAULT)
/* Chip Reset */
static void sh_eth_reset(struct net_device *ndev)
{
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	sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
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	mdelay(3);
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	sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
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}
#endif

#if defined(CONFIG_CPU_SH4)
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	int reserve;

	reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
	if (reserve)
		skb_reserve(skb, reserve);
}
#else
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
}
#endif


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/* CPU <-> EDMAC endian convert */
static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return cpu_to_le32(x);
	case EDMAC_BIG_ENDIAN:
		return cpu_to_be32(x);
	}
	return x;
}

static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return le32_to_cpu(x);
	case EDMAC_BIG_ENDIAN:
		return be32_to_cpu(x);
	}
	return x;
}

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/*
 * Program the hardware MAC address from dev->dev_addr.
 */
static void update_mac_address(struct net_device *ndev)
{
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	sh_eth_write(ndev,
		(ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
		(ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
	sh_eth_write(ndev,
		(ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
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}

/*
 * Get MAC address from SuperH MAC address register
 *
 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 * When you want use this device, you must set MAC address in bootloader.
 *
 */
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static void read_mac_address(struct net_device *ndev, unsigned char *mac)
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{
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	if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
		memcpy(ndev->dev_addr, mac, 6);
	} else {
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		ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
		ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
		ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
		ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
		ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
		ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
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	}
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}

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static int sh_eth_is_gether(struct sh_eth_private *mdp)
{
	if (mdp->reg_offset == sh_eth_offset_gigabit)
		return 1;
	else
		return 0;
}

static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
{
	if (sh_eth_is_gether(mdp))
		return EDTRR_TRNS_GETHER;
	else
		return EDTRR_TRNS_ETHER;
}

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struct bb_info {
	struct mdiobb_ctrl ctrl;
	u32 addr;
	u32 mmd_msk;/* MMD */
	u32 mdo_msk;
	u32 mdi_msk;
	u32 mdc_msk;
};

/* PHY bit set */
static void bb_set(u32 addr, u32 msk)
{
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	writel(readl(addr) | msk, addr);
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}

/* PHY bit clear */
static void bb_clr(u32 addr, u32 msk)
{
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	writel((readl(addr) & ~msk), addr);
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}

/* PHY bit read */
static int bb_read(u32 addr, u32 msk)
{
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	return (readl(addr) & msk) != 0;
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}

/* Data I/O pin control */
static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
	if (bit)
		bb_set(bitbang->addr, bitbang->mmd_msk);
	else
		bb_clr(bitbang->addr, bitbang->mmd_msk);
}

/* Set bit data*/
static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

	if (bit)
		bb_set(bitbang->addr, bitbang->mdo_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdo_msk);
}

/* Get bit data*/
static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
	return bb_read(bitbang->addr, bitbang->mdi_msk);
}

/* MDC pin control */
static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

	if (bit)
		bb_set(bitbang->addr, bitbang->mdc_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdc_msk);
}

/* mdio bus control struct */
static struct mdiobb_ops bb_ops = {
	.owner = THIS_MODULE,
	.set_mdc = sh_mdc_ctrl,
	.set_mdio_dir = sh_mmd_ctrl,
	.set_mdio_data = sh_set_mdio,
	.get_mdio_data = sh_get_mdio,
};

/* free skb and descriptor buffer */
static void sh_eth_ring_free(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;

	/* Free Rx skb ringbuffer */
	if (mdp->rx_skbuff) {
		for (i = 0; i < RX_RING_SIZE; i++) {
			if (mdp->rx_skbuff[i])
				dev_kfree_skb(mdp->rx_skbuff[i]);
		}
	}
	kfree(mdp->rx_skbuff);

	/* Free Tx skb ringbuffer */
	if (mdp->tx_skbuff) {
		for (i = 0; i < TX_RING_SIZE; i++) {
			if (mdp->tx_skbuff[i])
				dev_kfree_skb(mdp->tx_skbuff[i]);
		}
	}
	kfree(mdp->tx_skbuff);
}

/* format skb and descriptor buffer */
static void sh_eth_ring_format(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;
	struct sk_buff *skb;
	struct sh_eth_rxdesc *rxdesc = NULL;
	struct sh_eth_txdesc *txdesc = NULL;
	int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
	int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;

	mdp->cur_rx = mdp->cur_tx = 0;
	mdp->dirty_rx = mdp->dirty_tx = 0;

	memset(mdp->rx_ring, 0, rx_ringsize);

	/* build Rx ring buffer */
	for (i = 0; i < RX_RING_SIZE; i++) {
		/* skb */
		mdp->rx_skbuff[i] = NULL;
		skb = dev_alloc_skb(mdp->rx_buf_sz);
		mdp->rx_skbuff[i] = skb;
		if (skb == NULL)
			break;
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		dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
				DMA_FROM_DEVICE);
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		skb->dev = ndev; /* Mark as being used by this device. */
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		sh_eth_set_receive_align(skb);

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		/* RX descriptor */
		rxdesc = &mdp->rx_ring[i];
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		rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
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		rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
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		/* The size of the buffer is 16 byte boundary. */
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		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
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		/* Rx descriptor address set */
		if (i == 0) {
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			sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
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			if (sh_eth_is_gether(mdp))
				sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
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		}
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	}

	mdp->dirty_rx = (u32) (i - RX_RING_SIZE);

	/* Mark the last entry as wrapping the ring. */
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	rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
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	memset(mdp->tx_ring, 0, tx_ringsize);

	/* build Tx ring buffer */
	for (i = 0; i < TX_RING_SIZE; i++) {
		mdp->tx_skbuff[i] = NULL;
		txdesc = &mdp->tx_ring[i];
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		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
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		txdesc->buffer_length = 0;
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		if (i == 0) {
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			/* Tx descriptor address set */
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			sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
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			if (sh_eth_is_gether(mdp))
				sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
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		}
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	}

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	txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
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}

/* Get skb and descriptor buffer */
static int sh_eth_ring_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int rx_ringsize, tx_ringsize, ret = 0;

	/*
	 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
	 * card needs room to do 8 byte alignment, +2 so we can reserve
	 * the first 2 bytes, and +16 gets room for the status word from the
	 * card.
	 */
	mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
			  (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
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	if (mdp->cd->rpadir)
		mdp->rx_buf_sz += NET_IP_ALIGN;
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	/* Allocate RX and TX skb rings */
	mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
				GFP_KERNEL);
	if (!mdp->rx_skbuff) {
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		dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
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		ret = -ENOMEM;
		return ret;
	}

	mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
				GFP_KERNEL);
	if (!mdp->tx_skbuff) {
581
		dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
582 583 584 585 586 587 588 589 590 591
		ret = -ENOMEM;
		goto skb_ring_free;
	}

	/* Allocate all Rx descriptors. */
	rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
	mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
			GFP_KERNEL);

	if (!mdp->rx_ring) {
592 593
		dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
			rx_ringsize);
594 595 596 597 598 599 600 601 602 603 604
		ret = -ENOMEM;
		goto desc_ring_free;
	}

	mdp->dirty_rx = 0;

	/* Allocate all Tx descriptors. */
	tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
	mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
			GFP_KERNEL);
	if (!mdp->tx_ring) {
605 606
		dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
			tx_ringsize);
607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632
		ret = -ENOMEM;
		goto desc_ring_free;
	}
	return ret;

desc_ring_free:
	/* free DMA buffer */
	dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);

skb_ring_free:
	/* Free Rx and Tx skb ring buffer */
	sh_eth_ring_free(ndev);

	return ret;
}

static int sh_eth_dev_init(struct net_device *ndev)
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u_int32_t rx_int_var, tx_int_var;
	u32 val;

	/* Soft Reset */
	sh_eth_reset(ndev);

633 634
	/* Descriptor format */
	sh_eth_ring_format(ndev);
635
	if (mdp->cd->rpadir)
636
		sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
637 638

	/* all sh_eth int mask */
639
	sh_eth_write(ndev, 0, EESIPR);
640

641 642
#if defined(__LITTLE_ENDIAN__)
	if (mdp->cd->hw_swap)
643
		sh_eth_write(ndev, EDMR_EL, EDMR);
644
	else
645
#endif
646
		sh_eth_write(ndev, 0, EDMR);
647

648
	/* FIFO size set */
649 650
	sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
	sh_eth_write(ndev, 0, TFTR);
651

652
	/* Frame recv control */
653
	sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
654 655 656

	rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
	tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
657
	sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
658

659
	if (mdp->cd->bculr)
660
		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
661

662
	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
663

664
	if (!mdp->cd->no_trimd)
665
		sh_eth_write(ndev, 0, TRIMD);
666

667
	/* Recv frame limit set register */
668
	sh_eth_write(ndev, RFLR_VALUE, RFLR);
669

670 671
	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
672 673

	/* PAUSE Prohibition */
674
	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
675 676
		ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;

677
	sh_eth_write(ndev, val, ECMR);
678

679 680 681
	if (mdp->cd->set_rate)
		mdp->cd->set_rate(ndev);

682
	/* E-MAC Status Register clear */
683
	sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
684 685

	/* E-MAC Interrupt Enable register */
686
	sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
687 688 689 690 691

	/* Set MAC address */
	update_mac_address(ndev);

	/* mask reset */
692
	if (mdp->cd->apr)
693
		sh_eth_write(ndev, APR_AP, APR);
694
	if (mdp->cd->mpr)
695
		sh_eth_write(ndev, MPR_MP, MPR);
696
	if (mdp->cd->tpauser)
697
		sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
698

699
	/* Setting the Rx mode will start the Rx process. */
700
	sh_eth_write(ndev, EDRRR_R, EDRRR);
701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717

	netif_start_queue(ndev);

	return ret;
}

/* free Tx skb function */
static int sh_eth_txfree(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
	int freeNum = 0;
	int entry = 0;

	for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
		entry = mdp->dirty_tx % TX_RING_SIZE;
		txdesc = &mdp->tx_ring[entry];
718
		if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
719 720 721 722 723 724 725
			break;
		/* Free the original skb. */
		if (mdp->tx_skbuff[entry]) {
			dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
			mdp->tx_skbuff[entry] = NULL;
			freeNum++;
		}
726
		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
727
		if (entry >= TX_RING_SIZE - 1)
728
			txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745

		mdp->stats.tx_packets++;
		mdp->stats.tx_bytes += txdesc->buffer_length;
	}
	return freeNum;
}

/* Packet receive function */
static int sh_eth_rx(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;

	int entry = mdp->cur_rx % RX_RING_SIZE;
	int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
	struct sk_buff *skb;
	u16 pkt_len = 0;
746
	u32 desc_status;
747 748

	rxdesc = &mdp->rx_ring[entry];
749 750
	while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
		desc_status = edmac_to_cpu(mdp, rxdesc->status);
751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774
		pkt_len = rxdesc->frame_length;

		if (--boguscnt < 0)
			break;

		if (!(desc_status & RDFEND))
			mdp->stats.rx_length_errors++;

		if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
				   RD_RFS5 | RD_RFS6 | RD_RFS10)) {
			mdp->stats.rx_errors++;
			if (desc_status & RD_RFS1)
				mdp->stats.rx_crc_errors++;
			if (desc_status & RD_RFS2)
				mdp->stats.rx_frame_errors++;
			if (desc_status & RD_RFS3)
				mdp->stats.rx_length_errors++;
			if (desc_status & RD_RFS4)
				mdp->stats.rx_length_errors++;
			if (desc_status & RD_RFS6)
				mdp->stats.rx_missed_errors++;
			if (desc_status & RD_RFS10)
				mdp->stats.rx_over_errors++;
		} else {
775 776 777 778
			if (!mdp->cd->hw_swap)
				sh_eth_soft_swap(
					phys_to_virt(ALIGN(rxdesc->addr, 4)),
					pkt_len + 2);
779 780
			skb = mdp->rx_skbuff[entry];
			mdp->rx_skbuff[entry] = NULL;
781 782
			if (mdp->cd->rpadir)
				skb_reserve(skb, NET_IP_ALIGN);
783 784 785 786 787 788
			skb_put(skb, pkt_len);
			skb->protocol = eth_type_trans(skb, ndev);
			netif_rx(skb);
			mdp->stats.rx_packets++;
			mdp->stats.rx_bytes += pkt_len;
		}
789
		rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
790
		entry = (++mdp->cur_rx) % RX_RING_SIZE;
791
		rxdesc = &mdp->rx_ring[entry];
792 793 794 795 796 797
	}

	/* Refill the Rx ring buffers. */
	for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
		entry = mdp->dirty_rx % RX_RING_SIZE;
		rxdesc = &mdp->rx_ring[entry];
798
		/* The size of the buffer is 16 byte boundary. */
799
		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
800

801 802 803 804 805
		if (mdp->rx_skbuff[entry] == NULL) {
			skb = dev_alloc_skb(mdp->rx_buf_sz);
			mdp->rx_skbuff[entry] = skb;
			if (skb == NULL)
				break;	/* Better luck next round. */
806 807
			dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
					DMA_FROM_DEVICE);
808
			skb->dev = ndev;
809 810
			sh_eth_set_receive_align(skb);

811
			skb_checksum_none_assert(skb);
812
			rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
813 814 815
		}
		if (entry >= RX_RING_SIZE - 1)
			rxdesc->status |=
816
				cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
817 818
		else
			rxdesc->status |=
819
				cpu_to_edmac(mdp, RD_RACT | RD_RFP);
820 821 822 823
	}

	/* Restart Rx engine if stopped. */
	/* If we don't need to check status, don't. -KDU */
824 825
	if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
		sh_eth_write(ndev, EDRRR_R, EDRRR);
826 827 828 829

	return 0;
}

830
static void sh_eth_rcv_snd_disable(struct net_device *ndev)
831 832
{
	/* disable tx and rx */
833 834
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
		~(ECMR_RE | ECMR_TE), ECMR);
835 836
}

837
static void sh_eth_rcv_snd_enable(struct net_device *ndev)
838 839
{
	/* enable tx and rx */
840 841
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
		(ECMR_RE | ECMR_TE), ECMR);
842 843
}

844 845 846 847 848
/* error control function */
static void sh_eth_error(struct net_device *ndev, int intr_status)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 felic_stat;
849 850
	u32 link_stat;
	u32 mask;
851 852

	if (intr_status & EESR_ECI) {
853 854
		felic_stat = sh_eth_read(ndev, ECSR);
		sh_eth_write(ndev, felic_stat, ECSR);	/* clear int */
855 856 857 858
		if (felic_stat & ECSR_ICD)
			mdp->stats.tx_carrier_errors++;
		if (felic_stat & ECSR_LCHNG) {
			/* Link Changed */
859
			if (mdp->cd->no_psr || mdp->no_ether_link) {
860 861 862 863 864
				if (mdp->link == PHY_DOWN)
					link_stat = 0;
				else
					link_stat = PHY_ST_LINK;
			} else {
865
				link_stat = (sh_eth_read(ndev, PSR));
866 867
				if (mdp->ether_link_active_low)
					link_stat = ~link_stat;
868
			}
869
			if (!(link_stat & PHY_ST_LINK))
870
				sh_eth_rcv_snd_disable(ndev);
871
			else {
872
				/* Link Up */
873 874
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
					  ~DMAC_M_ECI, EESIPR);
875
				/*clear int */
876 877 878 879
				sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
					  ECSR);
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
					  DMAC_M_ECI, EESIPR);
880
				/* enable tx and rx */
881
				sh_eth_rcv_snd_enable(ndev);
882 883 884 885 886 887 888 889
			}
		}
	}

	if (intr_status & EESR_TWB) {
		/* Write buck end. unused write back interrupt */
		if (intr_status & EESR_TABT)	/* Transmit Abort int */
			mdp->stats.tx_aborted_errors++;
890 891
			if (netif_msg_tx_err(mdp))
				dev_err(&ndev->dev, "Transmit Abort\n");
892 893 894 895 896 897 898
	}

	if (intr_status & EESR_RABT) {
		/* Receive Abort int */
		if (intr_status & EESR_RFRMER) {
			/* Receive Frame Overflow int */
			mdp->stats.rx_frame_errors++;
899 900
			if (netif_msg_rx_err(mdp))
				dev_err(&ndev->dev, "Receive Abort\n");
901 902
		}
	}
903

904 905 906 907 908 909 910 911 912 913 914 915
	if (intr_status & EESR_TDE) {
		/* Transmit Descriptor Empty int */
		mdp->stats.tx_fifo_errors++;
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
	}

	if (intr_status & EESR_TFE) {
		/* FIFO under flow */
		mdp->stats.tx_fifo_errors++;
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
916 917 918 919 920 921
	}

	if (intr_status & EESR_RDE) {
		/* Receive Descriptor Empty int */
		mdp->stats.rx_over_errors++;

922 923
		if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
			sh_eth_write(ndev, EDRRR_R, EDRRR);
924 925
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive Descriptor Empty\n");
926
	}
927

928 929 930
	if (intr_status & EESR_RFE) {
		/* Receive FIFO Overflow int */
		mdp->stats.rx_fifo_errors++;
931 932 933 934 935 936 937 938 939
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive FIFO Overflow\n");
	}

	if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
		/* Address Error */
		mdp->stats.tx_fifo_errors++;
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Address Error\n");
940
	}
941 942 943 944 945

	mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
	if (mdp->cd->no_ade)
		mask &= ~EESR_ADE;
	if (intr_status & mask) {
946
		/* Tx error */
947
		u32 edtrr = sh_eth_read(ndev, EDTRR);
948
		/* dmesg */
949 950 951
		dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
				intr_status, mdp->cur_tx);
		dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
952 953 954 955 956
				mdp->dirty_tx, (u32) ndev->state, edtrr);
		/* dirty buffer free */
		sh_eth_txfree(ndev);

		/* SH7712 BUG */
957
		if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
958
			/* tx dma start */
959
			sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
960 961 962 963 964 965 966 967 968 969
		}
		/* wakeup */
		netif_wake_queue(ndev);
	}
}

static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
{
	struct net_device *ndev = netdev;
	struct sh_eth_private *mdp = netdev_priv(ndev);
970
	struct sh_eth_cpu_data *cd = mdp->cd;
971
	irqreturn_t ret = IRQ_NONE;
972
	u32 intr_status = 0;
973 974 975

	spin_lock(&mdp->lock);

976
	/* Get interrpt stat */
977
	intr_status = sh_eth_read(ndev, EESR);
978
	/* Clear interrupt */
979 980
	if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
			EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
981
			cd->tx_check | cd->eesr_err_check)) {
982
		sh_eth_write(ndev, intr_status, EESR);
983 984 985
		ret = IRQ_HANDLED;
	} else
		goto other_irq;
986

987 988 989 990 991 992 993
	if (intr_status & (EESR_FRC | /* Frame recv*/
			EESR_RMAF | /* Multi cast address recv*/
			EESR_RRF  | /* Bit frame recv */
			EESR_RTLF | /* Long frame recv*/
			EESR_RTSF | /* short frame recv */
			EESR_PRE  | /* PHY-LSI recv error */
			EESR_CERF)){ /* recv frame CRC error */
994
		sh_eth_rx(ndev);
995
	}
996

997
	/* Tx Check */
998
	if (intr_status & cd->tx_check) {
999 1000 1001 1002
		sh_eth_txfree(ndev);
		netif_wake_queue(ndev);
	}

1003
	if (intr_status & cd->eesr_err_check)
1004 1005
		sh_eth_error(ndev, intr_status);

1006
other_irq:
1007 1008
	spin_unlock(&mdp->lock);

1009
	return ret;
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030
}

static void sh_eth_timer(unsigned long data)
{
	struct net_device *ndev = (struct net_device *)data;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	mod_timer(&mdp->timer, jiffies + (10 * HZ));
}

/* PHY state control function */
static void sh_eth_adjust_link(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;
	int new_state = 0;

	if (phydev->link != PHY_DOWN) {
		if (phydev->duplex != mdp->duplex) {
			new_state = 1;
			mdp->duplex = phydev->duplex;
1031 1032
			if (mdp->cd->set_duplex)
				mdp->cd->set_duplex(ndev);
1033 1034 1035 1036 1037
		}

		if (phydev->speed != mdp->speed) {
			new_state = 1;
			mdp->speed = phydev->speed;
1038 1039
			if (mdp->cd->set_rate)
				mdp->cd->set_rate(ndev);
1040 1041
		}
		if (mdp->link == PHY_DOWN) {
1042 1043
			sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF)
					| ECMR_DM, ECMR);
1044 1045 1046 1047 1048 1049 1050 1051 1052 1053
			new_state = 1;
			mdp->link = phydev->link;
		}
	} else if (mdp->link) {
		new_state = 1;
		mdp->link = PHY_DOWN;
		mdp->speed = 0;
		mdp->duplex = -1;
	}

1054
	if (new_state && netif_msg_link(mdp))
1055 1056 1057 1058 1059 1060 1061
		phy_print_status(phydev);
}

/* PHY init function */
static int sh_eth_phy_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
1062
	char phy_id[MII_BUS_ID_SIZE + 3];
1063 1064
	struct phy_device *phydev = NULL;

1065
	snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1066 1067 1068 1069 1070 1071 1072
		mdp->mii_bus->id , mdp->phy_id);

	mdp->link = PHY_DOWN;
	mdp->speed = 0;
	mdp->duplex = -1;

	/* Try connect to PHY */
1073
	phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1074 1075 1076 1077 1078
				0, PHY_INTERFACE_MODE_MII);
	if (IS_ERR(phydev)) {
		dev_err(&ndev->dev, "phy_connect failed\n");
		return PTR_ERR(phydev);
	}
1079

1080
	dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1081
		phydev->addr, phydev->drv->name);
1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104

	mdp->phydev = phydev;

	return 0;
}

/* PHY control start function */
static int sh_eth_phy_start(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	ret = sh_eth_phy_init(ndev);
	if (ret)
		return ret;

	/* reset phy - this also wakes it from PDOWN */
	phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
	phy_start(mdp->phydev);

	return 0;
}

1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128
static int sh_eth_get_settings(struct net_device *ndev,
			struct ethtool_cmd *ecmd)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_ethtool_gset(mdp->phydev, ecmd);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_set_settings(struct net_device *ndev,
		struct ethtool_cmd *ecmd)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);

	/* disable tx and rx */
1129
	sh_eth_rcv_snd_disable(ndev);
1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146

	ret = phy_ethtool_sset(mdp->phydev, ecmd);
	if (ret)
		goto error_exit;

	if (ecmd->duplex == DUPLEX_FULL)
		mdp->duplex = 1;
	else
		mdp->duplex = 0;

	if (mdp->cd->set_duplex)
		mdp->cd->set_duplex(ndev);

error_exit:
	mdelay(1);

	/* enable tx and rx */
1147
	sh_eth_rcv_snd_enable(ndev);
1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229

	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_nway_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_start_aneg(mdp->phydev);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static u32 sh_eth_get_msglevel(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	return mdp->msg_enable;
}

static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	mdp->msg_enable = value;
}

static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
	"rx_current", "tx_current",
	"rx_dirty", "tx_dirty",
};
#define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)

static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
{
	switch (sset) {
	case ETH_SS_STATS:
		return SH_ETH_STATS_LEN;
	default:
		return -EOPNOTSUPP;
	}
}

static void sh_eth_get_ethtool_stats(struct net_device *ndev,
			struct ethtool_stats *stats, u64 *data)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i = 0;

	/* device-specific stats */
	data[i++] = mdp->cur_rx;
	data[i++] = mdp->cur_tx;
	data[i++] = mdp->dirty_rx;
	data[i++] = mdp->dirty_tx;
}

static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(data, *sh_eth_gstrings_stats,
					sizeof(sh_eth_gstrings_stats));
		break;
	}
}

static struct ethtool_ops sh_eth_ethtool_ops = {
	.get_settings	= sh_eth_get_settings,
	.set_settings	= sh_eth_set_settings,
	.nway_reset		= sh_eth_nway_reset,
	.get_msglevel	= sh_eth_get_msglevel,
	.set_msglevel	= sh_eth_set_msglevel,
	.get_link		= ethtool_op_get_link,
	.get_strings	= sh_eth_get_strings,
	.get_ethtool_stats  = sh_eth_get_ethtool_stats,
	.get_sset_count     = sh_eth_get_sset_count,
};

1230 1231 1232 1233 1234 1235
/* network device open function */
static int sh_eth_open(struct net_device *ndev)
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);

1236 1237
	pm_runtime_get_sync(&mdp->pdev->dev);

1238
	ret = request_irq(ndev->irq, sh_eth_interrupt,
1239
#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1240 1241
	defined(CONFIG_CPU_SUBTYPE_SH7764) || \
	defined(CONFIG_CPU_SUBTYPE_SH7757)
1242 1243 1244 1245 1246
				IRQF_SHARED,
#else
				0,
#endif
				ndev->name, ndev);
1247
	if (ret) {
1248
		dev_err(&ndev->dev, "Can not assign IRQ number\n");
1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269
		return ret;
	}

	/* Descriptor set */
	ret = sh_eth_ring_init(ndev);
	if (ret)
		goto out_free_irq;

	/* device init */
	ret = sh_eth_dev_init(ndev);
	if (ret)
		goto out_free_irq;

	/* PHY control start*/
	ret = sh_eth_phy_start(ndev);
	if (ret)
		goto out_free_irq;

	/* Set the timer to check for link beat. */
	init_timer(&mdp->timer);
	mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1270
	setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1271 1272 1273 1274 1275

	return ret;

out_free_irq:
	free_irq(ndev->irq, ndev);
1276
	pm_runtime_put_sync(&mdp->pdev->dev);
1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288
	return ret;
}

/* Timeout function */
static void sh_eth_tx_timeout(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;
	int i;

	netif_stop_queue(ndev);

1289 1290
	if (netif_msg_timer(mdp))
		dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1291
	       " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327

	/* tx_errors count up */
	mdp->stats.tx_errors++;

	/* timer off */
	del_timer_sync(&mdp->timer);

	/* Free all the skbuffs in the Rx queue. */
	for (i = 0; i < RX_RING_SIZE; i++) {
		rxdesc = &mdp->rx_ring[i];
		rxdesc->status = 0;
		rxdesc->addr = 0xBADF00D0;
		if (mdp->rx_skbuff[i])
			dev_kfree_skb(mdp->rx_skbuff[i]);
		mdp->rx_skbuff[i] = NULL;
	}
	for (i = 0; i < TX_RING_SIZE; i++) {
		if (mdp->tx_skbuff[i])
			dev_kfree_skb(mdp->tx_skbuff[i]);
		mdp->tx_skbuff[i] = NULL;
	}

	/* device init */
	sh_eth_dev_init(ndev);

	/* timer on */
	mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
	add_timer(&mdp->timer);
}

/* Packet transmit function */
static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
	u32 entry;
1328
	unsigned long flags;
1329 1330 1331 1332

	spin_lock_irqsave(&mdp->lock, flags);
	if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
		if (!sh_eth_txfree(ndev)) {
1333 1334
			if (netif_msg_tx_queued(mdp))
				dev_warn(&ndev->dev, "TxFD exhausted.\n");
1335 1336
			netif_stop_queue(ndev);
			spin_unlock_irqrestore(&mdp->lock, flags);
1337
			return NETDEV_TX_BUSY;
1338 1339 1340 1341 1342 1343 1344
		}
	}
	spin_unlock_irqrestore(&mdp->lock, flags);

	entry = mdp->cur_tx % TX_RING_SIZE;
	mdp->tx_skbuff[entry] = skb;
	txdesc = &mdp->tx_ring[entry];
1345
	txdesc->addr = virt_to_phys(skb->data);
1346
	/* soft swap. */
1347 1348 1349
	if (!mdp->cd->hw_swap)
		sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
				 skb->len + 2);
1350 1351 1352 1353 1354 1355 1356 1357
	/* write back */
	__flush_purge_region(skb->data, skb->len);
	if (skb->len < ETHERSMALL)
		txdesc->buffer_length = ETHERSMALL;
	else
		txdesc->buffer_length = skb->len;

	if (entry >= TX_RING_SIZE - 1)
1358
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1359
	else
1360
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1361 1362 1363

	mdp->cur_tx++;

1364 1365
	if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
		sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1366

1367
	return NETDEV_TX_OK;
1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378
}

/* device close function */
static int sh_eth_close(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ringsize;

	netif_stop_queue(ndev);

	/* Disable interrupts by clearing the interrupt mask. */
1379
	sh_eth_write(ndev, 0x0000, EESIPR);
1380 1381

	/* Stop the chip's Tx and Rx processes. */
1382 1383
	sh_eth_write(ndev, 0, EDTRR);
	sh_eth_write(ndev, 0, EDRRR);
1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405

	/* PHY Disconnect */
	if (mdp->phydev) {
		phy_stop(mdp->phydev);
		phy_disconnect(mdp->phydev);
	}

	free_irq(ndev->irq, ndev);

	del_timer_sync(&mdp->timer);

	/* Free all the skbuffs in the Rx queue. */
	sh_eth_ring_free(ndev);

	/* free DMA buffer */
	ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
	dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);

	/* free DMA buffer */
	ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
	dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);

1406 1407
	pm_runtime_put_sync(&mdp->pdev->dev);

1408 1409 1410 1411 1412 1413 1414
	return 0;
}

static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

1415 1416
	pm_runtime_get_sync(&mdp->pdev->dev);

1417 1418 1419 1420 1421 1422
	mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
	sh_eth_write(ndev, 0, TROCR);	/* (write clear) */
	mdp->stats.collisions += sh_eth_read(ndev, CDCR);
	sh_eth_write(ndev, 0, CDCR);	/* (write clear) */
	mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
	sh_eth_write(ndev, 0, LCCR);	/* (write clear) */
1423 1424 1425 1426 1427 1428 1429 1430 1431
	if (sh_eth_is_gether(mdp)) {
		mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
		sh_eth_write(ndev, 0, CERCR);	/* (write clear) */
		mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
		sh_eth_write(ndev, 0, CEECR);	/* (write clear) */
	} else {
		mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
		sh_eth_write(ndev, 0, CNDCR);	/* (write clear) */
	}
1432 1433
	pm_runtime_put_sync(&mdp->pdev->dev);

1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449
	return &mdp->stats;
}

/* ioctl to device funciotn*/
static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
				int cmd)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;

	if (!netif_running(ndev))
		return -EINVAL;

	if (!phydev)
		return -ENODEV;

1450
	return phy_mii_ioctl(phydev, rq, cmd);
1451 1452
}

1453
#if defined(SH_ETH_HAS_TSU)
1454 1455 1456 1457 1458
/* Multicast reception directions set */
static void sh_eth_set_multicast_list(struct net_device *ndev)
{
	if (ndev->flags & IFF_PROMISC) {
		/* Set promiscuous. */
1459 1460
		sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
				ECMR_PRM, ECMR);
1461 1462
	} else {
		/* Normal, unicast/broadcast-only mode. */
1463 1464
		sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
				ECMR_MCT, ECMR);
1465 1466
	}
}
1467
#endif /* SH_ETH_HAS_TSU */
1468 1469

/* SuperH's TSU register init function */
1470
static void sh_eth_tsu_init(struct sh_eth_private *mdp)
1471
{
1472 1473 1474 1475 1476 1477 1478 1479 1480 1481
	sh_eth_tsu_write(mdp, 0, TSU_FWEN0);	/* Disable forward(0->1) */
	sh_eth_tsu_write(mdp, 0, TSU_FWEN1);	/* Disable forward(1->0) */
	sh_eth_tsu_write(mdp, 0, TSU_FCM);	/* forward fifo 3k-3k */
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
	sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
1482 1483 1484 1485 1486 1487 1488
	if (sh_eth_is_gether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_QTAG0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAG1);	/* Disable QTAG(1->0) */
	} else {
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);	/* Disable QTAG(1->0) */
	}
1489 1490 1491 1492 1493 1494 1495
	sh_eth_tsu_write(mdp, 0, TSU_FWSR);	/* all interrupt status clear */
	sh_eth_tsu_write(mdp, 0, TSU_FWINMK);	/* Disable all interrupt */
	sh_eth_tsu_write(mdp, 0, TSU_TEN);	/* Disable all CAM entry */
	sh_eth_tsu_write(mdp, 0, TSU_POST1);	/* Disable CAM entry [ 0- 7] */
	sh_eth_tsu_write(mdp, 0, TSU_POST2);	/* Disable CAM entry [ 8-15] */
	sh_eth_tsu_write(mdp, 0, TSU_POST3);	/* Disable CAM entry [16-23] */
	sh_eth_tsu_write(mdp, 0, TSU_POST4);	/* Disable CAM entry [24-31] */
1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508
}

/* MDIO bus release function */
static int sh_mdio_release(struct net_device *ndev)
{
	struct mii_bus *bus = dev_get_drvdata(&ndev->dev);

	/* unregister mdio bus */
	mdiobus_unregister(bus);

	/* remove mdio bus info from net_device */
	dev_set_drvdata(&ndev->dev, NULL);

1509 1510 1511
	/* free interrupts memory */
	kfree(bus->irq);

1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532
	/* free bitbang info */
	free_mdio_bitbang(bus);

	return 0;
}

/* MDIO bus init function */
static int sh_mdio_init(struct net_device *ndev, int id)
{
	int ret, i;
	struct bb_info *bitbang;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* create bit control struct for PHY */
	bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
	if (!bitbang) {
		ret = -ENOMEM;
		goto out;
	}

	/* bitbang init */
1533
	bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
1534 1535 1536 1537 1538 1539
	bitbang->mdi_msk = 0x08;
	bitbang->mdo_msk = 0x04;
	bitbang->mmd_msk = 0x02;/* MMD */
	bitbang->mdc_msk = 0x01;
	bitbang->ctrl.ops = &bb_ops;

1540
	/* MII controller setting */
1541 1542 1543 1544 1545 1546 1547 1548
	mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
	if (!mdp->mii_bus) {
		ret = -ENOMEM;
		goto out_free_bitbang;
	}

	/* Hook up MII support for ethtool */
	mdp->mii_bus->name = "sh_mii";
1549
	mdp->mii_bus->parent = &ndev->dev;
1550
	snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574

	/* PHY IRQ */
	mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
	if (!mdp->mii_bus->irq) {
		ret = -ENOMEM;
		goto out_free_bus;
	}

	for (i = 0; i < PHY_MAX_ADDR; i++)
		mdp->mii_bus->irq[i] = PHY_POLL;

	/* regist mdio bus */
	ret = mdiobus_register(mdp->mii_bus);
	if (ret)
		goto out_free_irq;

	dev_set_drvdata(&ndev->dev, mdp->mii_bus);

	return 0;

out_free_irq:
	kfree(mdp->mii_bus->irq);

out_free_bus:
1575
	free_mdio_bitbang(mdp->mii_bus);
1576 1577 1578 1579 1580 1581 1582 1583

out_free_bitbang:
	kfree(bitbang);

out:
	return ret;
}

1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605
static const u16 *sh_eth_get_register_offset(int register_type)
{
	const u16 *reg_offset = NULL;

	switch (register_type) {
	case SH_ETH_REG_GIGABIT:
		reg_offset = sh_eth_offset_gigabit;
		break;
	case SH_ETH_REG_FAST_SH4:
		reg_offset = sh_eth_offset_fast_sh4;
		break;
	case SH_ETH_REG_FAST_SH3_SH2:
		reg_offset = sh_eth_offset_fast_sh3_sh2;
		break;
	default:
		printk(KERN_ERR "Unknown register type (%d)\n", register_type);
		break;
	}

	return reg_offset;
}

1606 1607 1608 1609 1610
static const struct net_device_ops sh_eth_netdev_ops = {
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
1611
#if defined(SH_ETH_HAS_TSU)
1612
	.ndo_set_multicast_list	= sh_eth_set_multicast_list,
1613
#endif
1614 1615 1616 1617 1618 1619 1620
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
	.ndo_change_mtu		= eth_change_mtu,
};

1621 1622
static int sh_eth_drv_probe(struct platform_device *pdev)
{
1623
	int ret, devno = 0;
1624 1625 1626
	struct resource *res;
	struct net_device *ndev = NULL;
	struct sh_eth_private *mdp;
1627
	struct sh_eth_plat_data *pd;
1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638

	/* get base addr */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(res == NULL)) {
		dev_err(&pdev->dev, "invalid resource\n");
		ret = -EINVAL;
		goto out;
	}

	ndev = alloc_etherdev(sizeof(struct sh_eth_private));
	if (!ndev) {
1639
		dev_err(&pdev->dev, "Could not allocate device.\n");
1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650
		ret = -ENOMEM;
		goto out;
	}

	/* The sh Ether-specific entries in the device structure. */
	ndev->base_addr = res->start;
	devno = pdev->id;
	if (devno < 0)
		devno = 0;

	ndev->dma = -1;
1651 1652
	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
1653 1654 1655
		ret = -ENODEV;
		goto out_release;
	}
1656
	ndev->irq = ret;
1657 1658 1659 1660 1661 1662 1663 1664

	SET_NETDEV_DEV(ndev, &pdev->dev);

	/* Fill in the fields of the device structure with ethernet values. */
	ether_setup(ndev);

	mdp = netdev_priv(ndev);
	spin_lock_init(&mdp->lock);
1665 1666 1667
	mdp->pdev = pdev;
	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);
1668

1669
	pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1670
	/* get PHY ID */
1671 1672 1673
	mdp->phy_id = pd->phy;
	/* EDMAC endian */
	mdp->edmac_endian = pd->edmac_endian;
1674 1675
	mdp->no_ether_link = pd->no_ether_link;
	mdp->ether_link_active_low = pd->ether_link_active_low;
1676
	mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
1677

1678 1679 1680 1681
	/* set cpu data */
	mdp->cd = &sh_eth_my_cpu_data;
	sh_eth_set_default_cpu_data(mdp->cd);

1682
	/* set function */
1683
	ndev->netdev_ops = &sh_eth_netdev_ops;
1684
	SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1685 1686
	ndev->watchdog_timeo = TX_TIMEOUT;

1687 1688
	/* debug message level */
	mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1689 1690 1691 1692
	mdp->post_rx = POST_RX >> (devno << 1);
	mdp->post_fw = POST_FW >> (devno << 1);

	/* read and set MAC address */
1693
	read_mac_address(ndev, pd->mac_addr);
1694 1695 1696

	/* First device only init */
	if (!devno) {
1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
		if (mdp->cd->tsu) {
			struct resource *rtsu;
			rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
			if (!rtsu) {
				dev_err(&pdev->dev, "Not found TSU resource\n");
				goto out_release;
			}
			mdp->tsu_addr = ioremap(rtsu->start,
						resource_size(rtsu));
		}
1707 1708
		if (mdp->cd->chip_reset)
			mdp->cd->chip_reset(ndev);
1709

1710 1711 1712 1713
		if (mdp->cd->tsu) {
			/* TSU init (Init only)*/
			sh_eth_tsu_init(mdp);
		}
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
	}

	/* network device register */
	ret = register_netdev(ndev);
	if (ret)
		goto out_release;

	/* mdio bus init */
	ret = sh_mdio_init(ndev, pdev->id);
	if (ret)
		goto out_unregister;

1726 1727 1728
	/* print device infomation */
	pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
	       (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1729 1730 1731 1732 1733 1734 1735 1736 1737 1738

	platform_set_drvdata(pdev, ndev);

	return ret;

out_unregister:
	unregister_netdev(ndev);

out_release:
	/* net_dev free */
1739 1740
	if (mdp->tsu_addr)
		iounmap(mdp->tsu_addr);
1741 1742 1743 1744 1745 1746 1747 1748 1749 1750
	if (ndev)
		free_netdev(ndev);

out:
	return ret;
}

static int sh_eth_drv_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
1751
	struct sh_eth_private *mdp = netdev_priv(ndev);
1752

1753
	iounmap(mdp->tsu_addr);
1754 1755
	sh_mdio_release(ndev);
	unregister_netdev(ndev);
1756
	pm_runtime_disable(&pdev->dev);
1757 1758 1759 1760 1761 1762
	free_netdev(ndev);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780
static int sh_eth_runtime_nop(struct device *dev)
{
	/*
	 * Runtime PM callback shared between ->runtime_suspend()
	 * and ->runtime_resume(). Simply returns success.
	 *
	 * This driver re-initializes all registers after
	 * pm_runtime_get_sync() anyway so there is no need
	 * to save and restore registers here.
	 */
	return 0;
}

static struct dev_pm_ops sh_eth_dev_pm_ops = {
	.runtime_suspend = sh_eth_runtime_nop,
	.runtime_resume = sh_eth_runtime_nop,
};

1781 1782 1783 1784 1785
static struct platform_driver sh_eth_driver = {
	.probe = sh_eth_drv_probe,
	.remove = sh_eth_drv_remove,
	.driver = {
		   .name = CARDNAME,
1786
		   .pm = &sh_eth_dev_pm_ops,
1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805
	},
};

static int __init sh_eth_init(void)
{
	return platform_driver_register(&sh_eth_driver);
}

static void __exit sh_eth_cleanup(void)
{
	platform_driver_unregister(&sh_eth_driver);
}

module_init(sh_eth_init);
module_exit(sh_eth_cleanup);

MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
MODULE_LICENSE("GPL v2");