xhci-hub.c 35.5 KB
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/*
 * xHCI host controller driver
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

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#include <linux/slab.h>
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#include <asm/unaligned.h>

#include "xhci.h"
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#include "xhci-trace.h"
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#define	PORT_WAKE_BITS	(PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
#define	PORT_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
			 PORT_RC | PORT_PLC | PORT_PE)

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/* USB 3.0 BOS descriptor and a capability descriptor, combined */
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static u8 usb_bos_descriptor [] = {
	USB_DT_BOS_SIZE,		/*  __u8 bLength, 5 bytes */
	USB_DT_BOS,			/*  __u8 bDescriptorType */
	0x0F, 0x00,			/*  __le16 wTotalLength, 15 bytes */
	0x1,				/*  __u8 bNumDeviceCaps */
	/* First device capability */
	USB_DT_USB_SS_CAP_SIZE,		/*  __u8 bLength, 10 bytes */
	USB_DT_DEVICE_CAPABILITY,	/* Device Capability */
	USB_SS_CAP_TYPE,		/* bDevCapabilityType, SUPERSPEED_USB */
	0x00,				/* bmAttributes, LTM off by default */
	USB_5GBPS_OPERATION, 0x00,	/* wSpeedsSupported, 5Gbps only */
	0x03,				/* bFunctionalitySupport,
					   USB 3.0 speed only */
	0x00,				/* bU1DevExitLat, set later. */
	0x00, 0x00			/* __le16 bU2DevExitLat, set later. */
};


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static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
		struct usb_hub_descriptor *desc, int ports)
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{
	u16 temp;

	desc->bPwrOn2PwrGood = 10;	/* xhci section 5.4.9 says 20ms max */
	desc->bHubContrCurrent = 0;

	desc->bNbrPorts = ports;
	temp = 0;
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	/* Bits 1:0 - support per-port power switching, or power always on */
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	if (HCC_PPC(xhci->hcc_params))
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		temp |= HUB_CHAR_INDV_PORT_LPSM;
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	else
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		temp |= HUB_CHAR_NO_LPSM;
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	/* Bit  2 - root hubs are not part of a compound device */
	/* Bits 4:3 - individual port over current protection */
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	temp |= HUB_CHAR_INDV_PORT_OCPM;
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	/* Bits 6:5 - no TTs in root ports */
	/* Bit  7 - no port indicators */
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	desc->wHubCharacteristics = cpu_to_le16(temp);
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}

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/* Fill in the USB 2.0 roothub descriptor */
static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
		struct usb_hub_descriptor *desc)
{
	int ports;
	u16 temp;
	__u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
	u32 portsc;
	unsigned int i;

	ports = xhci->num_usb2_ports;

	xhci_common_hub_descriptor(xhci, desc, ports);
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	desc->bDescriptorType = USB_DT_HUB;
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	temp = 1 + (ports / 8);
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	desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
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	/* The Device Removable bits are reported on a byte granularity.
	 * If the port doesn't exist within that byte, the bit is set to 0.
	 */
	memset(port_removable, 0, sizeof(port_removable));
	for (i = 0; i < ports; i++) {
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		portsc = readl(xhci->usb2_ports[i]);
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		/* If a device is removable, PORTSC reports a 0, same as in the
		 * hub descriptor DeviceRemovable bits.
		 */
		if (portsc & PORT_DEV_REMOVE)
			/* This math is hairy because bit 0 of DeviceRemovable
			 * is reserved, and bit 1 is for port 1, etc.
			 */
			port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
	}

	/* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
	 * ports on it.  The USB 2.0 specification says that there are two
	 * variable length fields at the end of the hub descriptor:
	 * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
	 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
	 * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
	 * 0xFF, so we initialize the both arrays (DeviceRemovable and
	 * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
	 * set of ports that actually exist.
	 */
	memset(desc->u.hs.DeviceRemovable, 0xff,
			sizeof(desc->u.hs.DeviceRemovable));
	memset(desc->u.hs.PortPwrCtrlMask, 0xff,
			sizeof(desc->u.hs.PortPwrCtrlMask));

	for (i = 0; i < (ports + 1 + 7) / 8; i++)
		memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
				sizeof(__u8));
}

/* Fill in the USB 3.0 roothub descriptor */
static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
		struct usb_hub_descriptor *desc)
{
	int ports;
	u16 port_removable;
	u32 portsc;
	unsigned int i;

	ports = xhci->num_usb3_ports;
	xhci_common_hub_descriptor(xhci, desc, ports);
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	desc->bDescriptorType = USB_DT_SS_HUB;
	desc->bDescLength = USB_DT_SS_HUB_SIZE;
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	/* header decode latency should be zero for roothubs,
	 * see section 4.23.5.2.
	 */
	desc->u.ss.bHubHdrDecLat = 0;
	desc->u.ss.wHubDelay = 0;

	port_removable = 0;
	/* bit 0 is reserved, bit 1 is for port 1, etc. */
	for (i = 0; i < ports; i++) {
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		portsc = readl(xhci->usb3_ports[i]);
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		if (portsc & PORT_DEV_REMOVE)
			port_removable |= 1 << (i + 1);
	}
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	desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
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}

static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
		struct usb_hub_descriptor *desc)
{

	if (hcd->speed == HCD_USB3)
		xhci_usb3_hub_descriptor(hcd, xhci, desc);
	else
		xhci_usb2_hub_descriptor(hcd, xhci, desc);

}

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static unsigned int xhci_port_speed(unsigned int port_status)
{
	if (DEV_LOWSPEED(port_status))
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		return USB_PORT_STAT_LOW_SPEED;
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	if (DEV_HIGHSPEED(port_status))
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		return USB_PORT_STAT_HIGH_SPEED;
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	/*
	 * FIXME: Yes, we should check for full speed, but the core uses that as
	 * a default in portspeed() in usb/core/hub.c (which is the only place
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	 * USB_PORT_STAT_*_SPEED is used).
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	 */
	return 0;
}

/*
 * These bits are Read Only (RO) and should be saved and written to the
 * registers: 0, 3, 10:13, 30
 * connect status, over-current status, port speed, and device removable.
 * connect status and port speed are also sticky - meaning they're in
 * the AUX well and they aren't changed by a hot, warm, or cold reset.
 */
#define	XHCI_PORT_RO	((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
/*
 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 * bits 5:8, 9, 14:15, 25:27
 * link state, port power, port indicator state, "wake on" enable state
 */
#define XHCI_PORT_RWS	((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
/*
 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 * bit 4 (port reset)
 */
#define	XHCI_PORT_RW1S	((1<<4))
/*
 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 * bits 1, 17, 18, 19, 20, 21, 22, 23
 * port enable/disable, and
 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 * over-current, reset, link state, and L1 change
 */
#define XHCI_PORT_RW1CS	((1<<1) | (0x7f<<17))
/*
 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 * latched in
 */
#define	XHCI_PORT_RW	((1<<16))
/*
 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 * bits 2, 24, 28:31
 */
#define	XHCI_PORT_RZ	((1<<2) | (1<<24) | (0xf<<28))

/*
 * Given a port state, this function returns a value that would result in the
 * port being in the same state, if the value was written to the port status
 * control register.
 * Save Read Only (RO) bits and save read/write bits where
 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 */
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u32 xhci_port_state_to_neutral(u32 state)
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{
	/* Save read-only status and port state */
	return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
}

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/*
 * find slot id based on port number.
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 * @port: The one-based port number from one of the two split roothubs.
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 */
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int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
		u16 port)
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{
	int slot_id;
	int i;
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	enum usb_device_speed speed;
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	slot_id = 0;
	for (i = 0; i < MAX_HC_SLOTS; i++) {
		if (!xhci->devs[i])
			continue;
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		speed = xhci->devs[i]->udev->speed;
		if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
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				&& xhci->devs[i]->fake_port == port) {
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			slot_id = i;
			break;
		}
	}

	return slot_id;
}

/*
 * Stop device
 * It issues stop endpoint command for EP 0 to 30. And wait the last command
 * to complete.
 * suspend will set to 1, if suspend bit need to set in command.
 */
static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
{
	struct xhci_virt_device *virt_dev;
	struct xhci_command *cmd;
	unsigned long flags;
	int ret;
	int i;

	ret = 0;
	virt_dev = xhci->devs[slot_id];
	cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
	if (!cmd) {
		xhci_dbg(xhci, "Couldn't allocate command structure.\n");
		return -ENOMEM;
	}

	spin_lock_irqsave(&xhci->lock, flags);
	for (i = LAST_EP_INDEX; i > 0; i--) {
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		if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
			struct xhci_command *command;
			command = xhci_alloc_command(xhci, false, false,
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						     GFP_NOWAIT);
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			if (!command) {
				spin_unlock_irqrestore(&xhci->lock, flags);
				xhci_free_command(xhci, cmd);
				return -ENOMEM;

			}
			xhci_queue_stop_endpoint(xhci, command, slot_id, i,
						 suspend);
		}
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	}
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	xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
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	xhci_ring_cmd_db(xhci);
	spin_unlock_irqrestore(&xhci->lock, flags);

	/* Wait for last stop endpoint command to finish */
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	wait_for_completion(cmd->completion);

	if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
		xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
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		ret = -ETIME;
	}
	xhci_free_command(xhci, cmd);
	return ret;
}

/*
 * Ring device, it rings the all doorbells unconditionally.
 */
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void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
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{
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	int i, s;
	struct xhci_virt_ep *ep;

	for (i = 0; i < LAST_EP_INDEX + 1; i++) {
		ep = &xhci->devs[slot_id]->eps[i];
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		if (ep->ep_state & EP_HAS_STREAMS) {
			for (s = 1; s < ep->stream_info->num_streams; s++)
				xhci_ring_ep_doorbell(xhci, slot_id, i, s);
		} else if (ep->ring && ep->ring->dequeue) {
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			xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
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		}
	}
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	return;
}

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static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
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		u16 wIndex, __le32 __iomem *addr, u32 port_status)
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{
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	/* Don't allow the USB core to disable SuperSpeed ports. */
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	if (hcd->speed == HCD_USB3) {
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		xhci_dbg(xhci, "Ignoring request to disable "
				"SuperSpeed port.\n");
		return;
	}

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	/* Write 1 to disable the port */
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	writel(port_status | PORT_PE, addr);
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	port_status = readl(addr);
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	xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
			wIndex, port_status);
}

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static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
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		u16 wIndex, __le32 __iomem *addr, u32 port_status)
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{
	char *port_change_bit;
	u32 status;

	switch (wValue) {
	case USB_PORT_FEAT_C_RESET:
		status = PORT_RC;
		port_change_bit = "reset";
		break;
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	case USB_PORT_FEAT_C_BH_PORT_RESET:
		status = PORT_WRC;
		port_change_bit = "warm(BH) reset";
		break;
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	case USB_PORT_FEAT_C_CONNECTION:
		status = PORT_CSC;
		port_change_bit = "connect";
		break;
	case USB_PORT_FEAT_C_OVER_CURRENT:
		status = PORT_OCC;
		port_change_bit = "over-current";
		break;
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	case USB_PORT_FEAT_C_ENABLE:
		status = PORT_PEC;
		port_change_bit = "enable/disable";
		break;
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	case USB_PORT_FEAT_C_SUSPEND:
		status = PORT_PLC;
		port_change_bit = "suspend/resume";
		break;
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	case USB_PORT_FEAT_C_PORT_LINK_STATE:
		status = PORT_PLC;
		port_change_bit = "link state";
		break;
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	default:
		/* Should never happen */
		return;
	}
	/* Change bits are all write 1 to clear */
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	writel(port_status | status, addr);
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	port_status = readl(addr);
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	xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
			port_change_bit, wIndex, port_status);
}

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static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
{
	int max_ports;
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);

	if (hcd->speed == HCD_USB3) {
		max_ports = xhci->num_usb3_ports;
		*port_array = xhci->usb3_ports;
	} else {
		max_ports = xhci->num_usb2_ports;
		*port_array = xhci->usb2_ports;
	}

	return max_ports;
}

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void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
				int port_id, u32 link_state)
{
	u32 temp;

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	temp = readl(port_array[port_id]);
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	temp = xhci_port_state_to_neutral(temp);
	temp &= ~PORT_PLS_MASK;
	temp |= PORT_LINK_STROBE | link_state;
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	writel(temp, port_array[port_id]);
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}

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static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
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		__le32 __iomem **port_array, int port_id, u16 wake_mask)
{
	u32 temp;

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	temp = readl(port_array[port_id]);
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	temp = xhci_port_state_to_neutral(temp);

	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
		temp |= PORT_WKCONN_E;
	else
		temp &= ~PORT_WKCONN_E;

	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
		temp |= PORT_WKDISC_E;
	else
		temp &= ~PORT_WKDISC_E;

	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
		temp |= PORT_WKOC_E;
	else
		temp &= ~PORT_WKOC_E;

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	writel(temp, port_array[port_id]);
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}

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/* Test and clear port RWC bit */
void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
				int port_id, u32 port_bit)
{
	u32 temp;

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	temp = readl(port_array[port_id]);
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	if (temp & port_bit) {
		temp = xhci_port_state_to_neutral(temp);
		temp |= port_bit;
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		writel(temp, port_array[port_id]);
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	}
}

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/* Updates Link Status for USB 2.1 port */
static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
{
	if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
		*status |= USB_PORT_STAT_L1;
}

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/* Updates Link Status for super Speed port */
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static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
		u32 *status, u32 status_reg)
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{
	u32 pls = status_reg & PORT_PLS_MASK;

	/* resume state is a xHCI internal state.
	 * Do not report it to usb core.
	 */
	if (pls == XDEV_RESUME)
		return;

	/* When the CAS bit is set then warm reset
	 * should be performed on port
	 */
	if (status_reg & PORT_CAS) {
		/* The CAS bit can be set while the port is
		 * in any link state.
		 * Only roothubs have CAS bit, so we
		 * pretend to be in compliance mode
		 * unless we're already in compliance
		 * or the inactive state.
		 */
		if (pls != USB_SS_PORT_LS_COMP_MOD &&
		    pls != USB_SS_PORT_LS_SS_INACTIVE) {
			pls = USB_SS_PORT_LS_COMP_MOD;
		}
		/* Return also connection bit -
		 * hub state machine resets port
		 * when this bit is set.
		 */
		pls |= USB_PORT_STAT_CONNECTION;
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	} else {
		/*
		 * If CAS bit isn't set but the Port is already at
		 * Compliance Mode, fake a connection so the USB core
		 * notices the Compliance state and resets the port.
		 * This resolves an issue generated by the SN65LVPE502CP
		 * in which sometimes the port enters compliance mode
		 * caused by a delay on the host-device negotiation.
		 */
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		if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
				(pls == USB_SS_PORT_LS_COMP_MOD))
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			pls |= USB_PORT_STAT_CONNECTION;
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	}
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	/* update status field */
	*status |= pls;
}

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/*
 * Function for Compliance Mode Quirk.
 *
 * This Function verifies if all xhc USB3 ports have entered U0, if so,
 * the compliance mode timer is deleted. A port won't enter
 * compliance mode if it has previously entered U0.
 */
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static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
				    u16 wIndex)
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{
	u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
	bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);

	if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
		return;

	if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
		xhci->port_status_u0 |= 1 << wIndex;
		if (xhci->port_status_u0 == all_ports_seen_u0) {
			del_timer_sync(&xhci->comp_mode_recovery_timer);
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			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"All USB3 ports have entered U0 already!");
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"Compliance Mode Recovery Timer Deleted.");
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		}
	}
}

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/*
 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 * 3.0 hubs use.
 *
 * Possible side effects:
 *  - Mark a port as being done with device resume,
 *    and ring the endpoint doorbells.
 *  - Stop the Synopsys redriver Compliance Mode polling.
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 *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
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 */
static u32 xhci_get_port_status(struct usb_hcd *hcd,
		struct xhci_bus_state *bus_state,
		__le32 __iomem **port_array,
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		u16 wIndex, u32 raw_port_status,
		unsigned long flags)
	__releases(&xhci->lock)
	__acquires(&xhci->lock)
571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604
{
	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	u32 status = 0;
	int slot_id;

	/* wPortChange bits */
	if (raw_port_status & PORT_CSC)
		status |= USB_PORT_STAT_C_CONNECTION << 16;
	if (raw_port_status & PORT_PEC)
		status |= USB_PORT_STAT_C_ENABLE << 16;
	if ((raw_port_status & PORT_OCC))
		status |= USB_PORT_STAT_C_OVERCURRENT << 16;
	if ((raw_port_status & PORT_RC))
		status |= USB_PORT_STAT_C_RESET << 16;
	/* USB3.0 only */
	if (hcd->speed == HCD_USB3) {
		if ((raw_port_status & PORT_PLC))
			status |= USB_PORT_STAT_C_LINK_STATE << 16;
		if ((raw_port_status & PORT_WRC))
			status |= USB_PORT_STAT_C_BH_RESET << 16;
	}

	if (hcd->speed != HCD_USB3) {
		if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
				&& (raw_port_status & PORT_POWER))
			status |= USB_PORT_STAT_SUSPEND;
	}
	if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
			!DEV_SUPERSPEED(raw_port_status)) {
		if ((raw_port_status & PORT_RESET) ||
				!(raw_port_status & PORT_PE))
			return 0xffffffff;
		if (time_after_eq(jiffies,
					bus_state->resume_done[wIndex])) {
605 606
			int time_left;

607 608 609 610
			xhci_dbg(xhci, "Resume USB2 port %d\n",
					wIndex + 1);
			bus_state->resume_done[wIndex] = 0;
			clear_bit(wIndex, &bus_state->resuming_ports);
611 612

			set_bit(wIndex, &bus_state->rexit_ports);
613 614
			xhci_set_link_state(xhci, port_array, wIndex,
					XDEV_U0);
615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631

			spin_unlock_irqrestore(&xhci->lock, flags);
			time_left = wait_for_completion_timeout(
					&bus_state->rexit_done[wIndex],
					msecs_to_jiffies(
						XHCI_MAX_REXIT_TIMEOUT));
			spin_lock_irqsave(&xhci->lock, flags);

			if (time_left) {
				slot_id = xhci_find_slot_id_by_port(hcd,
						xhci, wIndex + 1);
				if (!slot_id) {
					xhci_dbg(xhci, "slot_id is zero\n");
					return 0xffffffff;
				}
				xhci_ring_device(xhci, slot_id);
			} else {
632
				int port_status = readl(port_array[wIndex]);
633 634 635 636 637
				xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
						XHCI_MAX_REXIT_TIMEOUT,
						port_status);
				status |= USB_PORT_STAT_SUSPEND;
				clear_bit(wIndex, &bus_state->rexit_ports);
638
			}
639

640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674
			bus_state->port_c_suspend |= 1 << wIndex;
			bus_state->suspended_ports &= ~(1 << wIndex);
		} else {
			/*
			 * The resume has been signaling for less than
			 * 20ms. Report the port status as SUSPEND,
			 * let the usbcore check port status again
			 * and clear resume signaling later.
			 */
			status |= USB_PORT_STAT_SUSPEND;
		}
	}
	if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
			&& (raw_port_status & PORT_POWER)
			&& (bus_state->suspended_ports & (1 << wIndex))) {
		bus_state->suspended_ports &= ~(1 << wIndex);
		if (hcd->speed != HCD_USB3)
			bus_state->port_c_suspend |= 1 << wIndex;
	}
	if (raw_port_status & PORT_CONNECT) {
		status |= USB_PORT_STAT_CONNECTION;
		status |= xhci_port_speed(raw_port_status);
	}
	if (raw_port_status & PORT_PE)
		status |= USB_PORT_STAT_ENABLE;
	if (raw_port_status & PORT_OC)
		status |= USB_PORT_STAT_OVERCURRENT;
	if (raw_port_status & PORT_RESET)
		status |= USB_PORT_STAT_RESET;
	if (raw_port_status & PORT_POWER) {
		if (hcd->speed == HCD_USB3)
			status |= USB_SS_PORT_STAT_POWER;
		else
			status |= USB_PORT_STAT_POWER;
	}
675
	/* Update Port Link State */
676
	if (hcd->speed == HCD_USB3) {
677
		xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
678 679 680 681 682
		/*
		 * Verify if all USB3 Ports Have entered U0 already.
		 * Delete Compliance Mode Timer if so.
		 */
		xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
683 684
	} else {
		xhci_hub_report_usb2_link_state(&status, raw_port_status);
685 686 687 688 689 690 691
	}
	if (bus_state->port_c_suspend & (1 << wIndex))
		status |= 1 << USB_PORT_FEAT_C_SUSPEND;

	return status;
}

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692 693 694 695
int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
		u16 wIndex, char *buf, u16 wLength)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
696
	int max_ports;
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697
	unsigned long flags;
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698
	u32 temp, status;
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699
	int retval = 0;
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700
	__le32 __iomem **port_array;
701
	int slot_id;
702
	struct xhci_bus_state *bus_state;
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703
	u16 link_state = 0;
704
	u16 wake_mask = 0;
705
	u16 timeout = 0;
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706

707
	max_ports = xhci_get_ports(hcd, &port_array);
708
	bus_state = &xhci->bus_state[hcd_index(hcd)];
S
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709 710 711 712 713 714 715 716

	spin_lock_irqsave(&xhci->lock, flags);
	switch (typeReq) {
	case GetHubStatus:
		/* No power source, over-current reported per port */
		memset(buf, 0, 4);
		break;
	case GetHubDescriptor:
717 718 719 720 721 722 723 724 725 726 727
		/* Check to make sure userspace is asking for the USB 3.0 hub
		 * descriptor for the USB 3.0 roothub.  If not, we stall the
		 * endpoint, like external hubs do.
		 */
		if (hcd->speed == HCD_USB3 &&
				(wLength < USB_DT_SS_HUB_SIZE ||
				 wValue != (USB_DT_SS_HUB << 8))) {
			xhci_dbg(xhci, "Wrong hub descriptor type for "
					"USB 3.0 roothub.\n");
			goto error;
		}
728 729
		xhci_hub_descriptor(hcd, xhci,
				(struct usb_hub_descriptor *) buf);
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730
		break;
731 732 733 734 735 736 737
	case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
		if ((wValue & 0xff00) != (USB_DT_BOS << 8))
			goto error;

		if (hcd->speed != HCD_USB3)
			goto error;

738
		/* Set the U1 and U2 exit latencies. */
739 740
		memcpy(buf, &usb_bos_descriptor,
				USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
741 742 743 744 745
		if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
			temp = readl(&xhci->cap_regs->hcs_params3);
			buf[12] = HCS_U1_LATENCY(temp);
			put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
		}
746

747
		/* Indicate whether the host has LTM support. */
748
		temp = readl(&xhci->cap_regs->hcc_params);
749 750 751
		if (HCC_LTC(temp))
			buf[8] |= USB_LTM_SUPPORT;

752 753
		spin_unlock_irqrestore(&xhci->lock, flags);
		return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
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754
	case GetPortStatus:
755
		if (!wIndex || wIndex > max_ports)
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756 757
			goto error;
		wIndex--;
758
		temp = readl(port_array[wIndex]);
759 760 761 762
		if (temp == 0xffffffff) {
			retval = -ENODEV;
			break;
		}
763
		status = xhci_get_port_status(hcd, bus_state, port_array,
764
				wIndex, temp, flags);
765 766
		if (status == 0xffffffff)
			goto error;
767

768 769
		xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
				wIndex, temp);
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770
		xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
771

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772 773 774
		put_unaligned(cpu_to_le32(status), (__le32 *) buf);
		break;
	case SetPortFeature:
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775 776
		if (wValue == USB_PORT_FEAT_LINK_STATE)
			link_state = (wIndex & 0xff00) >> 3;
777 778
		if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
			wake_mask = wIndex & 0xff00;
779 780
		/* The MSB of wIndex is the U1/U2 timeout */
		timeout = (wIndex & 0xff00) >> 8;
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781
		wIndex &= 0xff;
782
		if (!wIndex || wIndex > max_ports)
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783 784
			goto error;
		wIndex--;
785
		temp = readl(port_array[wIndex]);
786 787 788 789
		if (temp == 0xffffffff) {
			retval = -ENODEV;
			break;
		}
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790
		temp = xhci_port_state_to_neutral(temp);
791
		/* FIXME: What new port features do we need to support? */
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792
		switch (wValue) {
793
		case USB_PORT_FEAT_SUSPEND:
794
			temp = readl(port_array[wIndex]);
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795 796 797 798 799 800 801 802
			if ((temp & PORT_PLS_MASK) != XDEV_U0) {
				/* Resume the port to U0 first */
				xhci_set_link_state(xhci, port_array, wIndex,
							XDEV_U0);
				spin_unlock_irqrestore(&xhci->lock, flags);
				msleep(10);
				spin_lock_irqsave(&xhci->lock, flags);
			}
803 804 805 806
			/* In spec software should not attempt to suspend
			 * a port unless the port reports that it is in the
			 * enabled (PED = ‘1’,PLS < ‘3’) state.
			 */
807
			temp = readl(port_array[wIndex]);
808 809 810 811 812 813 814
			if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
				|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
				xhci_warn(xhci, "USB core suspending device "
					  "not in U0/U1/U2.\n");
				goto error;
			}

815 816
			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
					wIndex + 1);
817 818 819 820 821 822 823 824 825
			if (!slot_id) {
				xhci_warn(xhci, "slot_id is zero\n");
				goto error;
			}
			/* unlock to execute stop endpoint commands */
			spin_unlock_irqrestore(&xhci->lock, flags);
			xhci_stop_device(xhci, slot_id, 1);
			spin_lock_irqsave(&xhci->lock, flags);

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826
			xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
827 828 829 830 831

			spin_unlock_irqrestore(&xhci->lock, flags);
			msleep(10); /* wait device to enter */
			spin_lock_irqsave(&xhci->lock, flags);

832
			temp = readl(port_array[wIndex]);
833
			bus_state->suspended_ports |= 1 << wIndex;
834
			break;
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835
		case USB_PORT_FEAT_LINK_STATE:
836
			temp = readl(port_array[wIndex]);
837 838 839 840 841 842 843 844 845 846 847 848

			/* Disable port */
			if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
				xhci_dbg(xhci, "Disable port %d\n", wIndex);
				temp = xhci_port_state_to_neutral(temp);
				/*
				 * Clear all change bits, so that we get a new
				 * connection event.
				 */
				temp |= PORT_CSC | PORT_PEC | PORT_WRC |
					PORT_OCC | PORT_RC | PORT_PLC |
					PORT_CEC;
849
				writel(temp | PORT_PE, port_array[wIndex]);
850
				temp = readl(port_array[wIndex]);
851 852 853 854 855 856 857 858
				break;
			}

			/* Put link in RxDetect (enable port) */
			if (link_state == USB_SS_PORT_LS_RX_DETECT) {
				xhci_dbg(xhci, "Enable port %d\n", wIndex);
				xhci_set_link_state(xhci, port_array, wIndex,
						link_state);
859
				temp = readl(port_array[wIndex]);
860 861 862
				break;
			}

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Andiry Xu 已提交
863
			/* Software should not attempt to set
864
			 * port link state above '3' (U3) and the port
A
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865 866 867
			 * must be enabled.
			 */
			if ((temp & PORT_PE) == 0 ||
868
				(link_state > USB_SS_PORT_LS_U3)) {
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869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
				xhci_warn(xhci, "Cannot set link state.\n");
				goto error;
			}

			if (link_state == USB_SS_PORT_LS_U3) {
				slot_id = xhci_find_slot_id_by_port(hcd, xhci,
						wIndex + 1);
				if (slot_id) {
					/* unlock to execute stop endpoint
					 * commands */
					spin_unlock_irqrestore(&xhci->lock,
								flags);
					xhci_stop_device(xhci, slot_id, 1);
					spin_lock_irqsave(&xhci->lock, flags);
				}
			}

A
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886 887
			xhci_set_link_state(xhci, port_array, wIndex,
						link_state);
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888 889 890 891 892

			spin_unlock_irqrestore(&xhci->lock, flags);
			msleep(20); /* wait device to enter */
			spin_lock_irqsave(&xhci->lock, flags);

893
			temp = readl(port_array[wIndex]);
A
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894 895 896
			if (link_state == USB_SS_PORT_LS_U3)
				bus_state->suspended_ports |= 1 << wIndex;
			break;
S
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897 898 899 900
		case USB_PORT_FEAT_POWER:
			/*
			 * Turn on ports, even if there isn't per-port switching.
			 * HC will report connect events even before this is set.
901
			 * However, hub_wq will ignore the roothub events until
S
Sarah Sharp 已提交
902 903
			 * the roothub is registered.
			 */
904
			writel(temp | PORT_POWER, port_array[wIndex]);
S
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905

906
			temp = readl(port_array[wIndex]);
S
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907
			xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
908

909
			spin_unlock_irqrestore(&xhci->lock, flags);
910 911 912 913 914
			temp = usb_acpi_power_manageable(hcd->self.root_hub,
					wIndex);
			if (temp)
				usb_acpi_set_power_state(hcd->self.root_hub,
						wIndex, true);
915
			spin_lock_irqsave(&xhci->lock, flags);
S
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916 917 918
			break;
		case USB_PORT_FEAT_RESET:
			temp = (temp | PORT_RESET);
919
			writel(temp, port_array[wIndex]);
S
Sarah Sharp 已提交
920

921
			temp = readl(port_array[wIndex]);
S
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922 923
			xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
			break;
924 925 926
		case USB_PORT_FEAT_REMOTE_WAKE_MASK:
			xhci_set_remote_wake_mask(xhci, port_array,
					wIndex, wake_mask);
927
			temp = readl(port_array[wIndex]);
928 929 930 931
			xhci_dbg(xhci, "set port remote wake mask, "
					"actual port %d status  = 0x%x\n",
					wIndex, temp);
			break;
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932 933
		case USB_PORT_FEAT_BH_PORT_RESET:
			temp |= PORT_WR;
934
			writel(temp, port_array[wIndex]);
A
Andiry Xu 已提交
935

936
			temp = readl(port_array[wIndex]);
A
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937
			break;
938 939 940
		case USB_PORT_FEAT_U1_TIMEOUT:
			if (hcd->speed != HCD_USB3)
				goto error;
941
			temp = readl(port_array[wIndex] + PORTPMSC);
942 943
			temp &= ~PORT_U1_TIMEOUT_MASK;
			temp |= PORT_U1_TIMEOUT(timeout);
944
			writel(temp, port_array[wIndex] + PORTPMSC);
945 946 947 948
			break;
		case USB_PORT_FEAT_U2_TIMEOUT:
			if (hcd->speed != HCD_USB3)
				goto error;
949
			temp = readl(port_array[wIndex] + PORTPMSC);
950 951
			temp &= ~PORT_U2_TIMEOUT_MASK;
			temp |= PORT_U2_TIMEOUT(timeout);
952
			writel(temp, port_array[wIndex] + PORTPMSC);
953
			break;
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954 955 956
		default:
			goto error;
		}
957
		/* unblock any posted writes */
958
		temp = readl(port_array[wIndex]);
S
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959 960
		break;
	case ClearPortFeature:
961
		if (!wIndex || wIndex > max_ports)
S
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962 963
			goto error;
		wIndex--;
964
		temp = readl(port_array[wIndex]);
965 966 967 968
		if (temp == 0xffffffff) {
			retval = -ENODEV;
			break;
		}
969
		/* FIXME: What new port features do we need to support? */
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970 971
		temp = xhci_port_state_to_neutral(temp);
		switch (wValue) {
972
		case USB_PORT_FEAT_SUSPEND:
973
			temp = readl(port_array[wIndex]);
974 975 976 977
			xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
			xhci_dbg(xhci, "PORTSC %04x\n", temp);
			if (temp & PORT_RESET)
				goto error;
978
			if ((temp & PORT_PLS_MASK) == XDEV_U3) {
979 980 981
				if ((temp & PORT_PE) == 0)
					goto error;

A
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982 983 984
				xhci_set_link_state(xhci, port_array, wIndex,
							XDEV_RESUME);
				spin_unlock_irqrestore(&xhci->lock, flags);
985 986
				msleep(20);
				spin_lock_irqsave(&xhci->lock, flags);
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987 988
				xhci_set_link_state(xhci, port_array, wIndex,
							XDEV_U0);
989
			}
990
			bus_state->port_c_suspend |= 1 << wIndex;
991

992 993
			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
					wIndex + 1);
994 995 996 997 998 999 1000
			if (!slot_id) {
				xhci_dbg(xhci, "slot_id is zero\n");
				goto error;
			}
			xhci_ring_device(xhci, slot_id);
			break;
		case USB_PORT_FEAT_C_SUSPEND:
1001
			bus_state->port_c_suspend &= ~(1 << wIndex);
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		case USB_PORT_FEAT_C_RESET:
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1003
		case USB_PORT_FEAT_C_BH_PORT_RESET:
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1004 1005
		case USB_PORT_FEAT_C_CONNECTION:
		case USB_PORT_FEAT_C_OVER_CURRENT:
1006
		case USB_PORT_FEAT_C_ENABLE:
1007
		case USB_PORT_FEAT_C_PORT_LINK_STATE:
1008
			xhci_clear_port_change_bit(xhci, wValue, wIndex,
1009
					port_array[wIndex], temp);
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1010
			break;
1011
		case USB_PORT_FEAT_ENABLE:
1012
			xhci_disable_port(hcd, xhci, wIndex,
1013
					port_array[wIndex], temp);
1014
			break;
1015
		case USB_PORT_FEAT_POWER:
1016
			writel(temp & ~PORT_POWER, port_array[wIndex]);
1017

1018
			spin_unlock_irqrestore(&xhci->lock, flags);
1019 1020 1021 1022 1023
			temp = usb_acpi_power_manageable(hcd->self.root_hub,
					wIndex);
			if (temp)
				usb_acpi_set_power_state(hcd->self.root_hub,
						wIndex, false);
1024
			spin_lock_irqsave(&xhci->lock, flags);
1025
			break;
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1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
		default:
			goto error;
		}
		break;
	default:
error:
		/* "stall" on error */
		retval = -EPIPE;
	}
	spin_unlock_irqrestore(&xhci->lock, flags);
	return retval;
}

/*
 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
 * Ports are 0-indexed from the HCD point of view,
 * and 1-indexed from the USB core pointer of view.
 *
 * Note that the status change bits will be cleared as soon as a port status
 * change event is generated, so we use the saved status from that event.
 */
int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
{
	unsigned long flags;
	u32 temp, status;
1051
	u32 mask;
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	int i, retval;
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1054
	int max_ports;
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	__le32 __iomem **port_array;
1056
	struct xhci_bus_state *bus_state;
1057
	bool reset_change = false;
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1059
	max_ports = xhci_get_ports(hcd, &port_array);
1060
	bus_state = &xhci->bus_state[hcd_index(hcd)];
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	/* Initial status is no changes */
1063
	retval = (max_ports + 8) / 8;
1064
	memset(buf, 0, retval);
1065 1066 1067 1068 1069 1070

	/*
	 * Inform the usbcore about resume-in-progress by returning
	 * a non-zero value even if there are no status changes.
	 */
	status = bus_state->resuming_ports;
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1072
	mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1073

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	spin_lock_irqsave(&xhci->lock, flags);
	/* For each port, did anything change?  If so, set that bit in buf. */
1076
	for (i = 0; i < max_ports; i++) {
1077
		temp = readl(port_array[i]);
1078 1079 1080 1081
		if (temp == 0xffffffff) {
			retval = -ENODEV;
			break;
		}
1082
		if ((temp & mask) != 0 ||
1083 1084 1085
			(bus_state->port_c_suspend & 1 << i) ||
			(bus_state->resume_done[i] && time_after_eq(
			    jiffies, bus_state->resume_done[i]))) {
1086
			buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
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			status = 1;
		}
1089 1090 1091 1092 1093 1094
		if ((temp & PORT_RC))
			reset_change = true;
	}
	if (!status && !reset_change) {
		xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
		clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
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	}
	spin_unlock_irqrestore(&xhci->lock, flags);
	return status ? retval : 0;
}
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#ifdef CONFIG_PM

int xhci_bus_suspend(struct usb_hcd *hcd)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1105
	int max_ports, port_index;
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	__le32 __iomem **port_array;
1107
	struct xhci_bus_state *bus_state;
1108 1109
	unsigned long flags;

1110
	max_ports = xhci_get_ports(hcd, &port_array);
1111
	bus_state = &xhci->bus_state[hcd_index(hcd)];
1112 1113 1114 1115

	spin_lock_irqsave(&xhci->lock, flags);

	if (hcd->self.root_hub->do_remote_wakeup) {
1116 1117 1118 1119 1120
		if (bus_state->resuming_ports) {
			spin_unlock_irqrestore(&xhci->lock, flags);
			xhci_dbg(xhci, "suspend failed because "
						"a port is resuming\n");
			return -EBUSY;
1121 1122 1123
		}
	}

1124
	port_index = max_ports;
1125
	bus_state->bus_suspended = 0;
1126
	while (port_index--) {
1127 1128 1129 1130
		/* suspend the port if the port is not suspended */
		u32 t1, t2;
		int slot_id;

1131
		t1 = readl(port_array[port_index]);
1132 1133 1134
		t2 = xhci_port_state_to_neutral(t1);

		if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1135
			xhci_dbg(xhci, "port %d not suspended\n", port_index);
1136
			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1137
					port_index + 1);
1138 1139 1140 1141 1142 1143 1144
			if (slot_id) {
				spin_unlock_irqrestore(&xhci->lock, flags);
				xhci_stop_device(xhci, slot_id, 1);
				spin_lock_irqsave(&xhci->lock, flags);
			}
			t2 &= ~PORT_PLS_MASK;
			t2 |= PORT_LINK_STROBE | XDEV_U3;
1145
			set_bit(port_index, &bus_state->bus_suspended);
1146
		}
1147
		/* USB core sets remote wake mask for USB 3.0 hubs,
1148
		 * including the USB 3.0 roothub, but only if CONFIG_PM
1149 1150
		 * is enabled, so also enable remote wake here.
		 */
1151
		if (hcd->self.root_hub->do_remote_wakeup) {
1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163
			if (t1 & PORT_CONNECT) {
				t2 |= PORT_WKOC_E | PORT_WKDISC_E;
				t2 &= ~PORT_WKCONN_E;
			} else {
				t2 |= PORT_WKOC_E | PORT_WKCONN_E;
				t2 &= ~PORT_WKDISC_E;
			}
		} else
			t2 &= ~PORT_WAKE_BITS;

		t1 = xhci_port_state_to_neutral(t1);
		if (t1 != t2)
1164
			writel(t2, port_array[port_index]);
1165 1166
	}
	hcd->state = HC_STATE_SUSPENDED;
1167
	bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1168 1169 1170 1171 1172 1173 1174
	spin_unlock_irqrestore(&xhci->lock, flags);
	return 0;
}

int xhci_bus_resume(struct usb_hcd *hcd)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1175
	int max_ports, port_index;
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	__le32 __iomem **port_array;
1177
	struct xhci_bus_state *bus_state;
1178 1179 1180
	u32 temp;
	unsigned long flags;

1181
	max_ports = xhci_get_ports(hcd, &port_array);
1182
	bus_state = &xhci->bus_state[hcd_index(hcd)];
1183

1184
	if (time_before(jiffies, bus_state->next_statechange))
1185 1186 1187 1188 1189 1190 1191 1192 1193
		msleep(5);

	spin_lock_irqsave(&xhci->lock, flags);
	if (!HCD_HW_ACCESSIBLE(hcd)) {
		spin_unlock_irqrestore(&xhci->lock, flags);
		return -ESHUTDOWN;
	}

	/* delay the irqs */
1194
	temp = readl(&xhci->op_regs->command);
1195
	temp &= ~CMD_EIE;
1196
	writel(temp, &xhci->op_regs->command);
1197

1198 1199
	port_index = max_ports;
	while (port_index--) {
1200 1201 1202 1203 1204
		/* Check whether need resume ports. If needed
		   resume port and disable remote wakeup */
		u32 temp;
		int slot_id;

1205
		temp = readl(port_array[port_index]);
1206 1207 1208 1209
		if (DEV_SUPERSPEED(temp))
			temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
		else
			temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1210
		if (test_bit(port_index, &bus_state->bus_suspended) &&
1211 1212
		    (temp & PORT_PLS_MASK)) {
			if (DEV_SUPERSPEED(temp)) {
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				xhci_set_link_state(xhci, port_array,
							port_index, XDEV_U0);
1215
			} else {
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				xhci_set_link_state(xhci, port_array,
						port_index, XDEV_RESUME);
1218 1219 1220 1221 1222

				spin_unlock_irqrestore(&xhci->lock, flags);
				msleep(20);
				spin_lock_irqsave(&xhci->lock, flags);

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				xhci_set_link_state(xhci, port_array,
							port_index, XDEV_U0);
1225
			}
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			/* wait for the port to enter U0 and report port link
			 * state change.
			 */
			spin_unlock_irqrestore(&xhci->lock, flags);
			msleep(20);
			spin_lock_irqsave(&xhci->lock, flags);

			/* Clear PLC */
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			xhci_test_and_clear_bit(xhci, port_array, port_index,
						PORT_PLC);
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1237 1238
			slot_id = xhci_find_slot_id_by_port(hcd,
					xhci, port_index + 1);
1239 1240 1241
			if (slot_id)
				xhci_ring_device(xhci, slot_id);
		} else
1242
			writel(temp, port_array[port_index]);
1243 1244
	}

1245
	(void) readl(&xhci->op_regs->command);
1246

1247
	bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1248
	/* re-enable irqs */
1249
	temp = readl(&xhci->op_regs->command);
1250
	temp |= CMD_EIE;
1251
	writel(temp, &xhci->op_regs->command);
1252
	temp = readl(&xhci->op_regs->command);
1253 1254 1255 1256 1257

	spin_unlock_irqrestore(&xhci->lock, flags);
	return 0;
}

1258
#endif	/* CONFIG_PM */