kvm_host.h 17.2 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * Derived from arch/arm/include/asm/kvm_host.h:
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM64_KVM_HOST_H__
#define __ARM64_KVM_HOST_H__

25 26
#include <linux/types.h>
#include <linux/kvm_types.h>
27
#include <asm/cpufeature.h>
28
#include <asm/daifflags.h>
29
#include <asm/fpsimd.h>
30
#include <asm/kvm.h>
31
#include <asm/kvm_asm.h>
32
#include <asm/kvm_mmio.h>
33
#include <asm/thread_info.h>
34

35 36
#define __KVM_HAVE_ARCH_INTC_INITIALIZED

37
#define KVM_USER_MEM_SLOTS 512
38
#define KVM_HALT_POLL_NS_DEFAULT 500000
39 40 41

#include <kvm/arm_vgic.h>
#include <kvm/arm_arch_timer.h>
42
#include <kvm/arm_pmu.h>
43

44 45
#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS

46
#define KVM_VCPU_MAX_FEATURES 4
47

48
#define KVM_REQ_SLEEP \
49
	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
50
#define KVM_REQ_IRQ_PENDING	KVM_ARCH_REQ(1)
51
#define KVM_REQ_VCPU_RESET	KVM_ARCH_REQ(2)
52

53 54
DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);

55
int __attribute_const__ kvm_target_cpu(void);
56
int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
57
int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext);
58
void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
59 60 61 62 63 64

struct kvm_arch {
	/* The VMID generation used for the virt. memory system */
	u64    vmid_gen;
	u32    vmid;

S
Steven Price 已提交
65
	/* 1-level 2nd stage table, protected by kvm->mmu_lock */
66 67 68 69 70
	pgd_t *pgd;

	/* VTTBR value associated with above pgd and vmid */
	u64    vttbr;

71 72 73
	/* The last vcpu id that ran on each physical CPU */
	int __percpu *last_vcpu_ran;

74 75 76
	/* The maximum number of vCPUs depends on the used GIC model */
	int max_vcpus;

77 78
	/* Interrupt controller */
	struct vgic_dist	vgic;
79 80 81

	/* Mandated version of PSCI */
	u32 psci_version;
82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
};

#define KVM_NR_MEM_OBJS     40

/*
 * We don't want allocation failures within the mmu code, so we preallocate
 * enough memory for a single page fault in a cache.
 */
struct kvm_mmu_memory_cache {
	int nobjs;
	void *objects[KVM_NR_MEM_OBJS];
};

struct kvm_vcpu_fault_info {
	u32 esr_el2;		/* Hyp Syndrom Register */
	u64 far_el2;		/* Hyp Fault Address Register */
	u64 hpfar_el2;		/* Hyp IPA Fault Address Register */
99
	u64 disr_el1;		/* Deferred [SError] Status Register */
100 101
};

102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
/*
 * 0 is reserved as an invalid value.
 * Order should be kept in sync with the save/restore code.
 */
enum vcpu_sysreg {
	__INVALID_SYSREG__,
	MPIDR_EL1,	/* MultiProcessor Affinity Register */
	CSSELR_EL1,	/* Cache Size Selection Register */
	SCTLR_EL1,	/* System Control Register */
	ACTLR_EL1,	/* Auxiliary Control Register */
	CPACR_EL1,	/* Coprocessor Access Control */
	TTBR0_EL1,	/* Translation Table Base Register 0 */
	TTBR1_EL1,	/* Translation Table Base Register 1 */
	TCR_EL1,	/* Translation Control Register */
	ESR_EL1,	/* Exception Syndrome Register */
117 118
	AFSR0_EL1,	/* Auxiliary Fault Status Register 0 */
	AFSR1_EL1,	/* Auxiliary Fault Status Register 1 */
119 120 121 122 123 124 125 126 127 128 129 130
	FAR_EL1,	/* Fault Address Register */
	MAIR_EL1,	/* Memory Attribute Indirection Register */
	VBAR_EL1,	/* Vector Base Address Register */
	CONTEXTIDR_EL1,	/* Context ID Register */
	TPIDR_EL0,	/* Thread ID, User R/W */
	TPIDRRO_EL0,	/* Thread ID, User R/O */
	TPIDR_EL1,	/* Thread ID, Privileged */
	AMAIR_EL1,	/* Aux Memory Attribute Indirection Register */
	CNTKCTL_EL1,	/* Timer Control Register (EL1) */
	PAR_EL1,	/* Physical Address Register */
	MDSCR_EL1,	/* Monitor Debug System Control Register */
	MDCCINT_EL1,	/* Monitor Debug Comms Channel Interrupt Enable Reg */
131
	DISR_EL1,	/* Deferred Interrupt Status Register */
132

133 134
	/* Performance Monitors Registers */
	PMCR_EL0,	/* Control Register */
135
	PMSELR_EL0,	/* Event Counter Selection Register */
136 137 138
	PMEVCNTR0_EL0,	/* Event Counter Register (0-30) */
	PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
	PMCCNTR_EL0,	/* Cycle Counter Register */
139 140 141
	PMEVTYPER0_EL0,	/* Event Type Register (0-30) */
	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
	PMCCFILTR_EL0,	/* Cycle Count Filter Register */
142
	PMCNTENSET_EL0,	/* Count Enable Set Register */
143
	PMINTENSET_EL1,	/* Interrupt Enable Set Register */
144
	PMOVSSET_EL0,	/* Overflow Flag Status Set Register */
145
	PMSWINC_EL0,	/* Software Increment Register */
146
	PMUSERENR_EL0,	/* User Enable Register */
147

148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197
	/* 32bit specific registers. Keep them at the end of the range */
	DACR32_EL2,	/* Domain Access Control Register */
	IFSR32_EL2,	/* Instruction Fault Status Register */
	FPEXC32_EL2,	/* Floating-Point Exception Control Register */
	DBGVCR32_EL2,	/* Debug Vector Catch Register */

	NR_SYS_REGS	/* Nothing after this line! */
};

/* 32bit mapping */
#define c0_MPIDR	(MPIDR_EL1 * 2)	/* MultiProcessor ID Register */
#define c0_CSSELR	(CSSELR_EL1 * 2)/* Cache Size Selection Register */
#define c1_SCTLR	(SCTLR_EL1 * 2)	/* System Control Register */
#define c1_ACTLR	(ACTLR_EL1 * 2)	/* Auxiliary Control Register */
#define c1_CPACR	(CPACR_EL1 * 2)	/* Coprocessor Access Control */
#define c2_TTBR0	(TTBR0_EL1 * 2)	/* Translation Table Base Register 0 */
#define c2_TTBR0_high	(c2_TTBR0 + 1)	/* TTBR0 top 32 bits */
#define c2_TTBR1	(TTBR1_EL1 * 2)	/* Translation Table Base Register 1 */
#define c2_TTBR1_high	(c2_TTBR1 + 1)	/* TTBR1 top 32 bits */
#define c2_TTBCR	(TCR_EL1 * 2)	/* Translation Table Base Control R. */
#define c3_DACR		(DACR32_EL2 * 2)/* Domain Access Control Register */
#define c5_DFSR		(ESR_EL1 * 2)	/* Data Fault Status Register */
#define c5_IFSR		(IFSR32_EL2 * 2)/* Instruction Fault Status Register */
#define c5_ADFSR	(AFSR0_EL1 * 2)	/* Auxiliary Data Fault Status R */
#define c5_AIFSR	(AFSR1_EL1 * 2)	/* Auxiliary Instr Fault Status R */
#define c6_DFAR		(FAR_EL1 * 2)	/* Data Fault Address Register */
#define c6_IFAR		(c6_DFAR + 1)	/* Instruction Fault Address Register */
#define c7_PAR		(PAR_EL1 * 2)	/* Physical Address Register */
#define c7_PAR_high	(c7_PAR + 1)	/* PAR top 32 bits */
#define c10_PRRR	(MAIR_EL1 * 2)	/* Primary Region Remap Register */
#define c10_NMRR	(c10_PRRR + 1)	/* Normal Memory Remap Register */
#define c12_VBAR	(VBAR_EL1 * 2)	/* Vector Base Address Register */
#define c13_CID		(CONTEXTIDR_EL1 * 2)	/* Context ID Register */
#define c13_TID_URW	(TPIDR_EL0 * 2)	/* Thread ID, User R/W */
#define c13_TID_URO	(TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
#define c13_TID_PRIV	(TPIDR_EL1 * 2)	/* Thread ID, Privileged */
#define c10_AMAIR0	(AMAIR_EL1 * 2)	/* Aux Memory Attr Indirection Reg */
#define c10_AMAIR1	(c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL	(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */

#define cp14_DBGDSCRext	(MDSCR_EL1 * 2)
#define cp14_DBGBCR0	(DBGBCR0_EL1 * 2)
#define cp14_DBGBVR0	(DBGBVR0_EL1 * 2)
#define cp14_DBGBXVR0	(cp14_DBGBVR0 + 1)
#define cp14_DBGWCR0	(DBGWCR0_EL1 * 2)
#define cp14_DBGWVR0	(DBGWVR0_EL1 * 2)
#define cp14_DBGDCCINT	(MDCCINT_EL1 * 2)

#define NR_COPRO_REGS	(NR_SYS_REGS * 2)

198 199
struct kvm_cpu_context {
	struct kvm_regs	gp_regs;
200 201
	union {
		u64 sys_regs[NR_SYS_REGS];
202
		u32 copro[NR_COPRO_REGS];
203
	};
204 205

	struct kvm_vcpu *__hyp_running_vcpu;
206 207 208 209
};

typedef struct kvm_cpu_context kvm_cpu_context_t;

210 211 212 213 214 215 216
struct vcpu_reset_state {
	unsigned long	pc;
	unsigned long	r0;
	bool		be;
	bool		reset;
};

217 218 219 220 221
struct kvm_vcpu_arch {
	struct kvm_cpu_context ctxt;

	/* HYP configuration */
	u64 hcr_el2;
222
	u32 mdcr_el2;
223 224 225 226

	/* Exception Information */
	struct kvm_vcpu_fault_info fault;

227 228 229
	/* State of various workarounds, see kvm_asm.h for bit assignment */
	u64 workaround_flags;

230 231
	/* Miscellaneous vcpu state flags */
	u64 flags;
232

233 234 235 236 237
	/*
	 * We maintain more than a single set of debug registers to support
	 * debugging the guest from the host and to maintain separate host and
	 * guest state during world switches. vcpu_debug_state are the debug
	 * registers of the vcpu as the guest sees them.  host_debug_state are
238 239 240 241
	 * the host registers which are saved and restored during
	 * world switches. external_debug_state contains the debug
	 * values we want to debug the guest. This is set via the
	 * KVM_SET_GUEST_DEBUG ioctl.
242 243 244 245 246 247
	 *
	 * debug_ptr points to the set of debug registers that should be loaded
	 * onto the hardware when running the guest.
	 */
	struct kvm_guest_debug_arch *debug_ptr;
	struct kvm_guest_debug_arch vcpu_debug_state;
248
	struct kvm_guest_debug_arch external_debug_state;
249

250 251
	/* Pointer to host CPU context */
	kvm_cpu_context_t *host_cpu_context;
252 253 254 255

	struct thread_info *host_thread_info;	/* hyp VA */
	struct user_fpsimd_state *host_fpsimd_state;	/* hyp VA */

256 257 258 259 260 261
	struct {
		/* {Break,watch}point registers */
		struct kvm_guest_debug_arch regs;
		/* Statistical profiling extension */
		u64 pmscr_el1;
	} host_debug_state;
262 263 264 265

	/* VGIC state */
	struct vgic_cpu vgic_cpu;
	struct arch_timer_cpu timer_cpu;
266
	struct kvm_pmu pmu;
267 268 269 270 271 272

	/*
	 * Anything that is not used directly from assembly code goes
	 * here.
	 */

273 274 275 276 277 278 279 280 281 282 283
	/*
	 * Guest registers we preserve during guest debugging.
	 *
	 * These shadow registers are updated by the kvm_handle_sys_reg
	 * trap handler if the guest accesses or updates them while we
	 * are using guest debug.
	 */
	struct {
		u32	mdscr_el1;
	} guest_debug_preserved;

284 285
	/* vcpu power-off state */
	bool power_off;
286

287 288 289
	/* Don't run the guest (internal implementation need) */
	bool pause;

290 291 292 293 294 295 296
	/* IO related fields */
	struct kvm_decode mmio_decode;

	/* Cache some mmu pages needed inside spinlock regions */
	struct kvm_mmu_memory_cache mmu_page_cache;

	/* Target CPU and feature flags */
297
	int target;
298 299 300 301
	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);

	/* Detect first run of a vcpu */
	bool has_run_once;
302 303 304

	/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
	u64 vsesr_el2;
305

306 307 308
	/* Additional reset state */
	struct vcpu_reset_state	reset_state;

309 310 311
	/* True when deferrable sysregs are loaded on the physical CPU,
	 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
	bool sysregs_loaded_on_cpu;
312 313
};

314 315
/* vcpu_arch flags field values: */
#define KVM_ARM64_DEBUG_DIRTY		(1 << 0)
316 317 318
#define KVM_ARM64_FP_ENABLED		(1 << 1) /* guest FP regs loaded */
#define KVM_ARM64_FP_HOST		(1 << 2) /* host FP regs loaded */
#define KVM_ARM64_HOST_SVE_IN_USE	(1 << 3) /* backup for host TIF_SVE */
319
#define KVM_ARM64_HOST_SVE_ENABLED	(1 << 4) /* SVE enabled for EL0 */
320

321
#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.gp_regs)
322 323 324 325 326 327 328 329 330

/*
 * Only use __vcpu_sys_reg if you know you want the memory backed version of a
 * register, and not the one most recently accessed by a running VCPU.  For
 * example, for userspace access or for system registers that are never context
 * switched, but only emulated.
 */
#define __vcpu_sys_reg(v,r)	((v)->arch.ctxt.sys_regs[(r)])

331 332
u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg);
void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
333

334 335 336 337 338 339
/*
 * CP14 and CP15 live in the same array, as they are backed by the
 * same system registers.
 */
#define vcpu_cp14(v,r)		((v)->arch.ctxt.copro[(r)])
#define vcpu_cp15(v,r)		((v)->arch.ctxt.copro[(r)])
340 341

struct kvm_vm_stat {
342
	ulong remote_tlb_flush;
343 344 345
};

struct kvm_vcpu_stat {
346 347 348 349 350
	u64 halt_successful_poll;
	u64 halt_attempted_poll;
	u64 halt_poll_invalid;
	u64 halt_wakeup;
	u64 hvc_exit_stat;
351 352 353 354 355
	u64 wfe_exit_stat;
	u64 wfi_exit_stat;
	u64 mmio_exit_user;
	u64 mmio_exit_kernel;
	u64 exits;
356 357
};

358
int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
359 360 361 362
unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
363 364
int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
			      struct kvm_vcpu_events *events);
365

366 367
int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
			      struct kvm_vcpu_events *events);
368 369 370 371 372

#define KVM_ARCH_WANT_MMU_NOTIFIER
int kvm_unmap_hva_range(struct kvm *kvm,
			unsigned long start, unsigned long end);
void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
373 374
int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
375 376

struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
377
struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
378 379
void kvm_arm_halt_guest(struct kvm *kvm);
void kvm_arm_resume_guest(struct kvm *kvm);
380

381
u64 __kvm_call_hyp(void *hypfn, ...);
382 383
#define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)

384
void force_vm_exit(const cpumask_t *mask);
385
void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
386 387 388

int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
		int exception_index);
389 390
void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
		       int exception_index);
391 392 393 394

int kvm_perf_init(void);
int kvm_perf_teardown(void);

395 396
void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);

397 398
struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);

399 400
DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);

401 402
void __kvm_enable_ssbs(void);

M
Marc Zyngier 已提交
403
static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
404 405 406
				       unsigned long hyp_stack_ptr,
				       unsigned long vector_ptr)
{
407 408 409 410 411 412 413
	/*
	 * Calculate the raw per-cpu offset without a translation from the
	 * kernel's mapping to the linear mapping, and store it in tpidr_el2
	 * so that we can use adr_l to access per-cpu variables in EL2.
	 */
	u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) -
			 (u64)kvm_ksym_ref(kvm_host_cpu_state));
414

415
	/*
416 417 418 419
	 * Call initialization code, and switch to the full blown HYP code.
	 * If the cpucaps haven't been finalized yet, something has gone very
	 * wrong, and hyp will crash and burn when it uses any
	 * cpus_have_const_cap() wrapper.
420
	 */
421
	BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
422
	__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
423 424 425 426 427 428 429 430 431

	/*
	 * Disabling SSBD on a non-VHE system requires us to enable SSBS
	 * at EL2.
	 */
	if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
	    arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
		kvm_call_hyp(__kvm_enable_ssbs);
	}
432
}
433

434 435 436 437 438 439 440 441 442 443 444 445 446
static inline bool kvm_arch_check_sve_has_vhe(void)
{
	/*
	 * The Arm architecture specifies that implementation of SVE
	 * requires VHE also to be implemented.  The KVM code for arm64
	 * relies on this when SVE is present:
	 */
	if (system_supports_sve())
		return has_vhe();
	else
		return true;
}

447 448 449 450
static inline void kvm_arch_hardware_unsetup(void) {}
static inline void kvm_arch_sync_events(struct kvm *kvm) {}
static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
451
static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
452

453 454 455
void kvm_arm_init_debug(void);
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
456
void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
457
bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run);
458 459 460 461 462 463
int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
			       struct kvm_device_attr *attr);
int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
			       struct kvm_device_attr *attr);
int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
			       struct kvm_device_attr *attr);
464

465 466
static inline void __cpu_init_stage2(void)
{
467 468 469 470
	u32 parange = kvm_call_hyp(__init_stage2_translation);

	WARN_ONCE(parange < 40,
		  "PARange is %d bits, unsupported configuration!", parange);
471 472
}

473 474 475 476 477 478 479 480
/* Guest/host FPSIMD coordination helpers */
int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);

#ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
481
{
482
	return kvm_arch_vcpu_run_map_fp(vcpu);
483
}
484
#endif
485

486 487 488 489 490 491 492 493
static inline void kvm_arm_vhe_guest_enter(void)
{
	local_daif_mask();
}

static inline void kvm_arm_vhe_guest_exit(void)
{
	local_daif_restore(DAIF_PROCCTX_NOIRQ);
494 495 496 497 498 499 500

	/*
	 * When we exit from the guest we change a number of CPU configuration
	 * parameters, such as traps.  Make sure these changes take effect
	 * before running the host or additional guests.
	 */
	isb();
501
}
502 503 504 505 506 507

static inline bool kvm_arm_harden_branch_predictor(void)
{
	return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
}

508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530
#define KVM_SSBD_UNKNOWN		-1
#define KVM_SSBD_FORCE_DISABLE		0
#define KVM_SSBD_KERNEL		1
#define KVM_SSBD_FORCE_ENABLE		2
#define KVM_SSBD_MITIGATED		3

static inline int kvm_arm_have_ssbd(void)
{
	switch (arm64_get_ssbd_state()) {
	case ARM64_SSBD_FORCE_DISABLE:
		return KVM_SSBD_FORCE_DISABLE;
	case ARM64_SSBD_KERNEL:
		return KVM_SSBD_KERNEL;
	case ARM64_SSBD_FORCE_ENABLE:
		return KVM_SSBD_FORCE_ENABLE;
	case ARM64_SSBD_MITIGATED:
		return KVM_SSBD_MITIGATED;
	case ARM64_SSBD_UNKNOWN:
	default:
		return KVM_SSBD_UNKNOWN;
	}
}

531 532 533
void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);

534 535 536 537
#define __KVM_HAVE_ARCH_VM_ALLOC
struct kvm *kvm_arch_alloc_vm(void);
void kvm_arch_free_vm(struct kvm *kvm);

538
#endif /* __ARM64_KVM_HOST_H__ */