dmtimer.c 23.9 KB
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/*
 * linux/arch/arm/plat-omap/dmtimer.c
 *
 * OMAP Dual-Mode Timers
 *
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 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
 * Thara Gopinath <thara@ti.com>
 *
 * dmtimer adaptation to platform_driver.
 *
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 * Copyright (C) 2005 Nokia Corporation
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 * OMAP2 support by Juha Yrjola
 * API improvements and OMAP2 clock framework support by Timo Teras
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 *
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 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
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 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
#include <linux/of_device.h>
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#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
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#include <plat/dmtimer.h>
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static u32 omap_reserved_systimers;
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static LIST_HEAD(omap_timer_list);
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static DEFINE_SPINLOCK(dm_timer_lock);
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enum {
	REQUEST_ANY = 0,
	REQUEST_BY_ID,
	REQUEST_BY_CAP,
	REQUEST_BY_NODE,
};

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/**
 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
 * @timer:      timer pointer over which read operation to perform
 * @reg:        lowest byte holds the register offset
 *
 * The posted mode bit is encoded in reg. Note that in posted mode write
 * pending bit must be checked. Otherwise a read of a non completed write
 * will produce an error.
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 */
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
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{
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	WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
	return __omap_dm_timer_read(timer, reg, timer->posted);
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}
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/**
 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
 * @timer:      timer pointer over which write operation is to perform
 * @reg:        lowest byte holds the register offset
 * @value:      data to write into the register
 *
 * The posted mode bit is encoded in reg. Note that in posted mode the write
 * pending bit must be checked. Otherwise a write on a register which has a
 * pending write will be lost.
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 */
static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
						u32 value)
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{
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	WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
	__omap_dm_timer_write(timer, reg, value, timer->posted);
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}

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static void omap_timer_restore_context(struct omap_dm_timer *timer)
{
	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
				timer->context.twer);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
				timer->context.tcrr);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
				timer->context.tldr);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
				timer->context.tmar);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
				timer->context.tsicr);
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	writel_relaxed(timer->context.tier, timer->irq_ena);
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	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
				timer->context.tclr);
}

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static int omap_dm_timer_reset(struct omap_dm_timer *timer)
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{
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	u32 l, timeout = 100000;
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	if (timer->revision != 1)
		return -EINVAL;
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	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);

	do {
		l = __omap_dm_timer_read(timer,
					 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
	} while (!l && timeout--);

	if (!timeout) {
		dev_err(&timer->pdev->dev, "Timer failed to reset\n");
		return -ETIMEDOUT;
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	}
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	/* Configure timer for smart-idle mode */
	l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
	l |= 0x2 << 0x3;
	__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);

	timer->posted = 0;

	return 0;
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}

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static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
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{
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	int rc;

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	/*
	 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
	 * do not call clk_get() for these devices.
	 */
	if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
		timer->fclk = clk_get(&timer->pdev->dev, "fck");
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		if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
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			dev_err(&timer->pdev->dev, ": No fclk handle.\n");
			return -EINVAL;
		}
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	}

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	omap_dm_timer_enable(timer);

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	if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
		rc = omap_dm_timer_reset(timer);
		if (rc) {
			omap_dm_timer_disable(timer);
			return rc;
		}
	}
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	__omap_dm_timer_enable_posted(timer);
	omap_dm_timer_disable(timer);
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	return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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}

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static inline u32 omap_dm_timer_reserved_systimer(int id)
{
	return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
}

int omap_dm_timer_reserve_systimer(int id)
{
	if (omap_dm_timer_reserved_systimer(id))
		return -ENODEV;

	omap_reserved_systimers |= (1 << (id - 1));

	return 0;
}

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static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
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{
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	struct omap_dm_timer *timer = NULL, *t;
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	struct device_node *np = NULL;
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	unsigned long flags;
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	u32 cap = 0;
	int id = 0;

	switch (req_type) {
	case REQUEST_BY_ID:
		id = *(int *)data;
		break;
	case REQUEST_BY_CAP:
		cap = *(u32 *)data;
		break;
	case REQUEST_BY_NODE:
		np = (struct device_node *)data;
		break;
	default:
		/* REQUEST_ANY */
		break;
	}
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	spin_lock_irqsave(&dm_timer_lock, flags);
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	list_for_each_entry(t, &omap_timer_list, node) {
		if (t->reserved)
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			continue;

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		switch (req_type) {
		case REQUEST_BY_ID:
			if (id == t->pdev->id) {
				timer = t;
				timer->reserved = 1;
				goto found;
			}
			break;
		case REQUEST_BY_CAP:
			if (cap == (t->capability & cap)) {
				/*
				 * If timer is not NULL, we have already found
				 * one timer but it was not an exact match
				 * because it had more capabilites that what
				 * was required. Therefore, unreserve the last
				 * timer found and see if this one is a better
				 * match.
				 */
				if (timer)
					timer->reserved = 0;
				timer = t;
				timer->reserved = 1;

				/* Exit loop early if we find an exact match */
				if (t->capability == cap)
					goto found;
			}
			break;
		case REQUEST_BY_NODE:
			if (np == t->pdev->dev.of_node) {
				timer = t;
				timer->reserved = 1;
				goto found;
			}
			break;
		default:
			/* REQUEST_ANY */
			timer = t;
			timer->reserved = 1;
			goto found;
		}
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	}
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found:
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	spin_unlock_irqrestore(&dm_timer_lock, flags);
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	if (timer && omap_dm_timer_prepare(timer)) {
		timer->reserved = 0;
		timer = NULL;
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	}
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	if (!timer)
		pr_debug("%s: timer request failed!\n", __func__);
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	return timer;
}
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struct omap_dm_timer *omap_dm_timer_request(void)
{
	return _omap_dm_timer_request(REQUEST_ANY, NULL);
}
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EXPORT_SYMBOL_GPL(omap_dm_timer_request);
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struct omap_dm_timer *omap_dm_timer_request_specific(int id)
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{
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	/* Requesting timer by ID is not supported when device tree is used */
	if (of_have_populated_dt()) {
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		pr_warn("%s: Please use omap_dm_timer_request_by_cap/node()\n",
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			__func__);
		return NULL;
	}

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	return _omap_dm_timer_request(REQUEST_BY_ID, &id);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
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/**
 * omap_dm_timer_request_by_cap - Request a timer by capability
 * @cap:	Bit mask of capabilities to match
 *
 * Find a timer based upon capabilities bit mask. Callers of this function
 * should use the definitions found in the plat/dmtimer.h file under the
 * comment "timer capabilities used in hwmod database". Returns pointer to
 * timer handle on success and a NULL pointer on failure.
 */
struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
{
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	return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
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/**
 * omap_dm_timer_request_by_node - Request a timer by device-tree node
 * @np:		Pointer to device-tree timer node
 *
 * Request a timer based upon a device node pointer. Returns pointer to
 * timer handle on success and a NULL pointer on failure.
 */
struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
{
	if (!np)
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		return NULL;

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	return _omap_dm_timer_request(REQUEST_BY_NODE, np);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_node);
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int omap_dm_timer_free(struct omap_dm_timer *timer)
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{
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	if (unlikely(!timer))
		return -EINVAL;

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	clk_put(timer->fclk);
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	WARN_ON(!timer->reserved);
	timer->reserved = 0;
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_free);
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void omap_dm_timer_enable(struct omap_dm_timer *timer)
{
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	int c;

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	pm_runtime_get_sync(&timer->pdev->dev);
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	if (!(timer->capability & OMAP_TIMER_ALWON)) {
		if (timer->get_context_loss_count) {
			c = timer->get_context_loss_count(&timer->pdev->dev);
			if (c != timer->ctx_loss_count) {
				omap_timer_restore_context(timer);
				timer->ctx_loss_count = c;
			}
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		} else {
			omap_timer_restore_context(timer);
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		}
	}
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
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void omap_dm_timer_disable(struct omap_dm_timer *timer)
{
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	pm_runtime_put_sync(&timer->pdev->dev);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
{
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	if (timer)
		return timer->irq;
	return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
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#if defined(CONFIG_ARCH_OMAP1)
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#include <mach/hardware.h>
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/**
 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 * @inputmask: current value of idlect mask
 */
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
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	int i = 0;
	struct omap_dm_timer *timer = NULL;
	unsigned long flags;
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	/* If ARMXOR cannot be idled this function call is unnecessary */
	if (!(inputmask & (1 << 1)))
		return inputmask;

	/* If any active timer is using ARMXOR return modified mask */
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	spin_lock_irqsave(&dm_timer_lock, flags);
	list_for_each_entry(timer, &omap_timer_list, node) {
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		u32 l;

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		l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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		if (l & OMAP_TIMER_CTRL_ST) {
			if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
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				inputmask &= ~(1 << 1);
			else
				inputmask &= ~(1 << 2);
		}
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		i++;
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	}
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	spin_unlock_irqrestore(&dm_timer_lock, flags);
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	return inputmask;
}
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EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
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#else
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struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
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{
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	if (timer && !IS_ERR(timer->fclk))
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		return timer->fclk;
	return NULL;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
	BUG();
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
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#endif
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int omap_dm_timer_trigger(struct omap_dm_timer *timer)
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{
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	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
		pr_err("%s: timer not available or enabled.\n", __func__);
		return -EINVAL;
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	}

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	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
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int omap_dm_timer_start(struct omap_dm_timer *timer)
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{
	u32 l;
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	if (unlikely(!timer))
		return -EINVAL;

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	omap_dm_timer_enable(timer);

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	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	if (!(l & OMAP_TIMER_CTRL_ST)) {
		l |= OMAP_TIMER_CTRL_ST;
		omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	}
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	/* Save the context */
	timer->context.tclr = l;
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_start);
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int omap_dm_timer_stop(struct omap_dm_timer *timer)
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{
459
	unsigned long rate = 0;
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	if (unlikely(!timer))
		return -EINVAL;

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	if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
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		rate = clk_get_rate(timer->fclk);
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	__omap_dm_timer_stop(timer, timer->posted, rate);
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	/*
	 * Since the register values are computed and written within
	 * __omap_dm_timer_stop, we need to use read to retrieve the
	 * context.
	 */
	timer->context.tclr =
			omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	omap_dm_timer_disable(timer);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
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int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
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{
483
	int ret;
484
	char *parent_name = NULL;
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	struct clk *parent;
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	struct dmtimer_platform_data *pdata;

	if (unlikely(!timer))
		return -EINVAL;

	pdata = timer->pdev->dev.platform_data;
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	if (source < 0 || source >= 3)
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		return -EINVAL;
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	/*
	 * FIXME: Used for OMAP1 devices only because they do not currently
	 * use the clock framework to set the parent clock. To be removed
	 * once OMAP1 migrated to using clock framework for dmtimers
	 */
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	if (pdata && pdata->set_timer_src)
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		return pdata->set_timer_src(timer->pdev, source);

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	if (IS_ERR(timer->fclk))
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		return -EINVAL;

	switch (source) {
	case OMAP_TIMER_SRC_SYS_CLK:
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		parent_name = "timer_sys_ck";
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		break;

	case OMAP_TIMER_SRC_32_KHZ:
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		parent_name = "timer_32k_ck";
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		break;

	case OMAP_TIMER_SRC_EXT_CLK:
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		parent_name = "timer_ext_ck";
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		break;
	}

	parent = clk_get(&timer->pdev->dev, parent_name);
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	if (IS_ERR(parent)) {
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		pr_err("%s: %s not found\n", __func__, parent_name);
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		return -EINVAL;
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	}

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	ret = clk_set_parent(timer->fclk, parent);
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	if (ret < 0)
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		pr_err("%s: failed to set %s as parent\n", __func__,
			parent_name);

	clk_put(parent);
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	return ret;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
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int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
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			    unsigned int load)
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{
	u32 l;
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	if (unlikely(!timer))
		return -EINVAL;

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	omap_dm_timer_enable(timer);
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	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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	if (autoreload)
		l |= OMAP_TIMER_CTRL_AR;
	else
		l &= ~OMAP_TIMER_CTRL_AR;
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	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
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	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
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	/* Save the context */
	timer->context.tclr = l;
	timer->context.tldr = load;
	omap_dm_timer_disable(timer);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
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/* Optimized set_load which removes costly spin wait in timer_start */
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int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
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                            unsigned int load)
{
	u32 l;

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	if (unlikely(!timer))
		return -EINVAL;

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	omap_dm_timer_enable(timer);

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	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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	if (autoreload) {
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		l |= OMAP_TIMER_CTRL_AR;
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		omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
	} else {
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		l &= ~OMAP_TIMER_CTRL_AR;
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	}
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	l |= OMAP_TIMER_CTRL_ST;

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	__omap_dm_timer_load_start(timer, l, load, timer->posted);
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	/* Save the context */
	timer->context.tclr = l;
	timer->context.tldr = load;
	timer->context.tcrr = load;
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
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int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
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			     unsigned int match)
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{
	u32 l;

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	if (unlikely(!timer))
		return -EINVAL;

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	omap_dm_timer_enable(timer);
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	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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Timo Teras 已提交
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	if (enable)
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		l |= OMAP_TIMER_CTRL_CE;
	else
		l &= ~OMAP_TIMER_CTRL_CE;
	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
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	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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	/* Save the context */
	timer->context.tclr = l;
	timer->context.tmar = match;
	omap_dm_timer_disable(timer);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
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int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
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			   int toggle, int trigger)
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{
	u32 l;

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	if (unlikely(!timer))
		return -EINVAL;

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	omap_dm_timer_enable(timer);
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	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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	l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
	       OMAP_TIMER_CTRL_PT | (0x03 << 10));
	if (def_on)
		l |= OMAP_TIMER_CTRL_SCPWM;
	if (toggle)
		l |= OMAP_TIMER_CTRL_PT;
	l |= trigger << 10;
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	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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	/* Save the context */
	timer->context.tclr = l;
	omap_dm_timer_disable(timer);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
644

645
int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
646 647 648
{
	u32 l;

649 650 651
	if (unlikely(!timer))
		return -EINVAL;

652
	omap_dm_timer_enable(timer);
653
	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
654 655 656 657 658
	l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
	if (prescaler >= 0x00 && prescaler <= 0x07) {
		l |= OMAP_TIMER_CTRL_PRE;
		l |= prescaler << 2;
	}
659
	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
660 661 662 663

	/* Save the context */
	timer->context.tclr = l;
	omap_dm_timer_disable(timer);
664
	return 0;
665
}
666
EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
667

668
int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
669
				  unsigned int value)
670
{
671 672 673
	if (unlikely(!timer))
		return -EINVAL;

674
	omap_dm_timer_enable(timer);
675
	__omap_dm_timer_int_enable(timer, value);
676 677 678 679 680

	/* Save the context */
	timer->context.tier = value;
	timer->context.twer = value;
	omap_dm_timer_disable(timer);
681
	return 0;
682
}
683
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
684

685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701
/**
 * omap_dm_timer_set_int_disable - disable timer interrupts
 * @timer:	pointer to timer handle
 * @mask:	bit mask of interrupts to be disabled
 *
 * Disables the specified timer interrupts for a timer.
 */
int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
{
	u32 l = mask;

	if (unlikely(!timer))
		return -EINVAL;

	omap_dm_timer_enable(timer);

	if (timer->revision == 1)
702
		l = readl_relaxed(timer->irq_ena) & ~mask;
703

704
	writel_relaxed(l, timer->irq_dis);
705 706 707 708 709 710 711 712 713 714 715
	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);

	/* Save the context */
	timer->context.tier &= ~mask;
	timer->context.twer &= ~mask;
	omap_dm_timer_disable(timer);
	return 0;
}
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);

716
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
717
{
718 719
	unsigned int l;

720 721
	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
		pr_err("%s: timer not available or enabled.\n", __func__);
722 723 724
		return 0;
	}

725
	l = readl_relaxed(timer->irq_stat);
726 727

	return l;
728
}
729
EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
730

731
int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
732
{
733 734 735
	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
		return -EINVAL;

736
	__omap_dm_timer_write_status(timer, value);
737

738
	return 0;
739
}
740
EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
741

742
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
743
{
744 745
	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
		pr_err("%s: timer not iavailable or enabled.\n", __func__);
746 747 748
		return 0;
	}

749
	return __omap_dm_timer_read_counter(timer, timer->posted);
750
}
751
EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
752

753
int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
T
Timo Teras 已提交
754
{
755 756 757
	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
		pr_err("%s: timer not available or enabled.\n", __func__);
		return -EINVAL;
758 759
	}

760
	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
761 762 763

	/* Save the context */
	timer->context.tcrr = value;
764
	return 0;
T
Timo Teras 已提交
765
}
766
EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
T
Timo Teras 已提交
767

768
int omap_dm_timers_active(void)
769
{
770
	struct omap_dm_timer *timer;
771

772
	list_for_each_entry(timer, &omap_timer_list, node) {
773
		if (!timer->reserved)
774 775
			continue;

776
		if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
777
		    OMAP_TIMER_CTRL_ST) {
778
			return 1;
779
		}
780 781 782
	}
	return 0;
}
783
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
784

785 786
static const struct of_device_id omap_timer_match[];

787 788 789 790 791 792 793
/**
 * omap_dm_timer_probe - probe function called for every registered device
 * @pdev:	pointer to current timer platform device
 *
 * Called by driver framework at the end of device registration for all
 * timer devices.
 */
794
static int omap_dm_timer_probe(struct platform_device *pdev)
795 796 797
{
	unsigned long flags;
	struct omap_dm_timer *timer;
798 799
	struct resource *mem, *irq;
	struct device *dev = &pdev->dev;
800 801
	const struct of_device_id *match;
	const struct dmtimer_platform_data *pdata;
802
	int ret;
803 804 805

	match = of_match_device(of_match_ptr(omap_timer_match), dev);
	pdata = match ? match->data : dev->platform_data;
806

807
	if (!pdata && !dev->of_node) {
808
		dev_err(dev, "%s: no platform data.\n", __func__);
809 810 811 812 813
		return -ENODEV;
	}

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (unlikely(!irq)) {
814
		dev_err(dev, "%s: no IRQ resource.\n", __func__);
815 816 817 818 819
		return -ENODEV;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!mem)) {
820
		dev_err(dev, "%s: no memory resource.\n", __func__);
821 822 823
		return -ENODEV;
	}

824
	timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
825
	if (!timer) {
826 827
		dev_err(dev, "%s: memory alloc failed!\n", __func__);
		return  -ENOMEM;
828 829
	}

830
	timer->fclk = ERR_PTR(-ENODEV);
831 832 833
	timer->io_base = devm_ioremap_resource(dev, mem);
	if (IS_ERR(timer->io_base))
		return PTR_ERR(timer->io_base);
834

835 836 837 838 839 840 841 842 843 844 845 846 847
	if (dev->of_node) {
		if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
			timer->capability |= OMAP_TIMER_ALWON;
		if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
			timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
		if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
			timer->capability |= OMAP_TIMER_HAS_PWM;
		if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
			timer->capability |= OMAP_TIMER_SECURE;
	} else {
		timer->id = pdev->id;
		timer->capability = pdata->timer_capability;
		timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
848
		timer->get_context_loss_count = pdata->get_context_loss_count;
849 850
	}

851 852 853
	if (pdata)
		timer->errata = pdata->timer_errata;

854 855 856
	timer->irq = irq->start;
	timer->pdev = pdev;

857
	/* Skip pm_runtime_enable for OMAP1 */
858
	if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
859 860
		pm_runtime_enable(dev);
		pm_runtime_irq_safe(dev);
861 862
	}

863
	if (!timer->reserved) {
864 865 866 867 868 869
		ret = pm_runtime_get_sync(dev);
		if (ret < 0) {
			dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
				__func__);
			goto err_get_sync;
		}
870
		__omap_dm_timer_init_regs(timer);
871
		pm_runtime_put(dev);
872 873
	}

874 875 876 877 878
	/* add the timer element to the list */
	spin_lock_irqsave(&dm_timer_lock, flags);
	list_add_tail(&timer->node, &omap_timer_list);
	spin_unlock_irqrestore(&dm_timer_lock, flags);

879
	dev_dbg(dev, "Device Probed.\n");
880 881

	return 0;
882 883 884 885 886

err_get_sync:
	pm_runtime_put_noidle(dev);
	pm_runtime_disable(dev);
	return ret;
887 888 889 890 891 892 893 894 895 896
}

/**
 * omap_dm_timer_remove - cleanup a registered timer device
 * @pdev:	pointer to current timer platform device
 *
 * Called by driver framework whenever a timer device is unregistered.
 * In addition to freeing platform resources it also deletes the timer
 * entry from the local list.
 */
897
static int omap_dm_timer_remove(struct platform_device *pdev)
898 899 900 901 902 903 904
{
	struct omap_dm_timer *timer;
	unsigned long flags;
	int ret = -EINVAL;

	spin_lock_irqsave(&dm_timer_lock, flags);
	list_for_each_entry(timer, &omap_timer_list, node)
905 906
		if (!strcmp(dev_name(&timer->pdev->dev),
			    dev_name(&pdev->dev))) {
907 908 909 910 911 912
			list_del(&timer->node);
			ret = 0;
			break;
		}
	spin_unlock_irqrestore(&dm_timer_lock, flags);

913 914
	pm_runtime_disable(&pdev->dev);

915 916 917
	return ret;
}

918 919 920 921
static const struct dmtimer_platform_data omap3plus_pdata = {
	.timer_errata = OMAP_TIMER_ERRATA_I103_I767,
};

922
static const struct of_device_id omap_timer_match[] = {
923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945
	{
		.compatible = "ti,omap2420-timer",
	},
	{
		.compatible = "ti,omap3430-timer",
		.data = &omap3plus_pdata,
	},
	{
		.compatible = "ti,omap4430-timer",
		.data = &omap3plus_pdata,
	},
	{
		.compatible = "ti,omap5430-timer",
		.data = &omap3plus_pdata,
	},
	{
		.compatible = "ti,am335x-timer",
		.data = &omap3plus_pdata,
	},
	{
		.compatible = "ti,am335x-timer-1ms",
		.data = &omap3plus_pdata,
	},
946 947 948 949
	{},
};
MODULE_DEVICE_TABLE(of, omap_timer_match);

950 951
static struct platform_driver omap_dm_timer_driver = {
	.probe  = omap_dm_timer_probe,
952
	.remove = omap_dm_timer_remove,
953 954
	.driver = {
		.name   = "omap_timer",
955
		.of_match_table = of_match_ptr(omap_timer_match),
956 957 958 959
	},
};

early_platform_init("earlytimer", &omap_dm_timer_driver);
960
module_platform_driver(omap_dm_timer_driver);
961 962 963 964 965

MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Texas Instruments Inc");