probe.c 42.0 KB
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/*
 * probe.c - PCI detection and setup code
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/cpumask.h>
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#include <linux/pci-aspm.h>
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#include "pci.h"
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#define CARDBUS_LATENCY_TIMER	176	/* secondary latency timer */
#define CARDBUS_RESERVE_BUSNR	3

/* Ugh.  Need to stop exporting this to modules. */
LIST_HEAD(pci_root_buses);
EXPORT_SYMBOL(pci_root_buses);

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static int find_anything(struct device *dev, void *data)
{
	return 1;
}
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/*
 * Some device drivers need know if pci is initiated.
 * Basically, we think pci is not initiated when there
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 * is no device to be found on the pci_bus_type.
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 */
int no_pci_devices(void)
{
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	struct device *dev;
	int no_devices;
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	dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
	no_devices = (dev == NULL);
	put_device(dev);
	return no_devices;
}
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EXPORT_SYMBOL(no_pci_devices);

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/*
 * PCI Bus Class
 */
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static void release_pcibus_dev(struct device *dev)
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{
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	struct pci_bus *pci_bus = to_pci_bus(dev);
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	if (pci_bus->bridge)
		put_device(pci_bus->bridge);
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	pci_bus_remove_resources(pci_bus);
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	pci_release_bus_of_node(pci_bus);
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	kfree(pci_bus);
}

static struct class pcibus_class = {
	.name		= "pci_bus",
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	.dev_release	= &release_pcibus_dev,
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	.dev_attrs	= pcibus_dev_attrs,
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};

static int __init pcibus_class_init(void)
{
	return class_register(&pcibus_class);
}
postcore_initcall(pcibus_class_init);

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static u64 pci_size(u64 base, u64 maxbase, u64 mask)
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{
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	u64 size = mask & maxbase;	/* Find the significant bits */
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	if (!size)
		return 0;

	/* Get the lowest of them to find the decode size, and
	   from that the extent.  */
	size = (size & ~(size-1)) - 1;

	/* base == maxbase can be valid only if the BAR has
	   already been programmed with all 1s.  */
	if (base == maxbase && ((base | size) & mask) != mask)
		return 0;

	return size;
}

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static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
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{
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	u32 mem_type;
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	unsigned long flags;
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	if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
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		flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
		flags |= IORESOURCE_IO;
		return flags;
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	}
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	flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
	flags |= IORESOURCE_MEM;
	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
		flags |= IORESOURCE_PREFETCH;
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	mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
	switch (mem_type) {
	case PCI_BASE_ADDRESS_MEM_TYPE_32:
		break;
	case PCI_BASE_ADDRESS_MEM_TYPE_1M:
		dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
		break;
	case PCI_BASE_ADDRESS_MEM_TYPE_64:
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		flags |= IORESOURCE_MEM_64;
		break;
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	default:
		dev_warn(&dev->dev,
			 "mem unknown type %x treated as 32-bit BAR\n",
			 mem_type);
		break;
	}
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	return flags;
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}

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/**
 * pci_read_base - read a PCI BAR
 * @dev: the PCI device
 * @type: type of the BAR
 * @res: resource buffer to be filled in
 * @pos: BAR position in the config space
 *
 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
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 */
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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			struct resource *res, unsigned int pos)
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{
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	u32 l, sz, mask;
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	u16 orig_cmd;
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	mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
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	if (!dev->mmio_always_on) {
		pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
		pci_write_config_word(dev, PCI_COMMAND,
			orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
	}

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	res->name = pci_name(dev);

	pci_read_config_dword(dev, pos, &l);
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	pci_write_config_dword(dev, pos, l | mask);
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	pci_read_config_dword(dev, pos, &sz);
	pci_write_config_dword(dev, pos, l);

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	if (!dev->mmio_always_on)
		pci_write_config_word(dev, PCI_COMMAND, orig_cmd);

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	/*
	 * All bits set in sz means the device isn't working properly.
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	 * If the BAR isn't implemented, all bits must be 0.  If it's a
	 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
	 * 1 must be clear.
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	 */
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	if (!sz || sz == 0xffffffff)
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		goto fail;

	/*
	 * I don't know how l can have all bits set.  Copied from old code.
	 * Maybe it fixes a bug on some ancient platform.
	 */
	if (l == 0xffffffff)
		l = 0;

	if (type == pci_bar_unknown) {
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		res->flags = decode_bar(dev, l);
		res->flags |= IORESOURCE_SIZEALIGN;
		if (res->flags & IORESOURCE_IO) {
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			l &= PCI_BASE_ADDRESS_IO_MASK;
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			mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
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		} else {
			l &= PCI_BASE_ADDRESS_MEM_MASK;
			mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
		}
	} else {
		res->flags |= (l & IORESOURCE_ROM_ENABLE);
		l &= PCI_ROM_ADDRESS_MASK;
		mask = (u32)PCI_ROM_ADDRESS_MASK;
	}

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	if (res->flags & IORESOURCE_MEM_64) {
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		u64 l64 = l;
		u64 sz64 = sz;
		u64 mask64 = mask | (u64)~0 << 32;

		pci_read_config_dword(dev, pos + 4, &l);
		pci_write_config_dword(dev, pos + 4, ~0);
		pci_read_config_dword(dev, pos + 4, &sz);
		pci_write_config_dword(dev, pos + 4, l);

		l64 |= ((u64)l << 32);
		sz64 |= ((u64)sz << 32);

		sz64 = pci_size(l64, sz64, mask64);

		if (!sz64)
			goto fail;

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		if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
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			dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
				pos);
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			goto fail;
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		}

		if ((sizeof(resource_size_t) < 8) && l) {
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			/* Address above 32-bit boundary; disable the BAR */
			pci_write_config_dword(dev, pos, 0);
			pci_write_config_dword(dev, pos + 4, 0);
			res->start = 0;
			res->end = sz64;
		} else {
			res->start = l64;
			res->end = l64 + sz64;
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			dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
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				   pos, res);
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		}
	} else {
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		sz = pci_size(l, sz, mask);
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		if (!sz)
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			goto fail;

		res->start = l;
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		res->end = l + sz;
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		dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
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	}

 out:
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	return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
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 fail:
	res->flags = 0;
	goto out;
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}

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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
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	unsigned int pos, reg;
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	for (pos = 0; pos < howmany; pos++) {
		struct resource *res = &dev->resource[pos];
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		reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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		pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
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	}
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	if (rom) {
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		struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
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		dev->rom_base_reg = rom;
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		res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
				IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
				IORESOURCE_SIZEALIGN;
		__pci_read_base(dev, pci_bar_mem32, res, rom);
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	}
}

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static void __devinit pci_read_bridge_io(struct pci_bus *child)
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{
	struct pci_dev *dev = child->self;
	u8 io_base_lo, io_limit_lo;
	unsigned long base, limit;
	struct resource *res;

	res = child->resource[0];
	pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
	pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
	base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
	limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;

	if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
		u16 io_base_hi, io_limit_hi;
		pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
		pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
		base |= (io_base_hi << 16);
		limit |= (io_limit_hi << 16);
	}

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	if (base && base <= limit) {
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		res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
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		if (!res->start)
			res->start = base;
		if (!res->end)
			res->end = limit + 0xfff;
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		dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
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	}
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}

static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
{
	struct pci_dev *dev = child->self;
	u16 mem_base_lo, mem_limit_lo;
	unsigned long base, limit;
	struct resource *res;
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	res = child->resource[1];
	pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
	pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
	base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
	limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
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	if (base && base <= limit) {
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		res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
		res->start = base;
		res->end = limit + 0xfffff;
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		dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
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	}
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}

static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
{
	struct pci_dev *dev = child->self;
	u16 mem_base_lo, mem_limit_lo;
	unsigned long base, limit;
	struct resource *res;
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	res = child->resource[2];
	pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
	pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
	base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
	limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;

	if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
		u32 mem_base_hi, mem_limit_hi;
		pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
		pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);

		/*
		 * Some bridges set the base > limit by default, and some
		 * (broken) BIOSes do not initialize them.  If we find
		 * this, just assume they are not being used.
		 */
		if (mem_base_hi <= mem_limit_hi) {
#if BITS_PER_LONG == 64
			base |= ((long) mem_base_hi) << 32;
			limit |= ((long) mem_limit_hi) << 32;
#else
			if (mem_base_hi || mem_limit_hi) {
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				dev_err(&dev->dev, "can't handle 64-bit "
					"address space for bridge\n");
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				return;
			}
#endif
		}
	}
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	if (base && base <= limit) {
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		res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
					 IORESOURCE_MEM | IORESOURCE_PREFETCH;
		if (res->flags & PCI_PREF_RANGE_TYPE_64)
			res->flags |= IORESOURCE_MEM_64;
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		res->start = base;
		res->end = limit + 0xfffff;
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		dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
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	}
}

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void __devinit pci_read_bridge_bases(struct pci_bus *child)
{
	struct pci_dev *dev = child->self;
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	struct resource *res;
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	int i;

	if (pci_is_root_bus(child))	/* It's a host bus, nothing to read */
		return;

	dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
		 child->secondary, child->subordinate,
		 dev->transparent ? " (subtractive decode)" : "");

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	pci_bus_remove_resources(child);
	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
		child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];

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	pci_read_bridge_io(child);
	pci_read_bridge_mmio(child);
	pci_read_bridge_mmio_pref(child);
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	if (dev->transparent) {
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		pci_bus_for_each_resource(child->parent, res, i) {
			if (res) {
				pci_bus_add_resource(child, res,
						     PCI_SUBTRACTIVE_DECODE);
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				dev_printk(KERN_DEBUG, &dev->dev,
					   "  bridge window %pR (subtractive decode)\n",
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					   res);
			}
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		}
	}
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}

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static struct pci_bus * pci_alloc_bus(void)
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{
	struct pci_bus *b;

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	b = kzalloc(sizeof(*b), GFP_KERNEL);
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	if (b) {
		INIT_LIST_HEAD(&b->node);
		INIT_LIST_HEAD(&b->children);
		INIT_LIST_HEAD(&b->devices);
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		INIT_LIST_HEAD(&b->slots);
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		INIT_LIST_HEAD(&b->resources);
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		b->max_bus_speed = PCI_SPEED_UNKNOWN;
		b->cur_bus_speed = PCI_SPEED_UNKNOWN;
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	}
	return b;
}

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static unsigned char pcix_bus_speed[] = {
	PCI_SPEED_UNKNOWN,		/* 0 */
	PCI_SPEED_66MHz_PCIX,		/* 1 */
	PCI_SPEED_100MHz_PCIX,		/* 2 */
	PCI_SPEED_133MHz_PCIX,		/* 3 */
	PCI_SPEED_UNKNOWN,		/* 4 */
	PCI_SPEED_66MHz_PCIX_ECC,	/* 5 */
	PCI_SPEED_100MHz_PCIX_ECC,	/* 6 */
	PCI_SPEED_133MHz_PCIX_ECC,	/* 7 */
	PCI_SPEED_UNKNOWN,		/* 8 */
	PCI_SPEED_66MHz_PCIX_266,	/* 9 */
	PCI_SPEED_100MHz_PCIX_266,	/* A */
	PCI_SPEED_133MHz_PCIX_266,	/* B */
	PCI_SPEED_UNKNOWN,		/* C */
	PCI_SPEED_66MHz_PCIX_533,	/* D */
	PCI_SPEED_100MHz_PCIX_533,	/* E */
	PCI_SPEED_133MHz_PCIX_533	/* F */
};

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static unsigned char pcie_link_speed[] = {
	PCI_SPEED_UNKNOWN,		/* 0 */
	PCIE_SPEED_2_5GT,		/* 1 */
	PCIE_SPEED_5_0GT,		/* 2 */
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	PCIE_SPEED_8_0GT,		/* 3 */
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	PCI_SPEED_UNKNOWN,		/* 4 */
	PCI_SPEED_UNKNOWN,		/* 5 */
	PCI_SPEED_UNKNOWN,		/* 6 */
	PCI_SPEED_UNKNOWN,		/* 7 */
	PCI_SPEED_UNKNOWN,		/* 8 */
	PCI_SPEED_UNKNOWN,		/* 9 */
	PCI_SPEED_UNKNOWN,		/* A */
	PCI_SPEED_UNKNOWN,		/* B */
	PCI_SPEED_UNKNOWN,		/* C */
	PCI_SPEED_UNKNOWN,		/* D */
	PCI_SPEED_UNKNOWN,		/* E */
	PCI_SPEED_UNKNOWN		/* F */
};

void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
{
	bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
}
EXPORT_SYMBOL_GPL(pcie_update_link_speed);

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static unsigned char agp_speeds[] = {
	AGP_UNKNOWN,
	AGP_1X,
	AGP_2X,
	AGP_4X,
	AGP_8X
};

static enum pci_bus_speed agp_speed(int agp3, int agpstat)
{
	int index = 0;

	if (agpstat & 4)
		index = 3;
	else if (agpstat & 2)
		index = 2;
	else if (agpstat & 1)
		index = 1;
	else
		goto out;
	
	if (agp3) {
		index += 2;
		if (index == 5)
			index = 0;
	}

 out:
	return agp_speeds[index];
}


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static void pci_set_bus_speed(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	int pos;

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	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
	if (!pos)
		pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
	if (pos) {
		u32 agpstat, agpcmd;

		pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
		bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);

		pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
		bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
	}

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	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
	if (pos) {
		u16 status;
		enum pci_bus_speed max;
		pci_read_config_word(bridge, pos + 2, &status);

		if (status & 0x8000) {
			max = PCI_SPEED_133MHz_PCIX_533;
		} else if (status & 0x4000) {
			max = PCI_SPEED_133MHz_PCIX_266;
		} else if (status & 0x0002) {
			if (((status >> 12) & 0x3) == 2) {
				max = PCI_SPEED_133MHz_PCIX_ECC;
			} else {
				max = PCI_SPEED_133MHz_PCIX;
			}
		} else {
			max = PCI_SPEED_66MHz_PCIX;
		}

		bus->max_bus_speed = max;
		bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];

		return;
	}

	pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
	if (pos) {
		u32 linkcap;
		u16 linksta;

		pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
		bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];

		pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
		pcie_update_link_speed(bus, linksta);
	}
}


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static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
					   struct pci_dev *bridge, int busnr)
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{
	struct pci_bus *child;
	int i;

	/*
	 * Allocate a new bus, and inherit stuff from the parent..
	 */
	child = pci_alloc_bus();
	if (!child)
		return NULL;

	child->parent = parent;
	child->ops = parent->ops;
	child->sysdata = parent->sysdata;
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	child->bus_flags = parent->bus_flags;
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	/* initialize some portions of the bus device, but don't register it
	 * now as the parent is not properly set up yet.  This device will get
	 * registered later in pci_bus_add_devices()
	 */
	child->dev.class = &pcibus_class;
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	dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
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	/*
	 * Set up the primary, secondary and subordinate
	 * bus numbers.
	 */
	child->number = child->secondary = busnr;
	child->primary = parent->secondary;
	child->subordinate = 0xff;

580 581 582 583 584
	if (!bridge)
		return child;

	child->self = bridge;
	child->bridge = get_device(&bridge->dev);
585
	pci_set_bus_of_node(child);
586 587
	pci_set_bus_speed(child);

L
Linus Torvalds 已提交
588
	/* Set up default resource pointers and names.. */
589
	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
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590 591 592 593 594 595 596 597
		child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
		child->resource[i]->name = child->name;
	}
	bridge->subordinate = child;

	return child;
}

598
struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
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{
	struct pci_bus *child;

	child = pci_alloc_child_bus(parent, dev, busnr);
603
	if (child) {
604
		down_write(&pci_bus_sem);
L
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605
		list_add_tail(&child->node, &parent->children);
606
		up_write(&pci_bus_sem);
607
	}
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	return child;
}

611
static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
612 613
{
	struct pci_bus *parent = child->parent;
614 615 616 617 618 619

	/* Attempts to fix that up are really dangerous unless
	   we're going to re-assign all bus numbers. */
	if (!pcibios_assign_all_busses())
		return;

620 621 622 623 624 625 626
	while (parent->parent && parent->subordinate < max) {
		parent->subordinate = max;
		pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
		parent = parent->parent;
	}
}

L
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627 628 629 630 631 632 633 634 635 636
/*
 * If it's a bridge, configure it and scan the bus behind it.
 * For CardBus bridges, we don't scan behind as the devices will
 * be handled by the bridge driver itself.
 *
 * We need to process bridges in two passes -- first we scan those
 * already configured by the BIOS and after we are done with all of
 * them, we proceed to assigning numbers to the remaining buses in
 * order to avoid overlaps between old and new bus numbers.
 */
637
int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
L
Linus Torvalds 已提交
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{
	struct pci_bus *child;
	int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
641
	u32 buses, i, j = 0;
L
Linus Torvalds 已提交
642
	u16 bctl;
643
	u8 primary, secondary, subordinate;
644
	int broken = 0;
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Linus Torvalds 已提交
645 646

	pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
647 648 649
	primary = buses & 0xFF;
	secondary = (buses >> 8) & 0xFF;
	subordinate = (buses >> 16) & 0xFF;
L
Linus Torvalds 已提交
650

651 652
	dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
		secondary, subordinate, pass);
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653

654 655
	/* Check if setup is sensible at all */
	if (!pass &&
656
	    (primary != bus->number || secondary <= bus->number)) {
657 658 659 660
		dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
		broken = 1;
	}

L
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661 662 663 664 665 666
	/* Disable MasterAbortMode during probing to avoid reporting
	   of bus errors (in some architectures) */ 
	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
	pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
			      bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);

667 668 669
	if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
	    !is_cardbus && !broken) {
		unsigned int cmax;
L
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		/*
		 * Bus already configured by firmware, process it in the first
		 * pass and just note the configuration.
		 */
		if (pass)
675
			goto out;
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676 677 678

		/*
		 * If we already got to this bus through a different bridge,
A
Alex Chiang 已提交
679 680 681 682
		 * don't re-add it. This can happen with the i450NX chipset.
		 *
		 * However, we continue to descend down the hierarchy and
		 * scan remaining child buses.
L
Linus Torvalds 已提交
683
		 */
684
		child = pci_find_bus(pci_domain_nr(bus), secondary);
A
Alex Chiang 已提交
685
		if (!child) {
686
			child = pci_add_new_bus(bus, dev, secondary);
A
Alex Chiang 已提交
687 688
			if (!child)
				goto out;
689 690
			child->primary = primary;
			child->subordinate = subordinate;
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Alex Chiang 已提交
691
			child->bridge_ctl = bctl;
L
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		}

		cmax = pci_scan_child_bus(child);
		if (cmax > max)
			max = cmax;
		if (child->subordinate > max)
			max = child->subordinate;
	} else {
		/*
		 * We need to assign a number to this bus which we always
		 * do in the second pass.
		 */
704
		if (!pass) {
705
			if (pcibios_assign_all_busses() || broken)
706 707 708 709 710 711 712 713
				/* Temporarily disable forwarding of the
				   configuration cycles on all bridges in
				   this bus segment to avoid possible
				   conflicts in the second pass between two
				   bridges programmed with overlapping
				   bus ranges. */
				pci_write_config_dword(dev, PCI_PRIMARY_BUS,
						       buses & ~0xffffff);
714
			goto out;
715
		}
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		/* Clear errors */
		pci_write_config_word(dev, PCI_STATUS, 0xffff);

720
		/* Prevent assigning a bus number that already exists.
721 722 723 724 725 726 727 728
		 * This can happen when a bridge is hot-plugged, so in
		 * this case we only re-scan this bus. */
		child = pci_find_bus(pci_domain_nr(bus), max+1);
		if (!child) {
			child = pci_add_new_bus(bus, dev, ++max);
			if (!child)
				goto out;
		}
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		buses = (buses & 0xff000000)
		      | ((unsigned int)(child->primary)     <<  0)
		      | ((unsigned int)(child->secondary)   <<  8)
		      | ((unsigned int)(child->subordinate) << 16);

		/*
		 * yenta.c forces a secondary latency timer of 176.
		 * Copy that behaviour here.
		 */
		if (is_cardbus) {
			buses &= ~0xff000000;
			buses |= CARDBUS_LATENCY_TIMER << 24;
		}
742

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		/*
		 * We need to blast all three values with a single write.
		 */
		pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);

		if (!is_cardbus) {
749
			child->bridge_ctl = bctl;
750 751 752 753 754 755 756
			/*
			 * Adjust subordinate busnr in parent buses.
			 * We do this before scanning for children because
			 * some devices may not be detected if the bios
			 * was lazy.
			 */
			pci_fixup_parent_subordinate_busnr(child, max);
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			/* Now we can scan all subordinate buses... */
			max = pci_scan_child_bus(child);
759 760 761 762 763
			/*
			 * now fix it up again since we have found
			 * the real value of max.
			 */
			pci_fixup_parent_subordinate_busnr(child, max);
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Linus Torvalds 已提交
764 765 766 767 768 769
		} else {
			/*
			 * For CardBus bridges, we leave 4 bus numbers
			 * as cards with a PCI-to-PCI bridge can be
			 * inserted later.
			 */
770 771
			for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
				struct pci_bus *parent = bus;
772 773 774
				if (pci_find_bus(pci_domain_nr(bus),
							max+i+1))
					break;
775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792
				while (parent->parent) {
					if ((!pcibios_assign_all_busses()) &&
					    (parent->subordinate > max) &&
					    (parent->subordinate <= max+i)) {
						j = 1;
					}
					parent = parent->parent;
				}
				if (j) {
					/*
					 * Often, there are two cardbus bridges
					 * -- try to leave one valid bus number
					 * for each one.
					 */
					i /= 2;
					break;
				}
			}
793
			max += i;
794
			pci_fixup_parent_subordinate_busnr(child, max);
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795 796 797 798 799 800 801 802
		}
		/*
		 * Set the subordinate bus number to its real value.
		 */
		child->subordinate = max;
		pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
	}

803 804 805
	sprintf(child->name,
		(is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
		pci_domain_nr(bus), child->number);
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Linus Torvalds 已提交
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807
	/* Has only triggered on CardBus, fixup is in yenta_socket */
808 809 810 811 812
	while (bus->parent) {
		if ((child->subordinate > bus->subordinate) ||
		    (child->number > bus->subordinate) ||
		    (child->number < bus->number) ||
		    (child->subordinate < bus->number)) {
813 814
			dev_info(&child->dev, "[bus %02x-%02x] %s "
				"hidden behind%s bridge %s [bus %02x-%02x]\n",
815 816 817
				child->number, child->subordinate,
				(bus->number > child->subordinate &&
				 bus->subordinate < child->number) ?
818 819
					"wholly" : "partially",
				bus->self->transparent ? " transparent" : "",
820
				dev_name(&bus->dev),
821
				bus->number, bus->subordinate);
822 823 824 825
		}
		bus = bus->parent;
	}

826 827 828
out:
	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);

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	return max;
}

/*
 * Read interrupt line and base address registers.
 * The architecture-dependent code can tweak these, of course.
 */
static void pci_read_irq(struct pci_dev *dev)
{
	unsigned char irq;

	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
841
	dev->pin = irq;
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	if (irq)
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	dev->irq = irq;
}

847
void set_pcie_port_type(struct pci_dev *pdev)
Y
Yu Zhao 已提交
848 849 850 851 852 853 854 855
{
	int pos;
	u16 reg16;

	pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
	if (!pos)
		return;
	pdev->is_pcie = 1;
856
	pdev->pcie_cap = pos;
Y
Yu Zhao 已提交
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	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
	pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
859 860
	pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
	pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Y
Yu Zhao 已提交
861 862
}

863
void set_pcie_hotplug_bridge(struct pci_dev *pdev)
864 865 866 867 868
{
	int pos;
	u16 reg16;
	u32 reg32;

869
	pos = pci_pcie_cap(pdev);
870 871 872 873 874 875 876 877 878 879
	if (!pos)
		return;
	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
	if (!(reg16 & PCI_EXP_FLAGS_SLOT))
		return;
	pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
	if (reg32 & PCI_EXP_SLTCAP_HPC)
		pdev->is_hotplug_bridge = 1;
}

880
#define LEGACY_IO_RESOURCE	(IORESOURCE_IO | IORESOURCE_PCI_FIXED)
881

L
Linus Torvalds 已提交
882 883 884 885 886 887 888
/**
 * pci_setup_device - fill in class and map information of a device
 * @dev: the device structure to fill
 *
 * Initialize the device structure with information about the device's 
 * vendor,class,memory and IO-space addresses,IRQ lines etc.
 * Called at initialisation of the PCI subsystem and by CardBus services.
Y
Yu Zhao 已提交
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 * Returns 0 on success and negative if unknown type of device (not normal,
 * bridge or CardBus).
L
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891
 */
Y
Yu Zhao 已提交
892
int pci_setup_device(struct pci_dev *dev)
L
Linus Torvalds 已提交
893 894
{
	u32 class;
Y
Yu Zhao 已提交
895 896
	u8 hdr_type;
	struct pci_slot *slot;
897
	int pos = 0;
Y
Yu Zhao 已提交
898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916

	if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
		return -EIO;

	dev->sysdata = dev->bus->sysdata;
	dev->dev.parent = dev->bus->bridge;
	dev->dev.bus = &pci_bus_type;
	dev->hdr_type = hdr_type & 0x7f;
	dev->multifunction = !!(hdr_type & 0x80);
	dev->error_state = pci_channel_io_normal;
	set_pcie_port_type(dev);

	list_for_each_entry(slot, &dev->bus->slots, list)
		if (PCI_SLOT(dev->devfn) == slot->number)
			dev->slot = slot;

	/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
	   set this higher, assuming the system even supports it.  */
	dev->dma_mask = 0xffffffff;
L
Linus Torvalds 已提交
917

918 919 920
	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
		     dev->bus->number, PCI_SLOT(dev->devfn),
		     PCI_FUNC(dev->devfn));
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Linus Torvalds 已提交
921 922

	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
A
Auke Kok 已提交
923
	dev->revision = class & 0xff;
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924 925 926 927
	class >>= 8;				    /* upper 3 bytes */
	dev->class = class;
	class >>= 8;

B
Bjorn Helgaas 已提交
928 929
	dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
		   dev->vendor, dev->device, dev->hdr_type, class);
L
Linus Torvalds 已提交
930

931 932 933
	/* need to have dev->class ready */
	dev->cfg_size = pci_cfg_space_size(dev);

L
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934
	/* "Unknown power state" */
935
	dev->current_state = PCI_UNKNOWN;
L
Linus Torvalds 已提交
936 937 938

	/* Early fixups, before probing the BARs */
	pci_fixup_device(pci_fixup_early, dev);
939 940
	/* device class may be changed after fixup */
	class = dev->class >> 8;
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Linus Torvalds 已提交
941 942 943 944 945 946 947 948 949

	switch (dev->hdr_type) {		    /* header type */
	case PCI_HEADER_TYPE_NORMAL:		    /* standard header */
		if (class == PCI_CLASS_BRIDGE_PCI)
			goto bad;
		pci_read_irq(dev);
		pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
		pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
		pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
950 951 952 953 954 955 956 957 958 959 960

		/*
		 *	Do the ugly legacy mode stuff here rather than broken chip
		 *	quirk code. Legacy mode ATA controllers have fixed
		 *	addresses. These are not always echoed in BAR0-3, and
		 *	BAR0-3 in a few cases contain junk!
		 */
		if (class == PCI_CLASS_STORAGE_IDE) {
			u8 progif;
			pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
			if ((progif & 1) == 0) {
961 962 963 964 965 966
				dev->resource[0].start = 0x1F0;
				dev->resource[0].end = 0x1F7;
				dev->resource[0].flags = LEGACY_IO_RESOURCE;
				dev->resource[1].start = 0x3F6;
				dev->resource[1].end = 0x3F6;
				dev->resource[1].flags = LEGACY_IO_RESOURCE;
967 968
			}
			if ((progif & 4) == 0) {
969 970 971 972 973 974
				dev->resource[2].start = 0x170;
				dev->resource[2].end = 0x177;
				dev->resource[2].flags = LEGACY_IO_RESOURCE;
				dev->resource[3].start = 0x376;
				dev->resource[3].end = 0x376;
				dev->resource[3].flags = LEGACY_IO_RESOURCE;
975 976
			}
		}
L
Linus Torvalds 已提交
977 978 979 980 981 982 983 984
		break;

	case PCI_HEADER_TYPE_BRIDGE:		    /* bridge header */
		if (class != PCI_CLASS_BRIDGE_PCI)
			goto bad;
		/* The PCI-to-PCI bridge spec requires that subtractive
		   decoding (i.e. transparent) bridge must have programming
		   interface code of 0x01. */ 
985
		pci_read_irq(dev);
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Linus Torvalds 已提交
986 987
		dev->transparent = ((dev->class & 0xff) == 1);
		pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
988
		set_pcie_hotplug_bridge(dev);
989 990 991 992 993
		pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
		if (pos) {
			pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
			pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
		}
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994 995 996 997 998 999 1000 1001 1002 1003 1004 1005
		break;

	case PCI_HEADER_TYPE_CARDBUS:		    /* CardBus bridge header */
		if (class != PCI_CLASS_BRIDGE_CARDBUS)
			goto bad;
		pci_read_irq(dev);
		pci_read_bases(dev, 1, 0);
		pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
		pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
		break;

	default:				    /* unknown header */
1006 1007
		dev_err(&dev->dev, "unknown header type %02x, "
			"ignoring device\n", dev->hdr_type);
Y
Yu Zhao 已提交
1008
		return -EIO;
L
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1009 1010

	bad:
1011 1012
		dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
			"type %02x)\n", class, dev->hdr_type);
L
Linus Torvalds 已提交
1013 1014 1015 1016 1017 1018 1019
		dev->class = PCI_CLASS_NOT_DEFINED;
	}

	/* We found a fine healthy device, go go go... */
	return 0;
}

1020 1021 1022
static void pci_release_capabilities(struct pci_dev *dev)
{
	pci_vpd_release(dev);
1023
	pci_iov_release(dev);
1024 1025
}

L
Linus Torvalds 已提交
1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
/**
 * pci_release_dev - free a pci device structure when all users of it are finished.
 * @dev: device that's been disconnected
 *
 * Will be called only by the device core when all users of this pci device are
 * done.
 */
static void pci_release_dev(struct device *dev)
{
	struct pci_dev *pci_dev;

	pci_dev = to_pci_dev(dev);
1038
	pci_release_capabilities(pci_dev);
1039
	pci_release_of_node(pci_dev);
L
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1040 1041 1042 1043 1044
	kfree(pci_dev);
}

/**
 * pci_cfg_space_size - get the configuration space size of the PCI device.
R
Randy Dunlap 已提交
1045
 * @dev: PCI device
L
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1046 1047 1048 1049 1050 1051 1052 1053
 *
 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
 * access it.  Maybe we don't have a way to generate extended config space
 * accesses, or the device is behind a reverse Express bridge.  So we try
 * reading the dword at 0x100 which must either be 0 or a valid extended
 * capability header.
 */
1054
int pci_cfg_space_size_ext(struct pci_dev *dev)
L
Linus Torvalds 已提交
1055 1056
{
	u32 status;
1057
	int pos = PCI_CFG_SPACE_SIZE;
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1058

1059
	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
		goto fail;
	if (status == 0xffffffff)
		goto fail;

	return PCI_CFG_SPACE_EXP_SIZE;

 fail:
	return PCI_CFG_SPACE_SIZE;
}

int pci_cfg_space_size(struct pci_dev *dev)
{
	int pos;
	u32 status;
1074 1075 1076 1077 1078
	u16 class;

	class = dev->class >> 8;
	if (class == PCI_CLASS_BRIDGE_HOST)
		return pci_cfg_space_size_ext(dev);
1079

1080
	pos = pci_pcie_cap(dev);
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1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
	if (!pos) {
		pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
		if (!pos)
			goto fail;

		pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
		if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
			goto fail;
	}

1091
	return pci_cfg_space_size_ext(dev);
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 fail:
	return PCI_CFG_SPACE_SIZE;
}

static void pci_release_bus_bridge_dev(struct device *dev)
{
	kfree(dev);
}

1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115
struct pci_dev *alloc_pci_dev(void)
{
	struct pci_dev *dev;

	dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
	if (!dev)
		return NULL;

	INIT_LIST_HEAD(&dev->bus_list);

	return dev;
}
EXPORT_SYMBOL(alloc_pci_dev);

L
Linus Torvalds 已提交
1116 1117 1118 1119
/*
 * Read the config data for a PCI device, sanity-check it
 * and fill in the dev structure...
 */
1120
static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
L
Linus Torvalds 已提交
1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141
{
	struct pci_dev *dev;
	u32 l;
	int delay = 1;

	if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
		return NULL;

	/* some broken boards return 0 or ~0 if a slot is empty: */
	if (l == 0xffffffff || l == 0x00000000 ||
	    l == 0x0000ffff || l == 0xffff0000)
		return NULL;

	/* Configuration request Retry Status */
	while (l == 0xffff0001) {
		msleep(delay);
		delay *= 2;
		if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
			return NULL;
		/* Card hasn't responded in 60 seconds?  Must be stuck. */
		if (delay > 60 * 1000) {
1142
			printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
L
Linus Torvalds 已提交
1143 1144 1145 1146 1147 1148 1149
					"responding\n", pci_domain_nr(bus),
					bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn));
			return NULL;
		}
	}

1150
	dev = alloc_pci_dev();
L
Linus Torvalds 已提交
1151 1152 1153 1154 1155 1156 1157
	if (!dev)
		return NULL;

	dev->bus = bus;
	dev->devfn = devfn;
	dev->vendor = l & 0xffff;
	dev->device = (l >> 16) & 0xffff;
1158

1159 1160
	pci_set_of_node(dev);

Y
Yu Zhao 已提交
1161
	if (pci_setup_device(dev)) {
L
Linus Torvalds 已提交
1162 1163 1164 1165 1166 1167 1168
		kfree(dev);
		return NULL;
	}

	return dev;
}

1169 1170 1171 1172 1173
static void pci_init_capabilities(struct pci_dev *dev)
{
	/* MSI/MSI-X list */
	pci_msi_init_pci_dev(dev);

1174 1175 1176
	/* Buffers for saving PCIe and PCI-X capabilities */
	pci_allocate_cap_save_buffers(dev);

1177 1178
	/* Power Management */
	pci_pm_init(dev);
1179
	platform_pci_wakeup_init(dev);
1180 1181 1182

	/* Vital Product Data */
	pci_vpd_pci22_init(dev);
Y
Yu Zhao 已提交
1183 1184 1185

	/* Alternative Routing-ID Forwarding */
	pci_enable_ari(dev);
1186 1187 1188

	/* Single Root I/O Virtualization */
	pci_iov_init(dev);
1189 1190

	/* Enable ACS P2P upstream forwarding */
C
Chris Wright 已提交
1191
	pci_enable_acs(dev);
1192 1193
}

1194
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
L
Linus Torvalds 已提交
1195
{
1196 1197 1198
	device_initialize(&dev->dev);
	dev->dev.release = pci_release_dev;
	pci_dev_get(dev);
L
Linus Torvalds 已提交
1199

1200
	dev->dev.dma_mask = &dev->dma_mask;
1201
	dev->dev.dma_parms = &dev->dma_parms;
1202
	dev->dev.coherent_dma_mask = 0xffffffffull;
L
Linus Torvalds 已提交
1203

1204
	pci_set_dma_max_seg_size(dev, 65536);
1205
	pci_set_dma_seg_boundary(dev, 0xffffffff);
1206

L
Linus Torvalds 已提交
1207 1208 1209
	/* Fix up broken headers */
	pci_fixup_device(pci_fixup_header, dev);

1210 1211 1212
	/* Clear the state_saved flag. */
	dev->state_saved = false;

1213 1214
	/* Initialize various capabilities */
	pci_init_capabilities(dev);
1215

L
Linus Torvalds 已提交
1216 1217 1218 1219
	/*
	 * Add the device to our list of discovered devices
	 * and the bus list for fixup functions, etc.
	 */
1220
	down_write(&pci_bus_sem);
L
Linus Torvalds 已提交
1221
	list_add_tail(&dev->bus_list, &bus->devices);
1222
	up_write(&pci_bus_sem);
1223 1224
}

1225
struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1226 1227 1228
{
	struct pci_dev *dev;

T
Trent Piepho 已提交
1229 1230 1231 1232 1233 1234
	dev = pci_get_slot(bus, devfn);
	if (dev) {
		pci_dev_put(dev);
		return dev;
	}

1235 1236 1237 1238 1239
	dev = pci_scan_device(bus, devfn);
	if (!dev)
		return NULL;

	pci_device_add(dev, bus);
L
Linus Torvalds 已提交
1240 1241 1242

	return dev;
}
1243
EXPORT_SYMBOL(pci_scan_single_device);
L
Linus Torvalds 已提交
1244

M
Matthew Wilcox 已提交
1245 1246 1247
static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
{
	u16 cap;
1248 1249 1250 1251 1252 1253
	unsigned pos, next_fn;

	if (!dev)
		return 0;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
M
Matthew Wilcox 已提交
1254 1255 1256
	if (!pos)
		return 0;
	pci_read_config_word(dev, pos + 4, &cap);
1257 1258 1259 1260
	next_fn = cap >> 8;
	if (next_fn <= fn)
		return 0;
	return next_fn;
M
Matthew Wilcox 已提交
1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283
}

static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
{
	return (fn + 1) % 8;
}

static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
{
	return 0;
}

static int only_one_child(struct pci_bus *bus)
{
	struct pci_dev *parent = bus->self;
	if (!parent || !pci_is_pcie(parent))
		return 0;
	if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
	    parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
		return 1;
	return 0;
}

L
Linus Torvalds 已提交
1284 1285 1286 1287 1288 1289 1290
/**
 * pci_scan_slot - scan a PCI slot on a bus for devices.
 * @bus: PCI bus to scan
 * @devfn: slot number to scan (must have zero function.)
 *
 * Scan a PCI slot on the specified PCI bus for devices, adding
 * discovered devices to the @bus->devices list.  New devices
1291
 * will not have is_added set.
1292 1293
 *
 * Returns the number of new devices found.
L
Linus Torvalds 已提交
1294
 */
1295
int pci_scan_slot(struct pci_bus *bus, int devfn)
L
Linus Torvalds 已提交
1296
{
M
Matthew Wilcox 已提交
1297
	unsigned fn, nr = 0;
1298
	struct pci_dev *dev;
M
Matthew Wilcox 已提交
1299 1300 1301 1302
	unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;

	if (only_one_child(bus) && (devfn > 0))
		return 0; /* Already scanned the entire slot */
L
Linus Torvalds 已提交
1303

1304
	dev = pci_scan_single_device(bus, devfn);
1305 1306 1307
	if (!dev)
		return 0;
	if (!dev->is_added)
1308 1309
		nr++;

M
Matthew Wilcox 已提交
1310 1311
	if (pci_ari_enabled(bus))
		next_fn = next_ari_fn;
1312
	else if (dev->multifunction)
M
Matthew Wilcox 已提交
1313 1314 1315 1316 1317 1318 1319 1320
		next_fn = next_trad_fn;

	for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
		dev = pci_scan_single_device(bus, devfn + fn);
		if (dev) {
			if (!dev->is_added)
				nr++;
			dev->multifunction = 1;
L
Linus Torvalds 已提交
1321 1322
		}
	}
S
Shaohua Li 已提交
1323

1324 1325
	/* only one slot has pcie device */
	if (bus->self && nr)
S
Shaohua Li 已提交
1326 1327
		pcie_aspm_init_link_state(bus->self);

L
Linus Torvalds 已提交
1328 1329 1330
	return nr;
}

1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473
static int pcie_find_smpss(struct pci_dev *dev, void *data)
{
	u8 *smpss = data;

	if (!pci_is_pcie(dev))
		return 0;

	/* For PCIE hotplug enabled slots not connected directly to a
	 * PCI-E root port, there can be problems when hotplugging
	 * devices.  This is due to the possibility of hotplugging a
	 * device into the fabric with a smaller MPS that the devices
	 * currently running have configured.  Modifying the MPS on the
	 * running devices could cause a fatal bus error due to an
	 * incoming frame being larger than the newly configured MPS.
	 * To work around this, the MPS for the entire fabric must be
	 * set to the minimum size.  Any devices hotplugged into this
	 * fabric will have the minimum MPS set.  If the PCI hotplug
	 * slot is directly connected to the root port and there are not
	 * other devices on the fabric (which seems to be the most
	 * common case), then this is not an issue and MPS discovery
	 * will occur as normal.
	 */
	if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
	    dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
		*smpss = 0;

	if (*smpss > dev->pcie_mpss)
		*smpss = dev->pcie_mpss;

	return 0;
}

static void pcie_write_mps(struct pci_dev *dev, int mps)
{
	int rc, dev_mpss;

	dev_mpss = 128 << dev->pcie_mpss;

	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
		if (dev->bus->self) {
			dev_dbg(&dev->bus->dev, "Bus MPSS %d\n",
				128 << dev->bus->self->pcie_mpss);

			/* For "MPS Force Max", the assumption is made that
			 * downstream communication will never be larger than
			 * the MRRS.  So, the MPS only needs to be configured
			 * for the upstream communication.  This being the case,
			 * walk from the top down and set the MPS of the child
			 * to that of the parent bus.
			 */
			mps = 128 << dev->bus->self->pcie_mpss;
			if (mps > dev_mpss)
				dev_warn(&dev->dev, "MPS configured higher than"
					 " maximum supported by the device.  If"
					 " a bus issue occurs, try running with"
					 " pci=pcie_bus_safe.\n");
		}

		dev->pcie_mpss = ffs(mps) - 8;
	}

	rc = pcie_set_mps(dev, mps);
	if (rc)
		dev_err(&dev->dev, "Failed attempting to set the MPS\n");
}

static void pcie_write_mrrs(struct pci_dev *dev, int mps)
{
	int rc, mrrs;

	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
		int dev_mpss = 128 << dev->pcie_mpss;

		/* For Max performance, the MRRS must be set to the largest
		 * supported value.  However, it cannot be configured larger
		 * than the MPS the device or the bus can support.  This assumes
		 * that the largest MRRS available on the device cannot be
		 * smaller than the device MPSS.
		 */
		mrrs = mps < dev_mpss ? mps : dev_mpss;
	} else
		/* In the "safe" case, configure the MRRS for fairness on the
		 * bus by making all devices have the same size
		 */
		mrrs = mps;


	/* MRRS is a R/W register.  Invalid values can be written, but a
	 * subsiquent read will verify if the value is acceptable or not.
	 * If the MRRS value provided is not acceptable (e.g., too large),
	 * shrink the value until it is acceptable to the HW.
 	 */
	while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
		rc = pcie_set_readrq(dev, mrrs);
		if (rc)
			dev_err(&dev->dev, "Failed attempting to set the MRRS\n");

		mrrs /= 2;
	}
}

static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
{
	int mps = 128 << *(u8 *)data;

	if (!pci_is_pcie(dev))
		return 0;

	dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
		 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));

	pcie_write_mps(dev, mps);
	pcie_write_mrrs(dev, mps);

	dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
		 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));

	return 0;
}

/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down,
 * parents then children fashion.  If this changes, then this code will not
 * work as designed.
 */
void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
{
	u8 smpss = mpss;

	if (!bus->self)
		return;

	if (!pci_is_pcie(bus->self))
		return;

	if (pcie_bus_config == PCIE_BUS_SAFE) {
		pcie_find_smpss(bus->self, &smpss);
		pci_walk_bus(bus, pcie_find_smpss, &smpss);
	}

	pcie_bus_configure_set(bus->self, &smpss);
	pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
}

1474
unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
L
Linus Torvalds 已提交
1475 1476 1477 1478
{
	unsigned int devfn, pass, max = bus->secondary;
	struct pci_dev *dev;

B
Bjorn Helgaas 已提交
1479
	dev_dbg(&bus->dev, "scanning bus\n");
L
Linus Torvalds 已提交
1480 1481 1482 1483 1484

	/* Go find them, Rover! */
	for (devfn = 0; devfn < 0x100; devfn += 8)
		pci_scan_slot(bus, devfn);

1485 1486 1487
	/* Reserve buses for SR-IOV capability. */
	max += pci_iov_bus_range(bus);

L
Linus Torvalds 已提交
1488 1489 1490 1491
	/*
	 * After performing arch-dependent fixup of the bus, look behind
	 * all PCI-to-PCI bridges on this bus.
	 */
A
Alex Chiang 已提交
1492
	if (!bus->is_added) {
B
Bjorn Helgaas 已提交
1493
		dev_dbg(&bus->dev, "fixups for bus\n");
A
Alex Chiang 已提交
1494 1495 1496 1497 1498
		pcibios_fixup_bus(bus);
		if (pci_is_root_bus(bus))
			bus->is_added = 1;
	}

L
Linus Torvalds 已提交
1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512
	for (pass=0; pass < 2; pass++)
		list_for_each_entry(dev, &bus->devices, bus_list) {
			if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
			    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
				max = pci_scan_bridge(bus, dev, max, pass);
		}

	/*
	 * We've scanned the bus and so we know all about what's on
	 * the other side of any bridges that may be on this bus plus
	 * any devices.
	 *
	 * Return how far we've got finding sub-buses.
	 */
B
Bjorn Helgaas 已提交
1513
	dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
L
Linus Torvalds 已提交
1514 1515 1516
	return max;
}

1517
struct pci_bus * pci_create_bus(struct device *parent,
1518
		int bus, struct pci_ops *ops, void *sysdata)
L
Linus Torvalds 已提交
1519 1520
{
	int error;
B
Bjorn Helgaas 已提交
1521
	struct pci_bus *b, *b2;
L
Linus Torvalds 已提交
1522 1523 1524 1525 1526 1527
	struct device *dev;

	b = pci_alloc_bus();
	if (!b)
		return NULL;

1528
	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
L
Linus Torvalds 已提交
1529 1530 1531 1532 1533 1534 1535 1536
	if (!dev){
		kfree(b);
		return NULL;
	}

	b->sysdata = sysdata;
	b->ops = ops;

B
Bjorn Helgaas 已提交
1537 1538
	b2 = pci_find_bus(pci_domain_nr(b), bus);
	if (b2) {
L
Linus Torvalds 已提交
1539
		/* If we already got to this bus through a different bridge, ignore it */
B
Bjorn Helgaas 已提交
1540
		dev_dbg(&b2->dev, "bus already known\n");
L
Linus Torvalds 已提交
1541 1542
		goto err_out;
	}
1543 1544

	down_write(&pci_bus_sem);
L
Linus Torvalds 已提交
1545
	list_add_tail(&b->node, &pci_root_buses);
1546
	up_write(&pci_bus_sem);
L
Linus Torvalds 已提交
1547 1548 1549

	dev->parent = parent;
	dev->release = pci_release_bus_bridge_dev;
1550
	dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
L
Linus Torvalds 已提交
1551 1552 1553 1554
	error = device_register(dev);
	if (error)
		goto dev_reg_err;
	b->bridge = get_device(dev);
1555
	device_enable_async_suspend(b->bridge);
1556
	pci_set_bus_of_node(b);
L
Linus Torvalds 已提交
1557

1558 1559 1560
	if (!parent)
		set_dev_node(b->bridge, pcibus_to_node(b));

1561 1562
	b->dev.class = &pcibus_class;
	b->dev.parent = b->bridge;
1563
	dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1564
	error = device_register(&b->dev);
L
Linus Torvalds 已提交
1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579
	if (error)
		goto class_dev_reg_err;

	/* Create legacy_io and legacy_mem files for this bus */
	pci_create_legacy_files(b);

	b->number = b->secondary = bus;
	b->resource[0] = &ioport_resource;
	b->resource[1] = &iomem_resource;

	return b;

class_dev_reg_err:
	device_unregister(dev);
dev_reg_err:
1580
	down_write(&pci_bus_sem);
L
Linus Torvalds 已提交
1581
	list_del(&b->node);
1582
	up_write(&pci_bus_sem);
L
Linus Torvalds 已提交
1583 1584 1585 1586 1587
err_out:
	kfree(dev);
	kfree(b);
	return NULL;
}
1588

1589
struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1590 1591 1592 1593 1594 1595 1596 1597 1598
		int bus, struct pci_ops *ops, void *sysdata)
{
	struct pci_bus *b;

	b = pci_create_bus(parent, bus, ops, sysdata);
	if (b)
		b->subordinate = pci_scan_child_bus(b);
	return b;
}
L
Linus Torvalds 已提交
1599 1600 1601
EXPORT_SYMBOL(pci_scan_bus_parented);

#ifdef CONFIG_HOTPLUG
A
Alex Chiang 已提交
1602 1603 1604 1605 1606 1607 1608 1609 1610
/**
 * pci_rescan_bus - scan a PCI bus for devices.
 * @bus: PCI bus to scan
 *
 * Scan a PCI bus and child buses for new devices, adds them,
 * and enables them.
 *
 * Returns the max number of subordinate bus discovered.
 */
1611
unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
A
Alex Chiang 已提交
1612 1613 1614 1615 1616 1617
{
	unsigned int max;
	struct pci_dev *dev;

	max = pci_scan_child_bus(bus);

A
Alex Chiang 已提交
1618
	down_read(&pci_bus_sem);
A
Alex Chiang 已提交
1619 1620 1621 1622 1623
	list_for_each_entry(dev, &bus->devices, bus_list)
		if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
		    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
			if (dev->subordinate)
				pci_bus_size_bridges(dev->subordinate);
A
Alex Chiang 已提交
1624
	up_read(&pci_bus_sem);
A
Alex Chiang 已提交
1625 1626 1627 1628 1629 1630 1631 1632 1633

	pci_bus_assign_resources(bus);
	pci_enable_bridges(bus);
	pci_bus_add_devices(bus);

	return max;
}
EXPORT_SYMBOL_GPL(pci_rescan_bus);

L
Linus Torvalds 已提交
1634 1635 1636 1637 1638
EXPORT_SYMBOL(pci_add_new_bus);
EXPORT_SYMBOL(pci_scan_slot);
EXPORT_SYMBOL(pci_scan_bridge);
EXPORT_SYMBOL_GPL(pci_scan_child_bus);
#endif
1639

1640
static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1641
{
1642 1643 1644
	const struct pci_dev *a = to_pci_dev(d_a);
	const struct pci_dev *b = to_pci_dev(d_b);

1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
	if      (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
	else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return  1;

	if      (a->bus->number < b->bus->number) return -1;
	else if (a->bus->number > b->bus->number) return  1;

	if      (a->devfn < b->devfn) return -1;
	else if (a->devfn > b->devfn) return  1;

	return 0;
}

1657
void __init pci_sort_breadthfirst(void)
1658
{
1659
	bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1660
}