ucc_geth.c 117.7 KB
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/*
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 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
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 *
 * Author: Shlomi Gridish <gridish@freescale.com>
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 *	   Li Yang <leoli@freescale.com>
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 *
 * Description:
 * QE UCC Gigabit Ethernet Driver
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/fsl_devices.h>
#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/workqueue.h>
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#include <asm/of_platform.h>
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#include <asm/uaccess.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/immap_qe.h>
#include <asm/qe.h>
#include <asm/ucc.h>
#include <asm/ucc_fast.h>

#include "ucc_geth.h"
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#include "ucc_geth_mii.h"
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#undef DEBUG

#define ugeth_printk(level, format, arg...)  \
        printk(level format "\n", ## arg)

#define ugeth_dbg(format, arg...)            \
        ugeth_printk(KERN_DEBUG , format , ## arg)
#define ugeth_err(format, arg...)            \
        ugeth_printk(KERN_ERR , format , ## arg)
#define ugeth_info(format, arg...)           \
        ugeth_printk(KERN_INFO , format , ## arg)
#define ugeth_warn(format, arg...)           \
        ugeth_printk(KERN_WARNING , format , ## arg)

#ifdef UGETH_VERBOSE_DEBUG
#define ugeth_vdbg ugeth_dbg
#else
#define ugeth_vdbg(fmt, args...) do { } while (0)
#endif				/* UGETH_VERBOSE_DEBUG */

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void uec_set_ethtool_ops(struct net_device *netdev);
	
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static DEFINE_SPINLOCK(ugeth_lock);

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static struct ucc_geth_info ugeth_primary_info = {
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	.uf_info = {
		    .bd_mem_part = MEM_PART_SYSTEM,
		    .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
		    .max_rx_buf_length = 1536,
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		    /* adjusted at startup if max-speed 1000 */
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		    .urfs = UCC_GETH_URFS_INIT,
		    .urfet = UCC_GETH_URFET_INIT,
		    .urfset = UCC_GETH_URFSET_INIT,
		    .utfs = UCC_GETH_UTFS_INIT,
		    .utfet = UCC_GETH_UTFET_INIT,
		    .utftt = UCC_GETH_UTFTT_INIT,
		    .ufpt = 256,
		    .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
		    .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
		    .tenc = UCC_FAST_TX_ENCODING_NRZ,
		    .renc = UCC_FAST_RX_ENCODING_NRZ,
		    .tcrc = UCC_FAST_16_BIT_CRC,
		    .synl = UCC_FAST_SYNC_LEN_NOT_USED,
		    },
	.numQueuesTx = 1,
	.numQueuesRx = 1,
	.extendedFilteringChainPointer = ((uint32_t) NULL),
	.typeorlen = 3072 /*1536 */ ,
	.nonBackToBackIfgPart1 = 0x40,
	.nonBackToBackIfgPart2 = 0x60,
	.miminumInterFrameGapEnforcement = 0x50,
	.backToBackInterFrameGap = 0x60,
	.mblinterval = 128,
	.nortsrbytetime = 5,
	.fracsiz = 1,
	.strictpriorityq = 0xff,
	.altBebTruncation = 0xa,
	.excessDefer = 1,
	.maxRetransmission = 0xf,
	.collisionWindow = 0x37,
	.receiveFlowControl = 1,
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	.transmitFlowControl = 1,
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	.maxGroupAddrInHash = 4,
	.maxIndAddrInHash = 4,
	.prel = 7,
	.maxFrameLength = 1518,
	.minFrameLength = 64,
	.maxD1Length = 1520,
	.maxD2Length = 1520,
	.vlantype = 0x8100,
	.ecamptr = ((uint32_t) NULL),
	.eventRegMask = UCCE_OTHER,
	.pausePeriod = 0xf000,
	.interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
	.bdRingLenTx = {
			TX_BD_RING_LEN,
			TX_BD_RING_LEN,
			TX_BD_RING_LEN,
			TX_BD_RING_LEN,
			TX_BD_RING_LEN,
			TX_BD_RING_LEN,
			TX_BD_RING_LEN,
			TX_BD_RING_LEN},

	.bdRingLenRx = {
			RX_BD_RING_LEN,
			RX_BD_RING_LEN,
			RX_BD_RING_LEN,
			RX_BD_RING_LEN,
			RX_BD_RING_LEN,
			RX_BD_RING_LEN,
			RX_BD_RING_LEN,
			RX_BD_RING_LEN},

	.numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
	.largestexternallookupkeysize =
	    QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
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	.statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
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	.vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
	.vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
	.rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
	.aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
	.padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
	.numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
	.numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
	.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
	.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
};

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static struct ucc_geth_info ugeth_info[8];
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#ifdef DEBUG
static void mem_disp(u8 *addr, int size)
{
	u8 *i;
	int size16Aling = (size >> 4) << 4;
	int size4Aling = (size >> 2) << 2;
	int notAlign = 0;
	if (size % 16)
		notAlign = 1;

	for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
		printk("0x%08x: %08x %08x %08x %08x\r\n",
		       (u32) i,
		       *((u32 *) (i)),
		       *((u32 *) (i + 4)),
		       *((u32 *) (i + 8)), *((u32 *) (i + 12)));
	if (notAlign == 1)
		printk("0x%08x: ", (u32) i);
	for (; (u32) i < (u32) addr + size4Aling; i += 4)
		printk("%08x ", *((u32 *) (i)));
	for (; (u32) i < (u32) addr + size; i++)
		printk("%02x", *((u8 *) (i)));
	if (notAlign == 1)
		printk("\r\n");
}
#endif /* DEBUG */

#ifdef CONFIG_UGETH_FILTERING
static void enqueue(struct list_head *node, struct list_head *lh)
{
	unsigned long flags;

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	spin_lock_irqsave(&ugeth_lock, flags);
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	list_add_tail(node, lh);
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	spin_unlock_irqrestore(&ugeth_lock, flags);
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}
#endif /* CONFIG_UGETH_FILTERING */

static struct list_head *dequeue(struct list_head *lh)
{
	unsigned long flags;

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	spin_lock_irqsave(&ugeth_lock, flags);
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	if (!list_empty(lh)) {
		struct list_head *node = lh->next;
		list_del(node);
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		spin_unlock_irqrestore(&ugeth_lock, flags);
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		return node;
	} else {
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		spin_unlock_irqrestore(&ugeth_lock, flags);
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		return NULL;
	}
}

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static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
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{
	struct sk_buff *skb = NULL;

	skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
				  UCC_GETH_RX_DATA_BUF_ALIGNMENT);

	if (skb == NULL)
		return NULL;

	/* We need the data buffer to be aligned properly.  We will reserve
	 * as many bytes as needed to align the data properly
	 */
	skb_reserve(skb,
		    UCC_GETH_RX_DATA_BUF_ALIGNMENT -
		    (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
					      1)));

	skb->dev = ugeth->dev;

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	out_be32(&((struct qe_bd *)bd)->buf,
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		      dma_map_single(NULL,
				     skb->data,
				     ugeth->ug_info->uf_info.max_rx_buf_length +
				     UCC_GETH_RX_DATA_BUF_ALIGNMENT,
				     DMA_FROM_DEVICE));

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	out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
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	return skb;
}

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static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
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{
	u8 *bd;
	u32 bd_status;
	struct sk_buff *skb;
	int i;

	bd = ugeth->p_rx_bd_ring[rxQ];
	i = 0;

	do {
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		bd_status = in_be32((u32*)bd);
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		skb = get_new_skb(ugeth, bd);

		if (!skb)	/* If can not allocate data buffer,
				abort. Cleanup will be elsewhere */
			return -ENOMEM;

		ugeth->rx_skbuff[rxQ][i] = skb;

		/* advance the BD pointer */
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		bd += sizeof(struct qe_bd);
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		i++;
	} while (!(bd_status & R_W));

	return 0;
}

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static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
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				  volatile u32 *p_start,
				  u8 num_entries,
				  u32 thread_size,
				  u32 thread_alignment,
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				  enum qe_risc_allocation risc,
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				  int skip_page_for_first_entry)
{
	u32 init_enet_offset;
	u8 i;
	int snum;

	for (i = 0; i < num_entries; i++) {
		if ((snum = qe_get_snum()) < 0) {
			ugeth_err("fill_init_enet_entries: Can not get SNUM.");
			return snum;
		}
		if ((i == 0) && skip_page_for_first_entry)
		/* First entry of Rx does not have page */
			init_enet_offset = 0;
		else {
			init_enet_offset =
			    qe_muram_alloc(thread_size, thread_alignment);
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			if (IS_ERR_VALUE(init_enet_offset)) {
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				ugeth_err
		("fill_init_enet_entries: Can not allocate DPRAM memory.");
				qe_put_snum((u8) snum);
				return -ENOMEM;
			}
		}
		*(p_start++) =
		    ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
		    | risc;
	}

	return 0;
}

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static int return_init_enet_entries(struct ucc_geth_private *ugeth,
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				    volatile u32 *p_start,
				    u8 num_entries,
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				    enum qe_risc_allocation risc,
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				    int skip_page_for_first_entry)
{
	u32 init_enet_offset;
	u8 i;
	int snum;

	for (i = 0; i < num_entries; i++) {
		/* Check that this entry was actually valid --
		needed in case failed in allocations */
		if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
			snum =
			    (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
			    ENET_INIT_PARAM_SNUM_SHIFT;
			qe_put_snum((u8) snum);
			if (!((i == 0) && skip_page_for_first_entry)) {
			/* First entry of Rx does not have page */
				init_enet_offset =
				    (in_be32(p_start) &
				     ENET_INIT_PARAM_PTR_MASK);
				qe_muram_free(init_enet_offset);
			}
			*(p_start++) = 0;	/* Just for cosmetics */
		}
	}

	return 0;
}

#ifdef DEBUG
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static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
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				  volatile u32 *p_start,
				  u8 num_entries,
				  u32 thread_size,
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				  enum qe_risc_allocation risc,
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				  int skip_page_for_first_entry)
{
	u32 init_enet_offset;
	u8 i;
	int snum;

	for (i = 0; i < num_entries; i++) {
		/* Check that this entry was actually valid --
		needed in case failed in allocations */
		if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
			snum =
			    (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
			    ENET_INIT_PARAM_SNUM_SHIFT;
			qe_put_snum((u8) snum);
			if (!((i == 0) && skip_page_for_first_entry)) {
			/* First entry of Rx does not have page */
				init_enet_offset =
				    (in_be32(p_start) &
				     ENET_INIT_PARAM_PTR_MASK);
				ugeth_info("Init enet entry %d:", i);
				ugeth_info("Base address: 0x%08x",
					   (u32)
					   qe_muram_addr(init_enet_offset));
				mem_disp(qe_muram_addr(init_enet_offset),
					 thread_size);
			}
			p_start++;
		}
	}

	return 0;
}
#endif

#ifdef CONFIG_UGETH_FILTERING
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static struct enet_addr_container *get_enet_addr_container(void)
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{
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	struct enet_addr_container *enet_addr_cont;
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	/* allocate memory */
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	enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
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	if (!enet_addr_cont) {
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		ugeth_err("%s: No memory for enet_addr_container object.",
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			  __FUNCTION__);
		return NULL;
	}

	return enet_addr_cont;
}
#endif /* CONFIG_UGETH_FILTERING */

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static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
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{
	kfree(enet_addr_cont);
}

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static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
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{
	out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
	out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
	out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
}

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#ifdef CONFIG_UGETH_FILTERING
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static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
                                u8 *p_enet_addr, u8 paddr_num)
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{
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	struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
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	if (!(paddr_num < NUM_OF_PADDRS)) {
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		ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
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		return -EINVAL;
	}

	p_82xx_addr_filt =
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	    (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
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	    addressfiltering;

	/* Ethernet frames are defined in Little Endian mode,    */
	/* therefore to insert the address we reverse the bytes. */
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	set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
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	return 0;
}
#endif /* CONFIG_UGETH_FILTERING */

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static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
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{
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	struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
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	if (!(paddr_num < NUM_OF_PADDRS)) {
		ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
		return -EINVAL;
	}

	p_82xx_addr_filt =
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	    (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
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	    addressfiltering;

	/* Writing address ff.ff.ff.ff.ff.ff disables address
	recognition for this register */
	out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
	out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
	out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);

	return 0;
}

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static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
                                u8 *p_enet_addr)
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{
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	struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
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	u32 cecr_subblock;

	p_82xx_addr_filt =
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	    (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
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	    addressfiltering;

	cecr_subblock =
	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);

	/* Ethernet frames are defined in Little Endian mode,
	therefor to insert */
	/* the address to the hash (Big Endian mode), we reverse the bytes.*/
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	set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
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	qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
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		     QE_CR_PROTOCOL_ETHERNET, 0);
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}

#ifdef CONFIG_UGETH_MAGIC_PACKET
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static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
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{
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	struct ucc_fast_private *uccf;
	struct ucc_geth *ug_regs;
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	u32 maccfg2, uccm;

	uccf = ugeth->uccf;
	ug_regs = ugeth->ug_regs;

	/* Enable interrupts for magic packet detection */
	uccm = in_be32(uccf->p_uccm);
	uccm |= UCCE_MPD;
	out_be32(uccf->p_uccm, uccm);

	/* Enable magic packet detection */
	maccfg2 = in_be32(&ug_regs->maccfg2);
	maccfg2 |= MACCFG2_MPE;
	out_be32(&ug_regs->maccfg2, maccfg2);
}

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static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
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{
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	struct ucc_fast_private *uccf;
	struct ucc_geth *ug_regs;
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	u32 maccfg2, uccm;

	uccf = ugeth->uccf;
	ug_regs = ugeth->ug_regs;

	/* Disable interrupts for magic packet detection */
	uccm = in_be32(uccf->p_uccm);
	uccm &= ~UCCE_MPD;
	out_be32(uccf->p_uccm, uccm);

	/* Disable magic packet detection */
	maccfg2 = in_be32(&ug_regs->maccfg2);
	maccfg2 &= ~MACCFG2_MPE;
	out_be32(&ug_regs->maccfg2, maccfg2);
}
#endif /* MAGIC_PACKET */

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static inline int compare_addr(u8 **addr1, u8 **addr2)
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{
	return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
}

#ifdef DEBUG
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static void get_statistics(struct ucc_geth_private *ugeth,
			   struct ucc_geth_tx_firmware_statistics *
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			   tx_firmware_statistics,
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			   struct ucc_geth_rx_firmware_statistics *
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			   rx_firmware_statistics,
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			   struct ucc_geth_hardware_statistics *hardware_statistics)
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{
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	struct ucc_fast *uf_regs;
	struct ucc_geth *ug_regs;
	struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
	struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
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	ug_regs = ugeth->ug_regs;
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	uf_regs = (struct ucc_fast *) ug_regs;
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	p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
	p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;

	/* Tx firmware only if user handed pointer and driver actually
	gathers Tx firmware statistics */
	if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
		tx_firmware_statistics->sicoltx =
		    in_be32(&p_tx_fw_statistics_pram->sicoltx);
		tx_firmware_statistics->mulcoltx =
		    in_be32(&p_tx_fw_statistics_pram->mulcoltx);
		tx_firmware_statistics->latecoltxfr =
		    in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
		tx_firmware_statistics->frabortduecol =
		    in_be32(&p_tx_fw_statistics_pram->frabortduecol);
		tx_firmware_statistics->frlostinmactxer =
		    in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
		tx_firmware_statistics->carriersenseertx =
		    in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
		tx_firmware_statistics->frtxok =
		    in_be32(&p_tx_fw_statistics_pram->frtxok);
		tx_firmware_statistics->txfrexcessivedefer =
		    in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
		tx_firmware_statistics->txpkts256 =
		    in_be32(&p_tx_fw_statistics_pram->txpkts256);
		tx_firmware_statistics->txpkts512 =
		    in_be32(&p_tx_fw_statistics_pram->txpkts512);
		tx_firmware_statistics->txpkts1024 =
		    in_be32(&p_tx_fw_statistics_pram->txpkts1024);
		tx_firmware_statistics->txpktsjumbo =
		    in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
	}

	/* Rx firmware only if user handed pointer and driver actually
	 * gathers Rx firmware statistics */
	if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
		int i;
		rx_firmware_statistics->frrxfcser =
		    in_be32(&p_rx_fw_statistics_pram->frrxfcser);
		rx_firmware_statistics->fraligner =
		    in_be32(&p_rx_fw_statistics_pram->fraligner);
		rx_firmware_statistics->inrangelenrxer =
		    in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
		rx_firmware_statistics->outrangelenrxer =
		    in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
		rx_firmware_statistics->frtoolong =
		    in_be32(&p_rx_fw_statistics_pram->frtoolong);
		rx_firmware_statistics->runt =
		    in_be32(&p_rx_fw_statistics_pram->runt);
		rx_firmware_statistics->verylongevent =
		    in_be32(&p_rx_fw_statistics_pram->verylongevent);
		rx_firmware_statistics->symbolerror =
		    in_be32(&p_rx_fw_statistics_pram->symbolerror);
		rx_firmware_statistics->dropbsy =
		    in_be32(&p_rx_fw_statistics_pram->dropbsy);
		for (i = 0; i < 0x8; i++)
			rx_firmware_statistics->res0[i] =
			    p_rx_fw_statistics_pram->res0[i];
		rx_firmware_statistics->mismatchdrop =
		    in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
		rx_firmware_statistics->underpkts =
		    in_be32(&p_rx_fw_statistics_pram->underpkts);
		rx_firmware_statistics->pkts256 =
		    in_be32(&p_rx_fw_statistics_pram->pkts256);
		rx_firmware_statistics->pkts512 =
		    in_be32(&p_rx_fw_statistics_pram->pkts512);
		rx_firmware_statistics->pkts1024 =
		    in_be32(&p_rx_fw_statistics_pram->pkts1024);
		rx_firmware_statistics->pktsjumbo =
		    in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
		rx_firmware_statistics->frlossinmacer =
		    in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
		rx_firmware_statistics->pausefr =
		    in_be32(&p_rx_fw_statistics_pram->pausefr);
		for (i = 0; i < 0x4; i++)
			rx_firmware_statistics->res1[i] =
			    p_rx_fw_statistics_pram->res1[i];
		rx_firmware_statistics->removevlan =
		    in_be32(&p_rx_fw_statistics_pram->removevlan);
		rx_firmware_statistics->replacevlan =
		    in_be32(&p_rx_fw_statistics_pram->replacevlan);
		rx_firmware_statistics->insertvlan =
		    in_be32(&p_rx_fw_statistics_pram->insertvlan);
	}

	/* Hardware only if user handed pointer and driver actually
	gathers hardware statistics */
	if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
		hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
		hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
		hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
		hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
		hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
		hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
		hardware_statistics->txok = in_be32(&ug_regs->txok);
		hardware_statistics->txcf = in_be16(&ug_regs->txcf);
		hardware_statistics->tmca = in_be32(&ug_regs->tmca);
		hardware_statistics->tbca = in_be32(&ug_regs->tbca);
		hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
		hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
		hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
		hardware_statistics->rmca = in_be32(&ug_regs->rmca);
		hardware_statistics->rbca = in_be32(&ug_regs->rbca);
	}
}

644
static void dump_bds(struct ucc_geth_private *ugeth)
645 646 647 648 649 650 651 652
{
	int i;
	int length;

	for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
		if (ugeth->p_tx_bd_ring[i]) {
			length =
			    (ugeth->ug_info->bdRingLenTx[i] *
653
			     sizeof(struct qe_bd));
654 655 656 657 658 659 660 661
			ugeth_info("TX BDs[%d]", i);
			mem_disp(ugeth->p_tx_bd_ring[i], length);
		}
	}
	for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
		if (ugeth->p_rx_bd_ring[i]) {
			length =
			    (ugeth->ug_info->bdRingLenRx[i] *
662
			     sizeof(struct qe_bd));
663 664 665 666 667 668
			ugeth_info("RX BDs[%d]", i);
			mem_disp(ugeth->p_rx_bd_ring[i], length);
		}
	}
}

669
static void dump_regs(struct ucc_geth_private *ugeth)
670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791
{
	int i;

	ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
	ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);

	ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->maccfg1,
		   in_be32(&ugeth->ug_regs->maccfg1));
	ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->maccfg2,
		   in_be32(&ugeth->ug_regs->maccfg2));
	ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->ipgifg,
		   in_be32(&ugeth->ug_regs->ipgifg));
	ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->hafdup,
		   in_be32(&ugeth->ug_regs->hafdup));
	ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->ifctl,
		   in_be32(&ugeth->ug_regs->ifctl));
	ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->ifstat,
		   in_be32(&ugeth->ug_regs->ifstat));
	ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->macstnaddr1,
		   in_be32(&ugeth->ug_regs->macstnaddr1));
	ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->macstnaddr2,
		   in_be32(&ugeth->ug_regs->macstnaddr2));
	ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->uempr,
		   in_be32(&ugeth->ug_regs->uempr));
	ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->utbipar,
		   in_be32(&ugeth->ug_regs->utbipar));
	ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
		   (u32) & ugeth->ug_regs->uescr,
		   in_be16(&ugeth->ug_regs->uescr));
	ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->tx64,
		   in_be32(&ugeth->ug_regs->tx64));
	ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->tx127,
		   in_be32(&ugeth->ug_regs->tx127));
	ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->tx255,
		   in_be32(&ugeth->ug_regs->tx255));
	ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rx64,
		   in_be32(&ugeth->ug_regs->rx64));
	ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rx127,
		   in_be32(&ugeth->ug_regs->rx127));
	ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rx255,
		   in_be32(&ugeth->ug_regs->rx255));
	ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->txok,
		   in_be32(&ugeth->ug_regs->txok));
	ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
		   (u32) & ugeth->ug_regs->txcf,
		   in_be16(&ugeth->ug_regs->txcf));
	ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->tmca,
		   in_be32(&ugeth->ug_regs->tmca));
	ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->tbca,
		   in_be32(&ugeth->ug_regs->tbca));
	ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rxfok,
		   in_be32(&ugeth->ug_regs->rxfok));
	ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rxbok,
		   in_be32(&ugeth->ug_regs->rxbok));
	ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rbyt,
		   in_be32(&ugeth->ug_regs->rbyt));
	ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rmca,
		   in_be32(&ugeth->ug_regs->rmca));
	ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->rbca,
		   in_be32(&ugeth->ug_regs->rbca));
	ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->scar,
		   in_be32(&ugeth->ug_regs->scar));
	ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
		   (u32) & ugeth->ug_regs->scam,
		   in_be32(&ugeth->ug_regs->scam));

	if (ugeth->p_thread_data_tx) {
		int numThreadsTxNumerical;
		switch (ugeth->ug_info->numThreadsTx) {
		case UCC_GETH_NUM_OF_THREADS_1:
			numThreadsTxNumerical = 1;
			break;
		case UCC_GETH_NUM_OF_THREADS_2:
			numThreadsTxNumerical = 2;
			break;
		case UCC_GETH_NUM_OF_THREADS_4:
			numThreadsTxNumerical = 4;
			break;
		case UCC_GETH_NUM_OF_THREADS_6:
			numThreadsTxNumerical = 6;
			break;
		case UCC_GETH_NUM_OF_THREADS_8:
			numThreadsTxNumerical = 8;
			break;
		default:
			numThreadsTxNumerical = 0;
			break;
		}

		ugeth_info("Thread data TXs:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_thread_data_tx);
		for (i = 0; i < numThreadsTxNumerical; i++) {
			ugeth_info("Thread data TX[%d]:", i);
			ugeth_info("Base address: 0x%08x",
				   (u32) & ugeth->p_thread_data_tx[i]);
			mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
792
				 sizeof(struct ucc_geth_thread_data_tx));
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		}
	}
	if (ugeth->p_thread_data_rx) {
		int numThreadsRxNumerical;
		switch (ugeth->ug_info->numThreadsRx) {
		case UCC_GETH_NUM_OF_THREADS_1:
			numThreadsRxNumerical = 1;
			break;
		case UCC_GETH_NUM_OF_THREADS_2:
			numThreadsRxNumerical = 2;
			break;
		case UCC_GETH_NUM_OF_THREADS_4:
			numThreadsRxNumerical = 4;
			break;
		case UCC_GETH_NUM_OF_THREADS_6:
			numThreadsRxNumerical = 6;
			break;
		case UCC_GETH_NUM_OF_THREADS_8:
			numThreadsRxNumerical = 8;
			break;
		default:
			numThreadsRxNumerical = 0;
			break;
		}

		ugeth_info("Thread data RX:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_thread_data_rx);
		for (i = 0; i < numThreadsRxNumerical; i++) {
			ugeth_info("Thread data RX[%d]:", i);
			ugeth_info("Base address: 0x%08x",
				   (u32) & ugeth->p_thread_data_rx[i]);
			mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
826
				 sizeof(struct ucc_geth_thread_data_rx));
827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003
		}
	}
	if (ugeth->p_exf_glbl_param) {
		ugeth_info("EXF global param:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_exf_glbl_param);
		mem_disp((u8 *) ugeth->p_exf_glbl_param,
			 sizeof(*ugeth->p_exf_glbl_param));
	}
	if (ugeth->p_tx_glbl_pram) {
		ugeth_info("TX global param:");
		ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
		ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_tx_glbl_pram->temoder,
			   in_be16(&ugeth->p_tx_glbl_pram->temoder));
		ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->sqptr,
			   in_be32(&ugeth->p_tx_glbl_pram->sqptr));
		ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
			   in_be32(&ugeth->p_tx_glbl_pram->
				   schedulerbasepointer));
		ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
			   in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
		ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->tstate,
			   in_be32(&ugeth->p_tx_glbl_pram->tstate));
		ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
			   ugeth->p_tx_glbl_pram->iphoffset[0]);
		ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
			   ugeth->p_tx_glbl_pram->iphoffset[1]);
		ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
			   ugeth->p_tx_glbl_pram->iphoffset[2]);
		ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
			   ugeth->p_tx_glbl_pram->iphoffset[3]);
		ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
			   ugeth->p_tx_glbl_pram->iphoffset[4]);
		ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
			   ugeth->p_tx_glbl_pram->iphoffset[5]);
		ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
			   ugeth->p_tx_glbl_pram->iphoffset[6]);
		ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
			   ugeth->p_tx_glbl_pram->iphoffset[7]);
		ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
		ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
		ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
		ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
		ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
		ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
		ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
		ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
			   in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
		ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_tx_glbl_pram->tqptr,
			   in_be32(&ugeth->p_tx_glbl_pram->tqptr));
	}
	if (ugeth->p_rx_glbl_pram) {
		ugeth_info("RX global param:");
		ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
		ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->remoder,
			   in_be32(&ugeth->p_rx_glbl_pram->remoder));
		ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->rqptr,
			   in_be32(&ugeth->p_rx_glbl_pram->rqptr));
		ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->typeorlen,
			   in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
		ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
			   ugeth->p_rx_glbl_pram->rxgstpack);
		ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
			   in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
		ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
			   in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
		ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
			   (u32) & ugeth->p_rx_glbl_pram->rstate,
			   ugeth->p_rx_glbl_pram->rstate);
		ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->mrblr,
			   in_be16(&ugeth->p_rx_glbl_pram->mrblr));
		ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
			   in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
		ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->mflr,
			   in_be16(&ugeth->p_rx_glbl_pram->mflr));
		ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->minflr,
			   in_be16(&ugeth->p_rx_glbl_pram->minflr));
		ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->maxd1,
			   in_be16(&ugeth->p_rx_glbl_pram->maxd1));
		ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->maxd2,
			   in_be16(&ugeth->p_rx_glbl_pram->maxd2));
		ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->ecamptr,
			   in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
		ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l2qt,
			   in_be32(&ugeth->p_rx_glbl_pram->l2qt));
		ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
		ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
		ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
		ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
		ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
		ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
		ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
		ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
			   in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
		ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->vlantype,
			   in_be16(&ugeth->p_rx_glbl_pram->vlantype));
		ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
			   (u32) & ugeth->p_rx_glbl_pram->vlantci,
			   in_be16(&ugeth->p_rx_glbl_pram->vlantci));
		for (i = 0; i < 64; i++)
			ugeth_info
		    ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
			     i,
			     (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
			     ugeth->p_rx_glbl_pram->addressfiltering[i]);
		ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
			   (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
			   in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
	}
	if (ugeth->p_send_q_mem_reg) {
		ugeth_info("Send Q memory registers:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_send_q_mem_reg);
		for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
			ugeth_info("SQQD[%d]:", i);
			ugeth_info("Base address: 0x%08x",
				   (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
			mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
1004
				 sizeof(struct ucc_geth_send_queue_qd));
1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085
		}
	}
	if (ugeth->p_scheduler) {
		ugeth_info("Scheduler:");
		ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
		mem_disp((u8 *) ugeth->p_scheduler,
			 sizeof(*ugeth->p_scheduler));
	}
	if (ugeth->p_tx_fw_statistics_pram) {
		ugeth_info("TX FW statistics pram:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_tx_fw_statistics_pram);
		mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
			 sizeof(*ugeth->p_tx_fw_statistics_pram));
	}
	if (ugeth->p_rx_fw_statistics_pram) {
		ugeth_info("RX FW statistics pram:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_rx_fw_statistics_pram);
		mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
			 sizeof(*ugeth->p_rx_fw_statistics_pram));
	}
	if (ugeth->p_rx_irq_coalescing_tbl) {
		ugeth_info("RX IRQ coalescing tables:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_rx_irq_coalescing_tbl);
		for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
			ugeth_info("RX IRQ coalescing table entry[%d]:", i);
			ugeth_info("Base address: 0x%08x",
				   (u32) & ugeth->p_rx_irq_coalescing_tbl->
				   coalescingentry[i]);
			ugeth_info
		("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
			     (u32) & ugeth->p_rx_irq_coalescing_tbl->
			     coalescingentry[i].interruptcoalescingmaxvalue,
			     in_be32(&ugeth->p_rx_irq_coalescing_tbl->
				     coalescingentry[i].
				     interruptcoalescingmaxvalue));
			ugeth_info
		("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
			     (u32) & ugeth->p_rx_irq_coalescing_tbl->
			     coalescingentry[i].interruptcoalescingcounter,
			     in_be32(&ugeth->p_rx_irq_coalescing_tbl->
				     coalescingentry[i].
				     interruptcoalescingcounter));
		}
	}
	if (ugeth->p_rx_bd_qs_tbl) {
		ugeth_info("RX BD QS tables:");
		ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
		for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
			ugeth_info("RX BD QS table[%d]:", i);
			ugeth_info("Base address: 0x%08x",
				   (u32) & ugeth->p_rx_bd_qs_tbl[i]);
			ugeth_info
			    ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
			     (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
			     in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
			ugeth_info
			    ("bdptr            : addr - 0x%08x, val - 0x%08x",
			     (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
			     in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
			ugeth_info
			    ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
			     (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
			     in_be32(&ugeth->p_rx_bd_qs_tbl[i].
				     externalbdbaseptr));
			ugeth_info
			    ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
			     (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
			     in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
			ugeth_info("ucode RX Prefetched BDs:");
			ugeth_info("Base address: 0x%08x",
				   (u32)
				   qe_muram_addr(in_be32
						 (&ugeth->p_rx_bd_qs_tbl[i].
						  bdbaseptr)));
			mem_disp((u8 *)
				 qe_muram_addr(in_be32
					       (&ugeth->p_rx_bd_qs_tbl[i].
						bdbaseptr)),
1086
				 sizeof(struct ucc_geth_rx_prefetched_bds));
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096
		}
	}
	if (ugeth->p_init_enet_param_shadow) {
		int size;
		ugeth_info("Init enet param shadow:");
		ugeth_info("Base address: 0x%08x",
			   (u32) ugeth->p_init_enet_param_shadow);
		mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
			 sizeof(*ugeth->p_init_enet_param_shadow));

1097
		size = sizeof(struct ucc_geth_thread_rx_pram);
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
		if (ugeth->ug_info->rxExtendedFiltering) {
			size +=
			    THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
			if (ugeth->ug_info->largestexternallookupkeysize ==
			    QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
				size +=
			THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
			if (ugeth->ug_info->largestexternallookupkeysize ==
			    QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
				size +=
			THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
		}

		dump_init_enet_entries(ugeth,
				       &(ugeth->p_init_enet_param_shadow->
					 txthread[0]),
				       ENET_INIT_PARAM_MAX_ENTRIES_TX,
1115
				       sizeof(struct ucc_geth_thread_tx_pram),
1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
				       ugeth->ug_info->riscTx, 0);
		dump_init_enet_entries(ugeth,
				       &(ugeth->p_init_enet_param_shadow->
					 rxthread[0]),
				       ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
				       ugeth->ug_info->riscRx, 1);
	}
}
#endif /* DEBUG */

static void init_default_reg_vals(volatile u32 *upsmr_register,
				  volatile u32 *maccfg1_register,
				  volatile u32 *maccfg2_register)
{
	out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
	out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
	out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
}

static int init_half_duplex_params(int alt_beb,
				   int back_pressure_no_backoff,
				   int no_backoff,
				   int excess_defer,
				   u8 alt_beb_truncation,
				   u8 max_retransmissions,
				   u8 collision_window,
				   volatile u32 *hafdup_register)
{
	u32 value = 0;

	if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
	    (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
	    (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
		return -EINVAL;

	value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);

	if (alt_beb)
		value |= HALFDUP_ALT_BEB;
	if (back_pressure_no_backoff)
		value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
	if (no_backoff)
		value |= HALFDUP_NO_BACKOFF;
	if (excess_defer)
		value |= HALFDUP_EXCESSIVE_DEFER;

	value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);

	value |= collision_window;

	out_be32(hafdup_register, value);
	return 0;
}

static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
				       u8 non_btb_ipg,
				       u8 min_ifg,
				       u8 btb_ipg,
				       volatile u32 *ipgifg_register)
{
	u32 value = 0;

	/* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
	IPG part 2 */
	if (non_btb_cs_ipg > non_btb_ipg)
		return -EINVAL;

	if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
	    (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
	    /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
	    (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
		return -EINVAL;

	value |=
	    ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
	     IPGIFG_NBTB_CS_IPG_MASK);
	value |=
	    ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
	     IPGIFG_NBTB_IPG_MASK);
	value |=
	    ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
	     IPGIFG_MIN_IFG_MASK);
	value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);

	out_be32(ipgifg_register, value);
	return 0;
}

L
Li Yang 已提交
1204
int init_flow_control_params(u32 automatic_flow_control_mode,
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421
				    int rx_flow_control_enable,
				    int tx_flow_control_enable,
				    u16 pause_period,
				    u16 extension_field,
				    volatile u32 *upsmr_register,
				    volatile u32 *uempr_register,
				    volatile u32 *maccfg1_register)
{
	u32 value = 0;

	/* Set UEMPR register */
	value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
	value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
	out_be32(uempr_register, value);

	/* Set UPSMR register */
	value = in_be32(upsmr_register);
	value |= automatic_flow_control_mode;
	out_be32(upsmr_register, value);

	value = in_be32(maccfg1_register);
	if (rx_flow_control_enable)
		value |= MACCFG1_FLOW_RX;
	if (tx_flow_control_enable)
		value |= MACCFG1_FLOW_TX;
	out_be32(maccfg1_register, value);

	return 0;
}

static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
					     int auto_zero_hardware_statistics,
					     volatile u32 *upsmr_register,
					     volatile u16 *uescr_register)
{
	u32 upsmr_value = 0;
	u16 uescr_value = 0;
	/* Enable hardware statistics gathering if requested */
	if (enable_hardware_statistics) {
		upsmr_value = in_be32(upsmr_register);
		upsmr_value |= UPSMR_HSE;
		out_be32(upsmr_register, upsmr_value);
	}

	/* Clear hardware statistics counters */
	uescr_value = in_be16(uescr_register);
	uescr_value |= UESCR_CLRCNT;
	/* Automatically zero hardware statistics counters on read,
	if requested */
	if (auto_zero_hardware_statistics)
		uescr_value |= UESCR_AUTOZ;
	out_be16(uescr_register, uescr_value);

	return 0;
}

static int init_firmware_statistics_gathering_mode(int
		enable_tx_firmware_statistics,
		int enable_rx_firmware_statistics,
		volatile u32 *tx_rmon_base_ptr,
		u32 tx_firmware_statistics_structure_address,
		volatile u32 *rx_rmon_base_ptr,
		u32 rx_firmware_statistics_structure_address,
		volatile u16 *temoder_register,
		volatile u32 *remoder_register)
{
	/* Note: this function does not check if */
	/* the parameters it receives are NULL   */
	u16 temoder_value;
	u32 remoder_value;

	if (enable_tx_firmware_statistics) {
		out_be32(tx_rmon_base_ptr,
			 tx_firmware_statistics_structure_address);
		temoder_value = in_be16(temoder_register);
		temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
		out_be16(temoder_register, temoder_value);
	}

	if (enable_rx_firmware_statistics) {
		out_be32(rx_rmon_base_ptr,
			 rx_firmware_statistics_structure_address);
		remoder_value = in_be32(remoder_register);
		remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
		out_be32(remoder_register, remoder_value);
	}

	return 0;
}

static int init_mac_station_addr_regs(u8 address_byte_0,
				      u8 address_byte_1,
				      u8 address_byte_2,
				      u8 address_byte_3,
				      u8 address_byte_4,
				      u8 address_byte_5,
				      volatile u32 *macstnaddr1_register,
				      volatile u32 *macstnaddr2_register)
{
	u32 value = 0;

	/* Example: for a station address of 0x12345678ABCD, */
	/* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */

	/* MACSTNADDR1 Register: */

	/* 0                      7   8                      15  */
	/* station address byte 5     station address byte 4     */
	/* 16                     23  24                     31  */
	/* station address byte 3     station address byte 2     */
	value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
	value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
	value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
	value |= (u32) ((address_byte_5 << 24) & 0xFF000000);

	out_be32(macstnaddr1_register, value);

	/* MACSTNADDR2 Register: */

	/* 0                      7   8                      15  */
	/* station address byte 1     station address byte 0     */
	/* 16                     23  24                     31  */
	/*         reserved                   reserved           */
	value = 0;
	value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
	value |= (u32) ((address_byte_1 << 24) & 0xFF000000);

	out_be32(macstnaddr2_register, value);

	return 0;
}

static int init_check_frame_length_mode(int length_check,
					volatile u32 *maccfg2_register)
{
	u32 value = 0;

	value = in_be32(maccfg2_register);

	if (length_check)
		value |= MACCFG2_LC;
	else
		value &= ~MACCFG2_LC;

	out_be32(maccfg2_register, value);
	return 0;
}

static int init_preamble_length(u8 preamble_length,
				volatile u32 *maccfg2_register)
{
	u32 value = 0;

	if ((preamble_length < 3) || (preamble_length > 7))
		return -EINVAL;

	value = in_be32(maccfg2_register);
	value &= ~MACCFG2_PREL_MASK;
	value |= (preamble_length << MACCFG2_PREL_SHIFT);
	out_be32(maccfg2_register, value);
	return 0;
}

static int init_rx_parameters(int reject_broadcast,
			      int receive_short_frames,
			      int promiscuous, volatile u32 *upsmr_register)
{
	u32 value = 0;

	value = in_be32(upsmr_register);

	if (reject_broadcast)
		value |= UPSMR_BRO;
	else
		value &= ~UPSMR_BRO;

	if (receive_short_frames)
		value |= UPSMR_RSH;
	else
		value &= ~UPSMR_RSH;

	if (promiscuous)
		value |= UPSMR_PRO;
	else
		value &= ~UPSMR_PRO;

	out_be32(upsmr_register, value);

	return 0;
}

static int init_max_rx_buff_len(u16 max_rx_buf_len,
				volatile u16 *mrblr_register)
{
	/* max_rx_buf_len value must be a multiple of 128 */
	if ((max_rx_buf_len == 0)
	    || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
		return -EINVAL;

	out_be16(mrblr_register, max_rx_buf_len);
	return 0;
}

static int init_min_frame_len(u16 min_frame_length,
			      volatile u16 *minflr_register,
			      volatile u16 *mrblr_register)
{
	u16 mrblr_value = 0;

	mrblr_value = in_be16(mrblr_register);
	if (min_frame_length >= (mrblr_value - 4))
		return -EINVAL;

	out_be16(minflr_register, min_frame_length);
	return 0;
}

1422
static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1423
{
1424 1425 1426
	struct ucc_geth_info *ug_info;
	struct ucc_geth *ug_regs;
	struct ucc_fast *uf_regs;
1427 1428
	int ret_val;
	u32 upsmr, maccfg2, tbiBaseAddress;
1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439
	u16 value;

	ugeth_vdbg("%s: IN", __FUNCTION__);

	ug_info = ugeth->ug_info;
	ug_regs = ugeth->ug_regs;
	uf_regs = ugeth->uccf->uf_regs;

	/*                    Set MACCFG2                    */
	maccfg2 = in_be32(&ug_regs->maccfg2);
	maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1440 1441
	if ((ugeth->max_speed == SPEED_10) ||
	    (ugeth->max_speed == SPEED_100))
1442
		maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1443
	else if (ugeth->max_speed == SPEED_1000)
1444 1445 1446 1447 1448 1449 1450
		maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
	maccfg2 |= ug_info->padAndCrc;
	out_be32(&ug_regs->maccfg2, maccfg2);

	/*                    Set UPSMR                      */
	upsmr = in_be32(&uf_regs->upsmr);
	upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
1451 1452 1453 1454
	if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1455
		upsmr |= UPSMR_RPM;
1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466
		switch (ugeth->max_speed) {
		case SPEED_10:
			upsmr |= UPSMR_R10M;
			/* FALLTHROUGH */
		case SPEED_100:
			if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
				upsmr |= UPSMR_RMM;
		}
	}
	if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1467
		upsmr |= UPSMR_TBIM;
1468
	}
1469 1470 1471 1472 1473
	out_be32(&uf_regs->upsmr, upsmr);

	/* Disable autonegotiation in tbi mode, because by default it
	comes up in autonegotiation mode. */
	/* Note that this depends on proper setting in utbipar register. */
1474 1475
	if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1476 1477 1478
		tbiBaseAddress = in_be32(&ug_regs->utbipar);
		tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
		tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1479 1480
		value = ugeth->phydev->bus->read(ugeth->phydev->bus,
				(u8) tbiBaseAddress, ENET_TBI_MII_CR);
1481
		value &= ~0x1000;	/* Turn off autonegotiation */
1482 1483
		ugeth->phydev->bus->write(ugeth->phydev->bus,
				(u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504
	}

	init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);

	ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
	if (ret_val != 0) {
		ugeth_err
		    ("%s: Preamble length must be between 3 and 7 inclusive.",
		     __FUNCTION__);
		return ret_val;
	}

	return 0;
}

/* Called every time the controller might need to be made
 * aware of new link state.  The PHY code conveys this
 * information through variables in the ugeth structure, and this
 * function converts those variables into the appropriate
 * register values, and can bring down the device if needed.
 */
1505

1506 1507
static void adjust_link(struct net_device *dev)
{
1508 1509
	struct ucc_geth_private *ugeth = netdev_priv(dev);
	struct ucc_geth *ug_regs;
1510 1511 1512 1513
	struct ucc_fast *uf_regs;
	struct phy_device *phydev = ugeth->phydev;
	unsigned long flags;
	int new_state = 0;
1514 1515

	ug_regs = ugeth->ug_regs;
1516
	uf_regs = ugeth->uccf->uf_regs;
1517

1518 1519 1520 1521 1522
	spin_lock_irqsave(&ugeth->lock, flags);

	if (phydev->link) {
		u32 tempval = in_be32(&ug_regs->maccfg2);
		u32 upsmr = in_be32(&uf_regs->upsmr);
1523 1524
		/* Now we make sure that we can be in full duplex mode.
		 * If not, we operate in half-duplex mode. */
1525 1526 1527
		if (phydev->duplex != ugeth->oldduplex) {
			new_state = 1;
			if (!(phydev->duplex))
1528
				tempval &= ~(MACCFG2_FDX);
1529
			else
1530
				tempval |= MACCFG2_FDX;
1531
			ugeth->oldduplex = phydev->duplex;
1532 1533
		}

1534 1535 1536 1537 1538 1539 1540
		if (phydev->speed != ugeth->oldspeed) {
			new_state = 1;
			switch (phydev->speed) {
			case SPEED_1000:
				tempval = ((tempval &
					    ~(MACCFG2_INTERFACE_MODE_MASK)) |
					    MACCFG2_INTERFACE_MODE_BYTE);
1541
				break;
1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
			case SPEED_100:
			case SPEED_10:
				tempval = ((tempval &
					    ~(MACCFG2_INTERFACE_MODE_MASK)) |
					    MACCFG2_INTERFACE_MODE_NIBBLE);
				/* if reduced mode, re-set UPSMR.R10M */
				if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
					if (phydev->speed == SPEED_10)
						upsmr |= UPSMR_R10M;
					else
						upsmr &= ~(UPSMR_R10M);
				}
1557 1558
				break;
			default:
1559 1560 1561 1562
				if (netif_msg_link(ugeth))
					ugeth_warn(
						"%s: Ack!  Speed (%d) is not 10/100/1000!",
						dev->name, phydev->speed);
1563 1564
				break;
			}
1565
			ugeth->oldspeed = phydev->speed;
1566 1567
		}

1568 1569 1570
		out_be32(&ug_regs->maccfg2, tempval);
		out_be32(&uf_regs->upsmr, upsmr);

1571
		if (!ugeth->oldlink) {
1572
			new_state = 1;
1573 1574 1575
			ugeth->oldlink = 1;
			netif_schedule(dev);
		}
1576 1577
	} else if (ugeth->oldlink) {
			new_state = 1;
1578 1579 1580 1581
			ugeth->oldlink = 0;
			ugeth->oldspeed = 0;
			ugeth->oldduplex = -1;
	}
1582 1583 1584 1585 1586

	if (new_state && netif_msg_link(ugeth))
		phy_print_status(phydev);

	spin_unlock_irqrestore(&ugeth->lock, flags);
1587 1588 1589 1590 1591 1592 1593
}

/* Configure the PHY for dev.
 * returns 0 if success.  -1 if failure
 */
static int init_phy(struct net_device *dev)
{
1594 1595 1596
	struct ucc_geth_private *priv = netdev_priv(dev);
	struct phy_device *phydev;
	char phy_id[BUS_ID_SIZE];
1597

1598 1599 1600
	priv->oldlink = 0;
	priv->oldspeed = 0;
	priv->oldduplex = -1;
1601

1602 1603
	snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->ug_info->mdio_bus,
			priv->ug_info->phy_address);
1604

1605
	phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
1606

1607 1608 1609
	if (IS_ERR(phydev)) {
		printk("%s: Could not attach to PHY\n", dev->name);
		return PTR_ERR(phydev);
1610 1611
	}

1612
	phydev->supported &= (ADVERTISED_10baseT_Half |
1613 1614
				 ADVERTISED_10baseT_Full |
				 ADVERTISED_100baseT_Half |
1615
				 ADVERTISED_100baseT_Full);
1616

1617 1618
	if (priv->max_speed == SPEED_1000)
		phydev->supported |= ADVERTISED_1000baseT_Full;
1619

1620
	phydev->advertising = phydev->supported;
1621

1622
	priv->phydev = phydev;
1623 1624 1625 1626

	return 0;
}

1627

1628

1629
static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1630
{
1631
	struct ucc_fast_private *uccf;
1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646
	u32 cecr_subblock;
	u32 temp;

	uccf = ugeth->uccf;

	/* Mask GRACEFUL STOP TX interrupt bit and clear it */
	temp = in_be32(uccf->p_uccm);
	temp &= ~UCCE_GRA;
	out_be32(uccf->p_uccm, temp);
	out_be32(uccf->p_ucce, UCCE_GRA);	/* clear by writing 1 */

	/* Issue host command */
	cecr_subblock =
	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
	qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1647
		     QE_CR_PROTOCOL_ETHERNET, 0);
1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658

	/* Wait for command to complete */
	do {
		temp = in_be32(uccf->p_ucce);
	} while (!(temp & UCCE_GRA));

	uccf->stopped_tx = 1;

	return 0;
}

1659
static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1660
{
1661
	struct ucc_fast_private *uccf;
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679
	u32 cecr_subblock;
	u8 temp;

	uccf = ugeth->uccf;

	/* Clear acknowledge bit */
	temp = ugeth->p_rx_glbl_pram->rxgstpack;
	temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
	ugeth->p_rx_glbl_pram->rxgstpack = temp;

	/* Keep issuing command and checking acknowledge bit until
	it is asserted, according to spec */
	do {
		/* Issue host command */
		cecr_subblock =
		    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
						ucc_num);
		qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1680
			     QE_CR_PROTOCOL_ETHERNET, 0);
1681 1682 1683 1684 1685 1686 1687 1688 1689

		temp = ugeth->p_rx_glbl_pram->rxgstpack;
	} while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));

	uccf->stopped_rx = 1;

	return 0;
}

1690
static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1691
{
1692
	struct ucc_fast_private *uccf;
1693 1694 1695 1696 1697 1698
	u32 cecr_subblock;

	uccf = ugeth->uccf;

	cecr_subblock =
	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1699
	qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1700 1701 1702 1703 1704
	uccf->stopped_tx = 0;

	return 0;
}

1705
static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1706
{
1707
	struct ucc_fast_private *uccf;
1708 1709 1710 1711 1712 1713
	u32 cecr_subblock;

	uccf = ugeth->uccf;

	cecr_subblock =
	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1714
	qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1715 1716 1717 1718 1719 1720
		     0);
	uccf->stopped_rx = 0;

	return 0;
}

1721
static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1722
{
1723
	struct ucc_fast_private *uccf;
1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749
	int enabled_tx, enabled_rx;

	uccf = ugeth->uccf;

	/* check if the UCC number is in range. */
	if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
		ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
		return -EINVAL;
	}

	enabled_tx = uccf->enabled_tx;
	enabled_rx = uccf->enabled_rx;

	/* Get Tx and Rx going again, in case this channel was actively
	disabled. */
	if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
		ugeth_restart_tx(ugeth);
	if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
		ugeth_restart_rx(ugeth);

	ucc_fast_enable(uccf, mode);	/* OK to do even if not disabled */

	return 0;

}

1750
static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1751
{
1752
	struct ucc_fast_private *uccf;
1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774

	uccf = ugeth->uccf;

	/* check if the UCC number is in range. */
	if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
		ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
		return -EINVAL;
	}

	/* Stop any transmissions */
	if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
		ugeth_graceful_stop_tx(ugeth);

	/* Stop any receptions */
	if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
		ugeth_graceful_stop_rx(ugeth);

	ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */

	return 0;
}

1775
static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1776 1777 1778 1779 1780 1781 1782 1783 1784
{
#ifdef DEBUG
	ucc_fast_dump_regs(ugeth->uccf);
	dump_regs(ugeth);
	dump_bds(ugeth);
#endif
}

#ifdef CONFIG_UGETH_FILTERING
1785
static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
1786
					     p_UccGethTadParams,
1787
					     struct qe_fltr_tad *qe_fltr_tad)
1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824
{
	u16 temp;

	/* Zero serialized TAD */
	memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);

	qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V;	/* Must have this */
	if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
	    (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
	    || (p_UccGethTadParams->vnontag_op !=
		UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
	    )
		qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
	if (p_UccGethTadParams->reject_frame)
		qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
	temp =
	    (u16) (((u16) p_UccGethTadParams->
		    vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
	qe_fltr_tad->serialized[0] |= (u8) (temp >> 8);	/* upper bits */

	qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff);	/* lower bits */
	if (p_UccGethTadParams->vnontag_op ==
	    UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
		qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
	qe_fltr_tad->serialized[1] |=
	    p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;

	qe_fltr_tad->serialized[2] |=
	    p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
	/* upper bits */
	qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
	/* lower bits */
	qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);

	return 0;
}

1825 1826 1827
static struct enet_addr_container_t
    *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
						 struct enet_addr *p_enet_addr)
1828
{
1829
	struct enet_addr_container *enet_addr_cont;
1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849
	struct list_head *p_lh;
	u16 i, num;
	int32_t j;
	u8 *p_counter;

	if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
		p_lh = &ugeth->group_hash_q;
		p_counter = &(ugeth->numGroupAddrInHash);
	} else {
		p_lh = &ugeth->ind_hash_q;
		p_counter = &(ugeth->numIndAddrInHash);
	}

	if (!p_lh)
		return NULL;

	num = *p_counter;

	for (i = 0; i < num; i++) {
		enet_addr_cont =
1850
		    (struct enet_addr_container *)
1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862
		    ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
		for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
			if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
				break;
			if (j == 0)
				return enet_addr_cont;	/* Found */
		}
		enqueue(p_lh, &enet_addr_cont->node);	/* Put it back */
	}
	return NULL;
}

1863 1864
static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
						 struct enet_addr *p_enet_addr)
1865
{
1866 1867
	enum ucc_geth_enet_address_recognition_location location;
	struct enet_addr_container *enet_addr_cont;
1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901
	struct list_head *p_lh;
	u8 i;
	u32 limit;
	u8 *p_counter;

	if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
		p_lh = &ugeth->group_hash_q;
		limit = ugeth->ug_info->maxGroupAddrInHash;
		location =
		    UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
		p_counter = &(ugeth->numGroupAddrInHash);
	} else {
		p_lh = &ugeth->ind_hash_q;
		limit = ugeth->ug_info->maxIndAddrInHash;
		location =
		    UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
		p_counter = &(ugeth->numIndAddrInHash);
	}

	if ((enet_addr_cont =
	     ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
		list_add(p_lh, &enet_addr_cont->node);	/* Put it back */
		return 0;
	}
	if ((!p_lh) || (!(*p_counter < limit)))
		return -EBUSY;
	if (!(enet_addr_cont = get_enet_addr_container()))
		return -ENOMEM;
	for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
		(enet_addr_cont->address)[i] = (*p_enet_addr)[i];
	enet_addr_cont->location = location;
	enqueue(p_lh, &enet_addr_cont->node);	/* Put it back */
	++(*p_counter);

1902
	hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1903 1904 1905
	return 0;
}

1906 1907
static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
						   struct enet_addr *p_enet_addr)
1908
{
1909 1910 1911 1912
	struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
	struct enet_addr_container *enet_addr_cont;
	struct ucc_fast_private *uccf;
	enum comm_dir comm_dir;
1913 1914 1915 1916 1917 1918 1919 1920
	u16 i, num;
	struct list_head *p_lh;
	u32 *addr_h, *addr_l;
	u8 *p_counter;

	uccf = ugeth->uccf;

	p_82xx_addr_filt =
1921
	    (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960
	    addressfiltering;

	if (!
	    (enet_addr_cont =
	     ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
		return -ENOENT;

	/* It's been found and removed from the CQ. */
	/* Now destroy its container */
	put_enet_addr_container(enet_addr_cont);

	if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
		addr_h = &(p_82xx_addr_filt->gaddr_h);
		addr_l = &(p_82xx_addr_filt->gaddr_l);
		p_lh = &ugeth->group_hash_q;
		p_counter = &(ugeth->numGroupAddrInHash);
	} else {
		addr_h = &(p_82xx_addr_filt->iaddr_h);
		addr_l = &(p_82xx_addr_filt->iaddr_l);
		p_lh = &ugeth->ind_hash_q;
		p_counter = &(ugeth->numIndAddrInHash);
	}

	comm_dir = 0;
	if (uccf->enabled_tx)
		comm_dir |= COMM_DIR_TX;
	if (uccf->enabled_rx)
		comm_dir |= COMM_DIR_RX;
	if (comm_dir)
		ugeth_disable(ugeth, comm_dir);

	/* Clear the hash table. */
	out_be32(addr_h, 0x00000000);
	out_be32(addr_l, 0x00000000);

	/* Add all remaining CQ elements back into hash */
	num = --(*p_counter);
	for (i = 0; i < num; i++) {
		enet_addr_cont =
1961
		    (struct enet_addr_container *)
1962
		    ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1963
		hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1964 1965 1966 1967 1968 1969 1970 1971 1972 1973
		enqueue(p_lh, &enet_addr_cont->node);	/* Put it back */
	}

	if (comm_dir)
		ugeth_enable(ugeth, comm_dir);

	return 0;
}
#endif /* CONFIG_UGETH_FILTERING */

1974
static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1975
						       ugeth,
1976
						       enum enet_addr_type
1977 1978
						       enet_addr_type)
{
1979 1980 1981
	struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
	struct ucc_fast_private *uccf;
	enum comm_dir comm_dir;
1982 1983 1984 1985 1986 1987 1988 1989
	struct list_head *p_lh;
	u16 i, num;
	u32 *addr_h, *addr_l;
	u8 *p_counter;

	uccf = ugeth->uccf;

	p_82xx_addr_filt =
1990
	    (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035
	    addressfiltering;

	if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
		addr_h = &(p_82xx_addr_filt->gaddr_h);
		addr_l = &(p_82xx_addr_filt->gaddr_l);
		p_lh = &ugeth->group_hash_q;
		p_counter = &(ugeth->numGroupAddrInHash);
	} else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
		addr_h = &(p_82xx_addr_filt->iaddr_h);
		addr_l = &(p_82xx_addr_filt->iaddr_l);
		p_lh = &ugeth->ind_hash_q;
		p_counter = &(ugeth->numIndAddrInHash);
	} else
		return -EINVAL;

	comm_dir = 0;
	if (uccf->enabled_tx)
		comm_dir |= COMM_DIR_TX;
	if (uccf->enabled_rx)
		comm_dir |= COMM_DIR_RX;
	if (comm_dir)
		ugeth_disable(ugeth, comm_dir);

	/* Clear the hash table. */
	out_be32(addr_h, 0x00000000);
	out_be32(addr_l, 0x00000000);

	if (!p_lh)
		return 0;

	num = *p_counter;

	/* Delete all remaining CQ elements */
	for (i = 0; i < num; i++)
		put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));

	*p_counter = 0;

	if (comm_dir)
		ugeth_enable(ugeth, comm_dir);

	return 0;
}

#ifdef CONFIG_UGETH_FILTERING
2036 2037
static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
						  struct enet_addr *p_enet_addr,
2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
						  u8 paddr_num)
{
	int i;

	if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
		ugeth_warn
		    ("%s: multicast address added to paddr will have no "
		     "effect - is this what you wanted?",
		     __FUNCTION__);

	ugeth->indAddrRegUsed[paddr_num] = 1;	/* mark this paddr as used */
	/* store address in our database */
	for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
		ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
	/* put in hardware */
	return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
}
#endif /* CONFIG_UGETH_FILTERING */

2057
static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
2058 2059 2060 2061 2062 2063
						    u8 paddr_num)
{
	ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
	return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
}

2064
static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134
{
	u16 i, j;
	u8 *bd;

	if (!ugeth)
		return;

	if (ugeth->uccf)
		ucc_fast_free(ugeth->uccf);

	if (ugeth->p_thread_data_tx) {
		qe_muram_free(ugeth->thread_dat_tx_offset);
		ugeth->p_thread_data_tx = NULL;
	}
	if (ugeth->p_thread_data_rx) {
		qe_muram_free(ugeth->thread_dat_rx_offset);
		ugeth->p_thread_data_rx = NULL;
	}
	if (ugeth->p_exf_glbl_param) {
		qe_muram_free(ugeth->exf_glbl_param_offset);
		ugeth->p_exf_glbl_param = NULL;
	}
	if (ugeth->p_rx_glbl_pram) {
		qe_muram_free(ugeth->rx_glbl_pram_offset);
		ugeth->p_rx_glbl_pram = NULL;
	}
	if (ugeth->p_tx_glbl_pram) {
		qe_muram_free(ugeth->tx_glbl_pram_offset);
		ugeth->p_tx_glbl_pram = NULL;
	}
	if (ugeth->p_send_q_mem_reg) {
		qe_muram_free(ugeth->send_q_mem_reg_offset);
		ugeth->p_send_q_mem_reg = NULL;
	}
	if (ugeth->p_scheduler) {
		qe_muram_free(ugeth->scheduler_offset);
		ugeth->p_scheduler = NULL;
	}
	if (ugeth->p_tx_fw_statistics_pram) {
		qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
		ugeth->p_tx_fw_statistics_pram = NULL;
	}
	if (ugeth->p_rx_fw_statistics_pram) {
		qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
		ugeth->p_rx_fw_statistics_pram = NULL;
	}
	if (ugeth->p_rx_irq_coalescing_tbl) {
		qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
		ugeth->p_rx_irq_coalescing_tbl = NULL;
	}
	if (ugeth->p_rx_bd_qs_tbl) {
		qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
		ugeth->p_rx_bd_qs_tbl = NULL;
	}
	if (ugeth->p_init_enet_param_shadow) {
		return_init_enet_entries(ugeth,
					 &(ugeth->p_init_enet_param_shadow->
					   rxthread[0]),
					 ENET_INIT_PARAM_MAX_ENTRIES_RX,
					 ugeth->ug_info->riscRx, 1);
		return_init_enet_entries(ugeth,
					 &(ugeth->p_init_enet_param_shadow->
					   txthread[0]),
					 ENET_INIT_PARAM_MAX_ENTRIES_TX,
					 ugeth->ug_info->riscTx, 0);
		kfree(ugeth->p_init_enet_param_shadow);
		ugeth->p_init_enet_param_shadow = NULL;
	}
	for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
		bd = ugeth->p_tx_bd_ring[i];
2135 2136
		if (!bd)
			continue;
2137 2138 2139
		for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
			if (ugeth->tx_skbuff[i][j]) {
				dma_unmap_single(NULL,
2140 2141
						 ((qe_bd_t *)bd)->buf,
						 (in_be32((u32 *)bd) &
2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166
						  BD_LENGTH_MASK),
						 DMA_TO_DEVICE);
				dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
				ugeth->tx_skbuff[i][j] = NULL;
			}
		}

		kfree(ugeth->tx_skbuff[i]);

		if (ugeth->p_tx_bd_ring[i]) {
			if (ugeth->ug_info->uf_info.bd_mem_part ==
			    MEM_PART_SYSTEM)
				kfree((void *)ugeth->tx_bd_ring_offset[i]);
			else if (ugeth->ug_info->uf_info.bd_mem_part ==
				 MEM_PART_MURAM)
				qe_muram_free(ugeth->tx_bd_ring_offset[i]);
			ugeth->p_tx_bd_ring[i] = NULL;
		}
	}
	for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
		if (ugeth->p_rx_bd_ring[i]) {
			/* Return existing data buffers in ring */
			bd = ugeth->p_rx_bd_ring[i];
			for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
				if (ugeth->rx_skbuff[i][j]) {
2167 2168 2169 2170 2171 2172 2173 2174
					dma_unmap_single(NULL,
						((struct qe_bd *)bd)->buf,
						ugeth->ug_info->
						uf_info.max_rx_buf_length +
						UCC_GETH_RX_DATA_BUF_ALIGNMENT,
						DMA_FROM_DEVICE);
					dev_kfree_skb_any(
						ugeth->rx_skbuff[i][j]);
2175 2176
					ugeth->rx_skbuff[i][j] = NULL;
				}
2177
				bd += sizeof(struct qe_bd);
2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201
			}

			kfree(ugeth->rx_skbuff[i]);

			if (ugeth->ug_info->uf_info.bd_mem_part ==
			    MEM_PART_SYSTEM)
				kfree((void *)ugeth->rx_bd_ring_offset[i]);
			else if (ugeth->ug_info->uf_info.bd_mem_part ==
				 MEM_PART_MURAM)
				qe_muram_free(ugeth->rx_bd_ring_offset[i]);
			ugeth->p_rx_bd_ring[i] = NULL;
		}
	}
	while (!list_empty(&ugeth->group_hash_q))
		put_enet_addr_container(ENET_ADDR_CONT_ENTRY
					(dequeue(&ugeth->group_hash_q)));
	while (!list_empty(&ugeth->ind_hash_q))
		put_enet_addr_container(ENET_ADDR_CONT_ENTRY
					(dequeue(&ugeth->ind_hash_q)));

}

static void ucc_geth_set_multi(struct net_device *dev)
{
2202
	struct ucc_geth_private *ugeth;
2203
	struct dev_mc_list *dmi;
2204 2205 2206
	struct ucc_fast *uf_regs;
	struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
	u8 tempaddr[6];
2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222
	u8 *mcptr, *tdptr;
	int i, j;

	ugeth = netdev_priv(dev);

	uf_regs = ugeth->uccf->uf_regs;

	if (dev->flags & IFF_PROMISC) {

		uf_regs->upsmr |= UPSMR_PRO;

	} else {

		uf_regs->upsmr &= ~UPSMR_PRO;

		p_82xx_addr_filt =
2223
		    (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251
		    p_rx_glbl_pram->addressfiltering;

		if (dev->flags & IFF_ALLMULTI) {
			/* Catch all multicast addresses, so set the
			 * filter to all 1's.
			 */
			out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
			out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
		} else {
			/* Clear filter and add the addresses in the list.
			 */
			out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
			out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);

			dmi = dev->mc_list;

			for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {

				/* Only support group multicast for now.
				 */
				if (!(dmi->dmi_addr[0] & 1))
					continue;

				/* The address in dmi_addr is LSB first,
				 * and taddr is MSB first.  We have to
				 * copy bytes MSB first from dmi_addr.
				 */
				mcptr = (u8 *) dmi->dmi_addr + 5;
2252
				tdptr = (u8 *) tempaddr;
2253 2254 2255 2256 2257 2258
				for (j = 0; j < 6; j++)
					*tdptr++ = *mcptr--;

				/* Ask CPM to run CRC and set bit in
				 * filter mask.
				 */
2259
				hw_add_addr_in_hash(ugeth, tempaddr);
2260 2261 2262 2263 2264
			}
		}
	}
}

2265
static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2266
{
2267
	struct ucc_geth *ug_regs = ugeth->ug_regs;
2268
	struct phy_device *phydev = ugeth->phydev;
2269 2270 2271 2272 2273 2274 2275 2276
	u32 tempval;

	ugeth_vdbg("%s: IN", __FUNCTION__);

	/* Disable the controller */
	ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);

	/* Tell the kernel the link is down */
2277
	phy_stop(phydev);
2278 2279

	/* Mask all interrupts */
2280
	out_be32(ugeth->uccf->p_uccm, 0x00000000);
2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294

	/* Clear all interrupts */
	out_be32(ugeth->uccf->p_ucce, 0xffffffff);

	/* Disable Rx and Tx */
	tempval = in_be32(&ug_regs->maccfg1);
	tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
	out_be32(&ug_regs->maccfg1, tempval);

	free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);

	ucc_geth_memclean(ugeth);
}

2295
static int ucc_struct_init(struct ucc_geth_private *ugeth)
2296
{
2297 2298
	struct ucc_geth_info *ug_info;
	struct ucc_fast_info *uf_info;
2299
	int i;
2300 2301 2302 2303

	ug_info = ugeth->ug_info;
	uf_info = &ug_info->uf_info;

2304 2305 2306 2307
	/* Create CQs for hash tables */
	INIT_LIST_HEAD(&ugeth->group_hash_q);
	INIT_LIST_HEAD(&ugeth->ind_hash_q);

2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
	if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
	      (uf_info->bd_mem_part == MEM_PART_MURAM))) {
		ugeth_err("%s: Bad memory partition value.", __FUNCTION__);
		return -EINVAL;
	}

	/* Rx BD lengths */
	for (i = 0; i < ug_info->numQueuesRx; i++) {
		if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
		    (ug_info->bdRingLenRx[i] %
		     UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
			ugeth_err
			    ("%s: Rx BD ring length must be multiple of 4,"
				" no smaller than 8.", __FUNCTION__);
			return -EINVAL;
		}
	}

	/* Tx BD lengths */
	for (i = 0; i < ug_info->numQueuesTx; i++) {
		if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
			ugeth_err
			    ("%s: Tx BD ring length must be no smaller than 2.",
			     __FUNCTION__);
			return -EINVAL;
		}
	}

	/* mrblr */
	if ((uf_info->max_rx_buf_length == 0) ||
	    (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
		ugeth_err
		    ("%s: max_rx_buf_length must be non-zero multiple of 128.",
		     __FUNCTION__);
		return -EINVAL;
	}

	/* num Tx queues */
	if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
		ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
		return -EINVAL;
	}

	/* num Rx queues */
	if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
		ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
		return -EINVAL;
	}

	/* l2qt */
	for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
		if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
			ugeth_err
			    ("%s: VLAN priority table entry must not be"
				" larger than number of Rx queues.",
			     __FUNCTION__);
			return -EINVAL;
		}
	}

	/* l3qt */
	for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
		if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
			ugeth_err
			    ("%s: IP priority table entry must not be"
				" larger than number of Rx queues.",
			     __FUNCTION__);
			return -EINVAL;
		}
	}

	if (ug_info->cam && !ug_info->ecamptr) {
		ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
			  __FUNCTION__);
		return -EINVAL;
	}

	if ((ug_info->numStationAddresses !=
	     UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
	    && ug_info->rxExtendedFiltering) {
		ugeth_err("%s: Number of station addresses greater than 1 "
			  "not allowed in extended parsing mode.",
			  __FUNCTION__);
		return -EINVAL;
	}

	/* Generate uccm_mask for receive */
	uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
	for (i = 0; i < ug_info->numQueuesRx; i++)
		uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);

	for (i = 0; i < ug_info->numQueuesTx; i++)
		uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
	/* Initialize the general fast UCC block. */
2402
	if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2403 2404 2405 2406
		ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}
2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437

	ugeth->ug_regs = (struct ucc_geth *) ioremap(uf_info->regs, sizeof(struct ucc_geth));

	return 0;
}

static int ucc_geth_startup(struct ucc_geth_private *ugeth)
{
	struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
	struct ucc_geth_init_pram *p_init_enet_pram;
	struct ucc_fast_private *uccf;
	struct ucc_geth_info *ug_info;
	struct ucc_fast_info *uf_info;
	struct ucc_fast *uf_regs;
	struct ucc_geth *ug_regs;
	int ret_val = -EINVAL;
	u32 remoder = UCC_GETH_REMODER_INIT;
	u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
	u32 ifstat, i, j, size, l2qt, l3qt, length;
	u16 temoder = UCC_GETH_TEMODER_INIT;
	u16 test;
	u8 function_code = 0;
	u8 *bd, *endOfRing;
	u8 numThreadsRxNumerical, numThreadsTxNumerical;

	ugeth_vdbg("%s: IN", __FUNCTION__);
	uccf = ugeth->uccf;
	ug_info = ugeth->ug_info;
	uf_info = &ug_info->uf_info;
	uf_regs = uccf->uf_regs;
	ug_regs = ugeth->ug_regs;
2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510

	switch (ug_info->numThreadsRx) {
	case UCC_GETH_NUM_OF_THREADS_1:
		numThreadsRxNumerical = 1;
		break;
	case UCC_GETH_NUM_OF_THREADS_2:
		numThreadsRxNumerical = 2;
		break;
	case UCC_GETH_NUM_OF_THREADS_4:
		numThreadsRxNumerical = 4;
		break;
	case UCC_GETH_NUM_OF_THREADS_6:
		numThreadsRxNumerical = 6;
		break;
	case UCC_GETH_NUM_OF_THREADS_8:
		numThreadsRxNumerical = 8;
		break;
	default:
		ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -EINVAL;
		break;
	}

	switch (ug_info->numThreadsTx) {
	case UCC_GETH_NUM_OF_THREADS_1:
		numThreadsTxNumerical = 1;
		break;
	case UCC_GETH_NUM_OF_THREADS_2:
		numThreadsTxNumerical = 2;
		break;
	case UCC_GETH_NUM_OF_THREADS_4:
		numThreadsTxNumerical = 4;
		break;
	case UCC_GETH_NUM_OF_THREADS_6:
		numThreadsTxNumerical = 6;
		break;
	case UCC_GETH_NUM_OF_THREADS_8:
		numThreadsTxNumerical = 8;
		break;
	default:
		ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -EINVAL;
		break;
	}

	/* Calculate rx_extended_features */
	ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
	    ug_info->ipAddressAlignment ||
	    (ug_info->numStationAddresses !=
	     UCC_GETH_NUM_OF_STATION_ADDRESSES_1);

	ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
	    (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
	    || (ug_info->vlanOperationNonTagged !=
		UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);

	init_default_reg_vals(&uf_regs->upsmr,
			      &ug_regs->maccfg1, &ug_regs->maccfg2);

	/*                    Set UPSMR                      */
	/* For more details see the hardware spec.           */
	init_rx_parameters(ug_info->bro,
			   ug_info->rsh, ug_info->pro, &uf_regs->upsmr);

	/* We're going to ignore other registers for now, */
	/* except as needed to get up and running         */

	/*                    Set MACCFG1                    */
	/* For more details see the hardware spec.           */
	init_flow_control_params(ug_info->aufc,
				 ug_info->receiveFlowControl,
L
Li Yang 已提交
2511
				 ug_info->transmitFlowControl,
2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573
				 ug_info->pausePeriod,
				 ug_info->extensionField,
				 &uf_regs->upsmr,
				 &ug_regs->uempr, &ug_regs->maccfg1);

	maccfg1 = in_be32(&ug_regs->maccfg1);
	maccfg1 |= MACCFG1_ENABLE_RX;
	maccfg1 |= MACCFG1_ENABLE_TX;
	out_be32(&ug_regs->maccfg1, maccfg1);

	/*                    Set IPGIFG                     */
	/* For more details see the hardware spec.           */
	ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
					      ug_info->nonBackToBackIfgPart2,
					      ug_info->
					      miminumInterFrameGapEnforcement,
					      ug_info->backToBackInterFrameGap,
					      &ug_regs->ipgifg);
	if (ret_val != 0) {
		ugeth_err("%s: IPGIFG initialization parameter too large.",
			  __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return ret_val;
	}

	/*                    Set HAFDUP                     */
	/* For more details see the hardware spec.           */
	ret_val = init_half_duplex_params(ug_info->altBeb,
					  ug_info->backPressureNoBackoff,
					  ug_info->noBackoff,
					  ug_info->excessDefer,
					  ug_info->altBebTruncation,
					  ug_info->maxRetransmission,
					  ug_info->collisionWindow,
					  &ug_regs->hafdup);
	if (ret_val != 0) {
		ugeth_err("%s: Half Duplex initialization parameter too large.",
			  __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return ret_val;
	}

	/*                    Set IFSTAT                     */
	/* For more details see the hardware spec.           */
	/* Read only - resets upon read                      */
	ifstat = in_be32(&ug_regs->ifstat);

	/*                    Clear UEMPR                    */
	/* For more details see the hardware spec.           */
	out_be32(&ug_regs->uempr, 0);

	/*                    Set UESCR                      */
	/* For more details see the hardware spec.           */
	init_hw_statistics_gathering_mode((ug_info->statisticsMode &
				UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
				0, &uf_regs->upsmr, &ug_regs->uescr);

	/* Allocate Tx bds */
	for (j = 0; j < ug_info->numQueuesTx; j++) {
		/* Allocate in multiple of
		   UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
		   according to spec */
2574
		length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2575 2576
			  / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
		    * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2577
		if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2578 2579 2580 2581 2582 2583 2584
		    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
			length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
		if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
			u32 align = 4;
			if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
				align = UCC_GETH_TX_BD_RING_ALIGNMENT;
			ugeth->tx_bd_ring_offset[j] =
2585 2586
				kmalloc((u32) (length + align), GFP_KERNEL);

2587 2588 2589 2590 2591 2592 2593 2594
			if (ugeth->tx_bd_ring_offset[j] != 0)
				ugeth->p_tx_bd_ring[j] =
					(void*)((ugeth->tx_bd_ring_offset[j] +
					align) & ~(align - 1));
		} else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
			ugeth->tx_bd_ring_offset[j] =
			    qe_muram_alloc(length,
					   UCC_GETH_TX_BD_RING_ALIGNMENT);
2595
			if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608
				ugeth->p_tx_bd_ring[j] =
				    (u8 *) qe_muram_addr(ugeth->
							 tx_bd_ring_offset[j]);
		}
		if (!ugeth->p_tx_bd_ring[j]) {
			ugeth_err
			    ("%s: Can not allocate memory for Tx bd rings.",
			     __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}
		/* Zero unused end of bd ring, according to spec */
		memset(ugeth->p_tx_bd_ring[j] +
2609 2610
		       ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
		       length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2611 2612 2613 2614
	}

	/* Allocate Rx bds */
	for (j = 0; j < ug_info->numQueuesRx; j++) {
2615
		length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2616 2617 2618 2619 2620
		if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
			u32 align = 4;
			if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
				align = UCC_GETH_RX_BD_RING_ALIGNMENT;
			ugeth->rx_bd_ring_offset[j] =
2621
				kmalloc((u32) (length + align), GFP_KERNEL);
2622 2623 2624 2625 2626 2627 2628 2629
			if (ugeth->rx_bd_ring_offset[j] != 0)
				ugeth->p_rx_bd_ring[j] =
					(void*)((ugeth->rx_bd_ring_offset[j] +
					align) & ~(align - 1));
		} else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
			ugeth->rx_bd_ring_offset[j] =
			    qe_muram_alloc(length,
					   UCC_GETH_RX_BD_RING_ALIGNMENT);
2630
			if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646
				ugeth->p_rx_bd_ring[j] =
				    (u8 *) qe_muram_addr(ugeth->
							 rx_bd_ring_offset[j]);
		}
		if (!ugeth->p_rx_bd_ring[j]) {
			ugeth_err
			    ("%s: Can not allocate memory for Rx bd rings.",
			     __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}
	}

	/* Init Tx bds */
	for (j = 0; j < ug_info->numQueuesTx; j++) {
		/* Setup the skbuff rings */
2647 2648 2649
		ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
					      ugeth->ug_info->bdRingLenTx[j],
					      GFP_KERNEL);
2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663

		if (ugeth->tx_skbuff[j] == NULL) {
			ugeth_err("%s: Could not allocate tx_skbuff",
				  __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}

		for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
			ugeth->tx_skbuff[j][i] = NULL;

		ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
		bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
		for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2664 2665 2666 2667 2668
			/* clear bd buffer */
			out_be32(&((struct qe_bd *)bd)->buf, 0);
			/* set bd status and length */
			out_be32((u32 *)bd, 0);
			bd += sizeof(struct qe_bd);
2669
		}
2670 2671 2672
		bd -= sizeof(struct qe_bd);
		/* set bd status and length */
		out_be32((u32 *)bd, T_W);	/* for last BD set Wrap bit */
2673 2674 2675 2676 2677
	}

	/* Init Rx bds */
	for (j = 0; j < ug_info->numQueuesRx; j++) {
		/* Setup the skbuff rings */
2678 2679 2680
		ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
					      ugeth->ug_info->bdRingLenRx[j],
					      GFP_KERNEL);
2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694

		if (ugeth->rx_skbuff[j] == NULL) {
			ugeth_err("%s: Could not allocate rx_skbuff",
				  __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}

		for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
			ugeth->rx_skbuff[j][i] = NULL;

		ugeth->skb_currx[j] = 0;
		bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
		for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2695 2696 2697 2698 2699
			/* set bd status and length */
			out_be32((u32 *)bd, R_I);
			/* clear bd buffer */
			out_be32(&((struct qe_bd *)bd)->buf, 0);
			bd += sizeof(struct qe_bd);
2700
		}
2701 2702 2703
		bd -= sizeof(struct qe_bd);
		/* set bd status and length */
		out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
2704 2705 2706 2707 2708 2709 2710 2711
	}

	/*
	 * Global PRAM
	 */
	/* Tx global PRAM */
	/* Allocate global tx parameter RAM page */
	ugeth->tx_glbl_pram_offset =
2712
	    qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2713
			   UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2714
	if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2715 2716 2717 2718 2719 2720 2721
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
		     __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}
	ugeth->p_tx_glbl_pram =
2722
	    (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
2723 2724
							tx_glbl_pram_offset);
	/* Zero out p_tx_glbl_pram */
2725
	memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2726 2727 2728 2729 2730 2731 2732

	/* Fill global PRAM */

	/* TQPTR */
	/* Size varies with number of Tx threads */
	ugeth->thread_dat_tx_offset =
	    qe_muram_alloc(numThreadsTxNumerical *
2733
			   sizeof(struct ucc_geth_thread_data_tx) +
2734 2735
			   32 * (numThreadsTxNumerical == 1),
			   UCC_GETH_THREAD_DATA_ALIGNMENT);
2736
	if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2737 2738 2739 2740 2741 2742 2743 2744
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
		     __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}

	ugeth->p_thread_data_tx =
2745
	    (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761
							thread_dat_tx_offset);
	out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);

	/* vtagtable */
	for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
		out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
			 ug_info->vtagtable[i]);

	/* iphoffset */
	for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
		ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];

	/* SQPTR */
	/* Size varies with number of Tx queues */
	ugeth->send_q_mem_reg_offset =
	    qe_muram_alloc(ug_info->numQueuesTx *
2762
			   sizeof(struct ucc_geth_send_queue_qd),
2763
			   UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2764
	if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2765 2766 2767 2768 2769 2770 2771 2772
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
		     __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}

	ugeth->p_send_q_mem_reg =
2773
	    (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
2774 2775 2776 2777 2778 2779 2780 2781
			send_q_mem_reg_offset);
	out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);

	/* Setup the table */
	/* Assume BD rings are already established */
	for (i = 0; i < ug_info->numQueuesTx; i++) {
		endOfRing =
		    ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2782
					      1) * sizeof(struct qe_bd);
2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804
		if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
				 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
				 last_bd_completed_address,
				 (u32) virt_to_phys(endOfRing));
		} else if (ugeth->ug_info->uf_info.bd_mem_part ==
			   MEM_PART_MURAM) {
			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
				 (u32) immrbar_virt_to_phys(ugeth->
							    p_tx_bd_ring[i]));
			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
				 last_bd_completed_address,
				 (u32) immrbar_virt_to_phys(endOfRing));
		}
	}

	/* schedulerbasepointer */

	if (ug_info->numQueuesTx > 1) {
	/* scheduler exists only if more than 1 tx queue */
		ugeth->scheduler_offset =
2805
		    qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2806
				   UCC_GETH_SCHEDULER_ALIGNMENT);
2807
		if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2808 2809 2810 2811 2812 2813 2814 2815
			ugeth_err
			 ("%s: Can not allocate DPRAM memory for p_scheduler.",
			     __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}

		ugeth->p_scheduler =
2816
		    (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
2817 2818 2819 2820
							   scheduler_offset);
		out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
			 ugeth->scheduler_offset);
		/* Zero out p_scheduler */
2821
		memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852

		/* Set values in scheduler */
		out_be32(&ugeth->p_scheduler->mblinterval,
			 ug_info->mblinterval);
		out_be16(&ugeth->p_scheduler->nortsrbytetime,
			 ug_info->nortsrbytetime);
		ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
		ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
		ugeth->p_scheduler->txasap = ug_info->txasap;
		ugeth->p_scheduler->extrabw = ug_info->extrabw;
		for (i = 0; i < NUM_TX_QUEUES; i++)
			ugeth->p_scheduler->weightfactor[i] =
			    ug_info->weightfactor[i];

		/* Set pointers to cpucount registers in scheduler */
		ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
		ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
		ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
		ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
		ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
		ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
		ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
		ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
	}

	/* schedulerbasepointer */
	/* TxRMON_PTR (statistics) */
	if (ug_info->
	    statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
		ugeth->tx_fw_statistics_pram_offset =
		    qe_muram_alloc(sizeof
2853
				   (struct ucc_geth_tx_firmware_statistics_pram),
2854
				   UCC_GETH_TX_STATISTICS_ALIGNMENT);
2855
		if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2856 2857 2858 2859 2860 2861 2862
			ugeth_err
			    ("%s: Can not allocate DPRAM memory for"
				" p_tx_fw_statistics_pram.", __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}
		ugeth->p_tx_fw_statistics_pram =
2863
		    (struct ucc_geth_tx_firmware_statistics_pram *)
2864 2865 2866
		    qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
		/* Zero out p_tx_fw_statistics_pram */
		memset(ugeth->p_tx_fw_statistics_pram,
2867
		       0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891
	}

	/* temoder */
	/* Already has speed set */

	if (ug_info->numQueuesTx > 1)
		temoder |= TEMODER_SCHEDULER_ENABLE;
	if (ug_info->ipCheckSumGenerate)
		temoder |= TEMODER_IP_CHECKSUM_GENERATE;
	temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
	out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);

	test = in_be16(&ugeth->p_tx_glbl_pram->temoder);

	/* Function code register value to be used later */
	function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL;
	/* Required for QE */

	/* function code register */
	out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);

	/* Rx global PRAM */
	/* Allocate global rx parameter RAM page */
	ugeth->rx_glbl_pram_offset =
2892
	    qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2893
			   UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2894
	if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2895 2896 2897 2898 2899 2900 2901
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
		     __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}
	ugeth->p_rx_glbl_pram =
2902
	    (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
2903 2904
							rx_glbl_pram_offset);
	/* Zero out p_rx_glbl_pram */
2905
	memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2906 2907 2908 2909 2910 2911 2912

	/* Fill global PRAM */

	/* RQPTR */
	/* Size varies with number of Rx threads */
	ugeth->thread_dat_rx_offset =
	    qe_muram_alloc(numThreadsRxNumerical *
2913
			   sizeof(struct ucc_geth_thread_data_rx),
2914
			   UCC_GETH_THREAD_DATA_ALIGNMENT);
2915
	if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2916 2917 2918 2919 2920 2921 2922 2923
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
		     __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}

	ugeth->p_thread_data_rx =
2924
	    (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935
							thread_dat_rx_offset);
	out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);

	/* typeorlen */
	out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);

	/* rxrmonbaseptr (statistics) */
	if (ug_info->
	    statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
		ugeth->rx_fw_statistics_pram_offset =
		    qe_muram_alloc(sizeof
2936
				   (struct ucc_geth_rx_firmware_statistics_pram),
2937
				   UCC_GETH_RX_STATISTICS_ALIGNMENT);
2938
		if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2939 2940 2941 2942 2943 2944 2945
			ugeth_err
				("%s: Can not allocate DPRAM memory for"
				" p_rx_fw_statistics_pram.", __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}
		ugeth->p_rx_fw_statistics_pram =
2946
		    (struct ucc_geth_rx_firmware_statistics_pram *)
2947 2948 2949
		    qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
		/* Zero out p_rx_fw_statistics_pram */
		memset(ugeth->p_rx_fw_statistics_pram, 0,
2950
		       sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2951 2952 2953 2954 2955 2956 2957
	}

	/* intCoalescingPtr */

	/* Size varies with number of Rx queues */
	ugeth->rx_irq_coalescing_tbl_offset =
	    qe_muram_alloc(ug_info->numQueuesRx *
2958 2959
			   sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
			   + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2960
	if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2961 2962 2963 2964 2965 2966 2967 2968
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for"
			" p_rx_irq_coalescing_tbl.", __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}

	ugeth->p_rx_irq_coalescing_tbl =
2969
	    (struct ucc_geth_rx_interrupt_coalescing_table *)
2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008
	    qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
	out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
		 ugeth->rx_irq_coalescing_tbl_offset);

	/* Fill interrupt coalescing table */
	for (i = 0; i < ug_info->numQueuesRx; i++) {
		out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
			 interruptcoalescingmaxvalue,
			 ug_info->interruptcoalescingmaxvalue[i]);
		out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
			 interruptcoalescingcounter,
			 ug_info->interruptcoalescingmaxvalue[i]);
	}

	/* MRBLR */
	init_max_rx_buff_len(uf_info->max_rx_buf_length,
			     &ugeth->p_rx_glbl_pram->mrblr);
	/* MFLR */
	out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
	/* MINFLR */
	init_min_frame_len(ug_info->minFrameLength,
			   &ugeth->p_rx_glbl_pram->minflr,
			   &ugeth->p_rx_glbl_pram->mrblr);
	/* MAXD1 */
	out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
	/* MAXD2 */
	out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);

	/* l2qt */
	l2qt = 0;
	for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
		l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
	out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);

	/* l3qt */
	for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
		l3qt = 0;
		for (i = 0; i < 8; i++)
			l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
3009
		out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024
	}

	/* vlantype */
	out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);

	/* vlantci */
	out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);

	/* ecamptr */
	out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);

	/* RBDQPTR */
	/* Size varies with number of Rx queues */
	ugeth->rx_bd_qs_tbl_offset =
	    qe_muram_alloc(ug_info->numQueuesRx *
3025 3026
			   (sizeof(struct ucc_geth_rx_bd_queues_entry) +
			    sizeof(struct ucc_geth_rx_prefetched_bds)),
3027
			   UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
3028
	if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
3029 3030 3031 3032 3033 3034 3035 3036
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
		     __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}

	ugeth->p_rx_bd_qs_tbl =
3037
	    (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
3038 3039 3040 3041 3042
				    rx_bd_qs_tbl_offset);
	out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
	/* Zero out p_rx_bd_qs_tbl */
	memset(ugeth->p_rx_bd_qs_tbl,
	       0,
3043 3044
	       ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
				       sizeof(struct ucc_geth_rx_prefetched_bds)));
3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114

	/* Setup the table */
	/* Assume BD rings are already established */
	for (i = 0; i < ug_info->numQueuesRx; i++) {
		if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
			out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
				 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
		} else if (ugeth->ug_info->uf_info.bd_mem_part ==
			   MEM_PART_MURAM) {
			out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
				 (u32) immrbar_virt_to_phys(ugeth->
							    p_rx_bd_ring[i]));
		}
		/* rest of fields handled by QE */
	}

	/* remoder */
	/* Already has speed set */

	if (ugeth->rx_extended_features)
		remoder |= REMODER_RX_EXTENDED_FEATURES;
	if (ug_info->rxExtendedFiltering)
		remoder |= REMODER_RX_EXTENDED_FILTERING;
	if (ug_info->dynamicMaxFrameLength)
		remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
	if (ug_info->dynamicMinFrameLength)
		remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
	remoder |=
	    ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
	remoder |=
	    ug_info->
	    vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
	remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
	remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
	if (ug_info->ipCheckSumCheck)
		remoder |= REMODER_IP_CHECKSUM_CHECK;
	if (ug_info->ipAddressAlignment)
		remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
	out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);

	/* Note that this function must be called */
	/* ONLY AFTER p_tx_fw_statistics_pram */
	/* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
	init_firmware_statistics_gathering_mode((ug_info->
		statisticsMode &
		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
		(ug_info->statisticsMode &
		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
		&ugeth->p_tx_glbl_pram->txrmonbaseptr,
		ugeth->tx_fw_statistics_pram_offset,
		&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
		ugeth->rx_fw_statistics_pram_offset,
		&ugeth->p_tx_glbl_pram->temoder,
		&ugeth->p_rx_glbl_pram->remoder);

	/* function code register */
	ugeth->p_rx_glbl_pram->rstate = function_code;

	/* initialize extended filtering */
	if (ug_info->rxExtendedFiltering) {
		if (!ug_info->extendedFilteringChainPointer) {
			ugeth_err("%s: Null Extended Filtering Chain Pointer.",
				  __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -EINVAL;
		}

		/* Allocate memory for extended filtering Mode Global
		Parameters */
		ugeth->exf_glbl_param_offset =
3115
		    qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
3116
		UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
3117
		if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
3118 3119 3120 3121 3122 3123 3124 3125
			ugeth_err
				("%s: Can not allocate DPRAM memory for"
				" p_exf_glbl_param.", __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return -ENOMEM;
		}

		ugeth->p_exf_glbl_param =
3126
		    (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140
				 exf_glbl_param_offset);
		out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
			 ugeth->exf_glbl_param_offset);
		out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
			 (u32) ug_info->extendedFilteringChainPointer);

	} else {		/* initialize 82xx style address filtering */

		/* Init individual address recognition registers to disabled */

		for (j = 0; j < NUM_OF_PADDRS; j++)
			ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);

		p_82xx_addr_filt =
3141
		    (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163
		    p_rx_glbl_pram->addressfiltering;

		ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
			ENET_ADDR_TYPE_GROUP);
		ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
			ENET_ADDR_TYPE_INDIVIDUAL);
	}

	/*
	 * Initialize UCC at QE level
	 */

	command = QE_INIT_TX_RX;

	/* Allocate shadow InitEnet command parameter structure.
	 * This is needed because after the InitEnet command is executed,
	 * the structure in DPRAM is released, because DPRAM is a premium
	 * resource.
	 * This shadow structure keeps a copy of what was done so that the
	 * allocated resources can be released when the channel is freed.
	 */
	if (!(ugeth->p_init_enet_param_shadow =
3164
	      kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
3165 3166 3167 3168 3169 3170 3171 3172
		ugeth_err
		    ("%s: Can not allocate memory for"
			" p_UccInitEnetParamShadows.", __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}
	/* Zero out *p_init_enet_param_shadow */
	memset((char *)ugeth->p_init_enet_param_shadow,
3173
	       0, sizeof(struct ucc_geth_init_pram));
3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206

	/* Fill shadow InitEnet command parameter structure */

	ugeth->p_init_enet_param_shadow->resinit1 =
	    ENET_INIT_PARAM_MAGIC_RES_INIT1;
	ugeth->p_init_enet_param_shadow->resinit2 =
	    ENET_INIT_PARAM_MAGIC_RES_INIT2;
	ugeth->p_init_enet_param_shadow->resinit3 =
	    ENET_INIT_PARAM_MAGIC_RES_INIT3;
	ugeth->p_init_enet_param_shadow->resinit4 =
	    ENET_INIT_PARAM_MAGIC_RES_INIT4;
	ugeth->p_init_enet_param_shadow->resinit5 =
	    ENET_INIT_PARAM_MAGIC_RES_INIT5;
	ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
	    ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
	ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
	    ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;

	ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
	    ugeth->rx_glbl_pram_offset | ug_info->riscRx;
	if ((ug_info->largestexternallookupkeysize !=
	     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
	    && (ug_info->largestexternallookupkeysize !=
		QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
	    && (ug_info->largestexternallookupkeysize !=
		QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
		ugeth_err("%s: Invalid largest External Lookup Key Size.",
			  __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -EINVAL;
	}
	ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
	    ug_info->largestexternallookupkeysize;
3207
	size = sizeof(struct ucc_geth_thread_rx_pram);
3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237
	if (ug_info->rxExtendedFiltering) {
		size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
		if (ug_info->largestexternallookupkeysize ==
		    QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
			size +=
			    THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
		if (ug_info->largestexternallookupkeysize ==
		    QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
			size +=
			    THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
	}

	if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
		p_init_enet_param_shadow->rxthread[0]),
		(u8) (numThreadsRxNumerical + 1)
		/* Rx needs one extra for terminator */
		, size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
		ug_info->riscRx, 1)) != 0) {
			ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
				__FUNCTION__);
		ucc_geth_memclean(ugeth);
		return ret_val;
	}

	ugeth->p_init_enet_param_shadow->txglobal =
	    ugeth->tx_glbl_pram_offset | ug_info->riscTx;
	if ((ret_val =
	     fill_init_enet_entries(ugeth,
				    &(ugeth->p_init_enet_param_shadow->
				      txthread[0]), numThreadsTxNumerical,
3238
				    sizeof(struct ucc_geth_thread_tx_pram),
3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257
				    UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
				    ug_info->riscTx, 0)) != 0) {
		ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
			  __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return ret_val;
	}

	/* Load Rx bds with buffers */
	for (i = 0; i < ug_info->numQueuesRx; i++) {
		if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
			ugeth_err("%s: Can not fill Rx bds with buffers.",
				  __FUNCTION__);
			ucc_geth_memclean(ugeth);
			return ret_val;
		}
	}

	/* Allocate InitEnet command parameter structure */
3258
	init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3259
	if (IS_ERR_VALUE(init_enet_pram_offset)) {
3260 3261 3262 3263 3264 3265 3266
		ugeth_err
		    ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
		     __FUNCTION__);
		ucc_geth_memclean(ugeth);
		return -ENOMEM;
	}
	p_init_enet_pram =
3267
	    (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291

	/* Copy shadow InitEnet command parameter structure into PRAM */
	p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
	p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
	p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
	p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
	out_be16(&p_init_enet_pram->resinit5,
		 ugeth->p_init_enet_param_shadow->resinit5);
	p_init_enet_pram->largestexternallookupkeysize =
	    ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
	out_be32(&p_init_enet_pram->rgftgfrxglobal,
		 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
	for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
		out_be32(&p_init_enet_pram->rxthread[i],
			 ugeth->p_init_enet_param_shadow->rxthread[i]);
	out_be32(&p_init_enet_pram->txglobal,
		 ugeth->p_init_enet_param_shadow->txglobal);
	for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
		out_be32(&p_init_enet_pram->txthread[i],
			 ugeth->p_init_enet_param_shadow->txthread[i]);

	/* Issue QE command */
	cecr_subblock =
	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3292
	qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303
		     init_enet_pram_offset);

	/* Free InitEnet command parameter */
	qe_muram_free(init_enet_pram_offset);

	return 0;
}

/* returns a net_device_stats structure pointer */
static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev)
{
3304
	struct ucc_geth_private *ugeth = netdev_priv(dev);
3305 3306 3307 3308 3309 3310 3311 3312 3313 3314

	return &(ugeth->stats);
}

/* ucc_geth_timeout gets called when a packet has not been
 * transmitted after a set amount of time.
 * For now, assume that clearing out all the structures, and
 * starting over will fix the problem. */
static void ucc_geth_timeout(struct net_device *dev)
{
3315
	struct ucc_geth_private *ugeth = netdev_priv(dev);
3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334

	ugeth_vdbg("%s: IN", __FUNCTION__);

	ugeth->stats.tx_errors++;

	ugeth_dump_regs(ugeth);

	if (dev->flags & IFF_UP) {
		ucc_geth_stop(ugeth);
		ucc_geth_startup(ugeth);
	}

	netif_schedule(dev);
}

/* This is called by the kernel when a frame is ready for transmission. */
/* It is pointed to by the dev->hard_start_xmit function pointer */
static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
3335
	struct ucc_geth_private *ugeth = netdev_priv(dev);
3336 3337 3338
#ifdef CONFIG_UGETH_TX_ON_DEMAND
	struct ucc_fast_private *uccf;
#endif
3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350
	u8 *bd;			/* BD pointer */
	u32 bd_status;
	u8 txQ = 0;

	ugeth_vdbg("%s: IN", __FUNCTION__);

	spin_lock_irq(&ugeth->lock);

	ugeth->stats.tx_bytes += skb->len;

	/* Start from the next BD that should be filled */
	bd = ugeth->txBd[txQ];
3351
	bd_status = in_be32((u32 *)bd);
3352 3353 3354 3355 3356 3357 3358 3359 3360
	/* Save the skb pointer so we can free it later */
	ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;

	/* Update the current skb pointer (wrapping if this was the last) */
	ugeth->skb_curtx[txQ] =
	    (ugeth->skb_curtx[txQ] +
	     1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);

	/* set up the buffer descriptor */
3361
	out_be32(&((struct qe_bd *)bd)->buf,
3362 3363
		      dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));

3364
	/* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3365 3366 3367

	bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;

3368 3369
	/* set bd status and length */
	out_be32((u32 *)bd, bd_status);
3370 3371 3372 3373 3374

	dev->trans_start = jiffies;

	/* Move to next BD in the ring */
	if (!(bd_status & T_W))
L
Li Yang 已提交
3375
		bd += sizeof(struct qe_bd);
3376
	else
L
Li Yang 已提交
3377
		bd = ugeth->p_tx_bd_ring[txQ];
3378 3379 3380 3381 3382 3383 3384 3385

	/* If the next BD still needs to be cleaned up, then the bds
	   are full.  We need to tell the kernel to stop sending us stuff. */
	if (bd == ugeth->confBd[txQ]) {
		if (!netif_queue_stopped(dev))
			netif_stop_queue(dev);
	}

L
Li Yang 已提交
3386 3387
	ugeth->txBd[txQ] = bd;

3388 3389 3390 3391 3392 3393 3394 3395 3396
	if (ugeth->p_scheduler) {
		ugeth->cpucount[txQ]++;
		/* Indicate to QE that there are more Tx bds ready for
		transmission */
		/* This is done by writing a running counter of the bd
		count to the scheduler PRAM. */
		out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
	}

3397 3398 3399 3400
#ifdef CONFIG_UGETH_TX_ON_DEMAND
	uccf = ugeth->uccf;
	out_be16(uccf->p_utodr, UCC_FAST_TOD);
#endif
3401 3402
	spin_unlock_irq(&ugeth->lock);

3403
	return 0;
3404 3405
}

3406
static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418
{
	struct sk_buff *skb;
	u8 *bd;
	u16 length, howmany = 0;
	u32 bd_status;
	u8 *bdBuffer;

	ugeth_vdbg("%s: IN", __FUNCTION__);

	/* collect received buffers */
	bd = ugeth->rxBd[rxQ];

3419
	bd_status = in_be32((u32 *)bd);
3420 3421 3422

	/* while there are received buffers and BD is full (~R_E) */
	while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3423
		bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476
		length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
		skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];

		/* determine whether buffer is first, last, first and last
		(single buffer frame) or middle (not first and not last) */
		if (!skb ||
		    (!(bd_status & (R_F | R_L))) ||
		    (bd_status & R_ERRORS_FATAL)) {
			ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x",
				   __FUNCTION__, __LINE__, (u32) skb);
			if (skb)
				dev_kfree_skb_any(skb);

			ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
			ugeth->stats.rx_dropped++;
		} else {
			ugeth->stats.rx_packets++;
			howmany++;

			/* Prep the skb for the packet */
			skb_put(skb, length);

			/* Tell the skb what kind of packet this is */
			skb->protocol = eth_type_trans(skb, ugeth->dev);

			ugeth->stats.rx_bytes += length;
			/* Send the packet up the stack */
#ifdef CONFIG_UGETH_NAPI
			netif_receive_skb(skb);
#else
			netif_rx(skb);
#endif				/* CONFIG_UGETH_NAPI */
		}

		ugeth->dev->last_rx = jiffies;

		skb = get_new_skb(ugeth, bd);
		if (!skb) {
			ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
			ugeth->stats.rx_dropped++;
			break;
		}

		ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;

		/* update to point at the next skb */
		ugeth->skb_currx[rxQ] =
		    (ugeth->skb_currx[rxQ] +
		     1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);

		if (bd_status & R_W)
			bd = ugeth->p_rx_bd_ring[rxQ];
		else
3477
			bd += sizeof(struct qe_bd);
3478

3479
		bd_status = in_be32((u32 *)bd);
3480 3481 3482 3483 3484 3485 3486 3487 3488
	}

	ugeth->rxBd[rxQ] = bd;
	return howmany;
}

static int ucc_geth_tx(struct net_device *dev, u8 txQ)
{
	/* Start from the next BD that should be filled */
3489
	struct ucc_geth_private *ugeth = netdev_priv(dev);
3490 3491 3492 3493
	u8 *bd;			/* BD pointer */
	u32 bd_status;

	bd = ugeth->confBd[txQ];
3494
	bd_status = in_be32((u32 *)bd);
3495 3496 3497 3498 3499 3500 3501

	/* Normal processing. */
	while ((bd_status & T_R) == 0) {
		/* BD contains already transmitted buffer.   */
		/* Handle the transmitted buffer and release */
		/* the BD to be used with the current frame  */

L
Li Yang 已提交
3502
		if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520
			break;

		ugeth->stats.tx_packets++;

		/* Free the sk buffer associated with this TxBD */
		dev_kfree_skb_irq(ugeth->
				  tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
		ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
		ugeth->skb_dirtytx[txQ] =
		    (ugeth->skb_dirtytx[txQ] +
		     1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);

		/* We freed a buffer, so now we can restart transmission */
		if (netif_queue_stopped(dev))
			netif_wake_queue(dev);

		/* Advance the confirmation BD pointer */
		if (!(bd_status & T_W))
L
Li Yang 已提交
3521
			bd += sizeof(struct qe_bd);
3522
		else
L
Li Yang 已提交
3523 3524
			bd = ugeth->p_tx_bd_ring[txQ];
		bd_status = in_be32((u32 *)bd);
3525
	}
L
Li Yang 已提交
3526
	ugeth->confBd[txQ] = bd;
3527 3528 3529 3530 3531 3532
	return 0;
}

#ifdef CONFIG_UGETH_NAPI
static int ucc_geth_poll(struct net_device *dev, int *budget)
{
3533
	struct ucc_geth_private *ugeth = netdev_priv(dev);
M
Michael Reiss 已提交
3534 3535
	struct ucc_geth_info *ug_info;
	struct ucc_fast_private *uccf;
3536
	int howmany;
M
Michael Reiss 已提交
3537 3538 3539
	u8 i;
	int rx_work_limit;
	register u32 uccm;
3540

M
Michael Reiss 已提交
3541 3542 3543
	ug_info = ugeth->ug_info;

	rx_work_limit = *budget;
3544 3545 3546
	if (rx_work_limit > dev->quota)
		rx_work_limit = dev->quota;

M
Michael Reiss 已提交
3547 3548 3549 3550 3551
	howmany = 0;

	for (i = 0; i < ug_info->numQueuesRx; i++) {
		howmany += ucc_geth_rx(ugeth, i, rx_work_limit);
	}
3552 3553 3554 3555 3556

	dev->quota -= howmany;
	rx_work_limit -= howmany;
	*budget -= howmany;

M
Michael Reiss 已提交
3557
	if (rx_work_limit > 0) {
3558
		netif_rx_complete(dev);
M
Michael Reiss 已提交
3559 3560 3561 3562 3563
		uccf = ugeth->uccf;
		uccm = in_be32(uccf->p_uccm);
		uccm |= UCCE_RX_EVENTS;
		out_be32(uccf->p_uccm, uccm);
	}
3564

M
Michael Reiss 已提交
3565
	return (rx_work_limit > 0) ? 0 : 1;
3566 3567 3568
}
#endif				/* CONFIG_UGETH_NAPI */

3569
static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3570 3571
{
	struct net_device *dev = (struct net_device *)info;
3572 3573 3574
	struct ucc_geth_private *ugeth = netdev_priv(dev);
	struct ucc_fast_private *uccf;
	struct ucc_geth_info *ug_info;
M
Michael Reiss 已提交
3575 3576 3577 3578 3579 3580 3581
	register u32 ucce;
	register u32 uccm;
#ifndef CONFIG_UGETH_NAPI
	register u32 rx_mask;
#endif
	register u32 tx_mask;
	u8 i;
3582 3583 3584 3585 3586 3587 3588 3589 3590

	ugeth_vdbg("%s: IN", __FUNCTION__);

	if (!ugeth)
		return IRQ_NONE;

	uccf = ugeth->uccf;
	ug_info = ugeth->ug_info;

M
Michael Reiss 已提交
3591 3592 3593 3594 3595
	/* read and clear events */
	ucce = (u32) in_be32(uccf->p_ucce);
	uccm = (u32) in_be32(uccf->p_uccm);
	ucce &= uccm;
	out_be32(uccf->p_ucce, ucce);
3596

M
Michael Reiss 已提交
3597 3598 3599 3600 3601 3602 3603 3604 3605 3606
	/* check for receive events that require processing */
	if (ucce & UCCE_RX_EVENTS) {
#ifdef CONFIG_UGETH_NAPI
		if (netif_rx_schedule_prep(dev)) {
		uccm &= ~UCCE_RX_EVENTS;
			out_be32(uccf->p_uccm, uccm);
			__netif_rx_schedule(dev);
		}
#else
		rx_mask = UCCE_RXBF_SINGLE_MASK;
3607
		for (i = 0; i < ug_info->numQueuesRx; i++) {
M
Michael Reiss 已提交
3608 3609 3610 3611
			if (ucce & rx_mask)
				ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
			ucce &= ~rx_mask;
			rx_mask <<= 1;
3612
		}
M
Michael Reiss 已提交
3613 3614
#endif /* CONFIG_UGETH_NAPI */
	}
3615

M
Michael Reiss 已提交
3616 3617 3618 3619
	/* Tx event processing */
	if (ucce & UCCE_TX_EVENTS) {
		spin_lock(&ugeth->lock);
		tx_mask = UCCE_TXBF_SINGLE_MASK;
3620 3621 3622 3623 3624 3625
		for (i = 0; i < ug_info->numQueuesTx; i++) {
			if (ucce & tx_mask)
				ucc_geth_tx(dev, i);
			ucce &= ~tx_mask;
			tx_mask <<= 1;
		}
M
Michael Reiss 已提交
3626 3627
		spin_unlock(&ugeth->lock);
	}
3628

M
Michael Reiss 已提交
3629 3630
	/* Errors and other events */
	if (ucce & UCCE_OTHER) {
3631 3632 3633
		if (ucce & UCCE_BSY) {
			ugeth->stats.rx_errors++;
		}
M
Michael Reiss 已提交
3634 3635
		if (ucce & UCCE_TXE) {
			ugeth->stats.tx_errors++;
3636 3637 3638 3639 3640 3641 3642 3643 3644 3645
		}
	}

	return IRQ_HANDLED;
}

/* Called when something needs to use the ethernet device */
/* Returns 0 for success. */
static int ucc_geth_open(struct net_device *dev)
{
3646
	struct ucc_geth_private *ugeth = netdev_priv(dev);
3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657
	int err;

	ugeth_vdbg("%s: IN", __FUNCTION__);

	/* Test station address */
	if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
		ugeth_err("%s: Multicast address used for station address"
			  " - is this what you wanted?", __FUNCTION__);
		return -EINVAL;
	}

3658 3659 3660 3661 3662 3663
	err = ucc_struct_init(ugeth);
	if (err) {
		ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
		return err;
	}

3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690
	err = ucc_geth_startup(ugeth);
	if (err) {
		ugeth_err("%s: Cannot configure net device, aborting.",
			  dev->name);
		return err;
	}

	err = adjust_enet_interface(ugeth);
	if (err) {
		ugeth_err("%s: Cannot configure net device, aborting.",
			  dev->name);
		return err;
	}

	/*       Set MACSTNADDR1, MACSTNADDR2                */
	/* For more details see the hardware spec.           */
	init_mac_station_addr_regs(dev->dev_addr[0],
				   dev->dev_addr[1],
				   dev->dev_addr[2],
				   dev->dev_addr[3],
				   dev->dev_addr[4],
				   dev->dev_addr[5],
				   &ugeth->ug_regs->macstnaddr1,
				   &ugeth->ug_regs->macstnaddr2);

	err = init_phy(dev);
	if (err) {
3691
		ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
3692 3693
		return err;
	}
3694 3695 3696

	phy_start(ugeth->phydev);

3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721
	err =
	    request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
			"UCC Geth", dev);
	if (err) {
		ugeth_err("%s: Cannot get IRQ for net device, aborting.",
			  dev->name);
		ucc_geth_stop(ugeth);
		return err;
	}

	err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
	if (err) {
		ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
		ucc_geth_stop(ugeth);
		return err;
	}

	netif_start_queue(dev);

	return err;
}

/* Stops the kernel queue, and halts the controller */
static int ucc_geth_close(struct net_device *dev)
{
3722
	struct ucc_geth_private *ugeth = netdev_priv(dev);
3723 3724 3725 3726 3727

	ugeth_vdbg("%s: IN", __FUNCTION__);

	ucc_geth_stop(ugeth);

3728 3729
	phy_disconnect(ugeth->phydev);
	ugeth->phydev = NULL;
3730 3731 3732 3733 3734 3735

	netif_stop_queue(dev);

	return 0;
}

3736
static phy_interface_t to_phy_interface(const char *phy_connection_type)
3737
{
3738
	if (strcasecmp(phy_connection_type, "mii") == 0)
3739
		return PHY_INTERFACE_MODE_MII;
3740
	if (strcasecmp(phy_connection_type, "gmii") == 0)
3741
		return PHY_INTERFACE_MODE_GMII;
3742
	if (strcasecmp(phy_connection_type, "tbi") == 0)
3743
		return PHY_INTERFACE_MODE_TBI;
3744
	if (strcasecmp(phy_connection_type, "rmii") == 0)
3745
		return PHY_INTERFACE_MODE_RMII;
3746
	if (strcasecmp(phy_connection_type, "rgmii") == 0)
3747
		return PHY_INTERFACE_MODE_RGMII;
3748
	if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3749
		return PHY_INTERFACE_MODE_RGMII_ID;
3750
	if (strcasecmp(phy_connection_type, "rtbi") == 0)
3751 3752 3753 3754 3755
		return PHY_INTERFACE_MODE_RTBI;

	return PHY_INTERFACE_MODE_MII;
}

3756
static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3757
{
3758 3759
	struct device *device = &ofdev->dev;
	struct device_node *np = ofdev->node;
3760
	struct device_node *mdio;
3761 3762 3763
	struct net_device *dev = NULL;
	struct ucc_geth_private *ugeth = NULL;
	struct ucc_geth_info *ug_info;
3764 3765
	struct resource res;
	struct device_node *phy;
3766
	int err, ucc_num, max_speed = 0;
3767 3768
	const phandle *ph;
	const unsigned int *prop;
3769
	const void *mac_addr;
3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782
	phy_interface_t phy_interface;
	static const int enet_to_speed[] = {
		SPEED_10, SPEED_10, SPEED_10,
		SPEED_100, SPEED_100, SPEED_100,
		SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
	};
	static const phy_interface_t enet_to_phy_interface[] = {
		PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
		PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
		PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
		PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
		PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
	};
3783 3784 3785

	ugeth_vdbg("%s: IN", __FUNCTION__);

3786
	prop = of_get_property(np, "device-id", NULL);
3787 3788 3789 3790 3791 3792
	ucc_num = *prop - 1;
	if ((ucc_num < 0) || (ucc_num > 7))
		return -ENODEV;

	ug_info = &ugeth_info[ucc_num];
	ug_info->uf_info.ucc_num = ucc_num;
3793

3794
	prop = of_get_property(np, "rx-clock", NULL);
3795
	ug_info->uf_info.rx_clock = *prop;
3796
	prop = of_get_property(np, "tx-clock", NULL);
3797 3798 3799 3800 3801 3802 3803 3804
	ug_info->uf_info.tx_clock = *prop;
	err = of_address_to_resource(np, 0, &res);
	if (err)
		return -EINVAL;

	ug_info->uf_info.regs = res.start;
	ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);

3805
	ph = of_get_property(np, "phy-handle", NULL);
3806
	phy = of_find_node_by_phandle(*ph);
3807

3808 3809 3810
	if (phy == NULL)
		return -ENODEV;

3811
	/* set the PHY address */
3812
	prop = of_get_property(phy, "reg", NULL);
3813 3814
	if (prop == NULL)
		return -1;
3815
	ug_info->phy_address = *prop;
3816 3817

	/* get the phy interface type, or default to MII */
3818
	prop = of_get_property(np, "phy-connection-type", NULL);
3819 3820
	if (!prop) {
		/* handle interface property present in old trees */
3821
		prop = of_get_property(phy, "interface", NULL);
3822
		if (prop != NULL) {
3823
			phy_interface = enet_to_phy_interface[*prop];
3824 3825
			max_speed = enet_to_speed[*prop];
		} else
3826 3827 3828 3829 3830
			phy_interface = PHY_INTERFACE_MODE_MII;
	} else {
		phy_interface = to_phy_interface((const char *)prop);
	}

3831 3832
	/* get speed, or derive from PHY interface */
	if (max_speed == 0)
3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846
		switch (phy_interface) {
		case PHY_INTERFACE_MODE_GMII:
		case PHY_INTERFACE_MODE_RGMII:
		case PHY_INTERFACE_MODE_RGMII_ID:
		case PHY_INTERFACE_MODE_TBI:
		case PHY_INTERFACE_MODE_RTBI:
			max_speed = SPEED_1000;
			break;
		default:
			max_speed = SPEED_100;
			break;
		}

	if (max_speed == SPEED_1000) {
3847
		/* configure muram FIFOs for gigabit operation */
3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868
		ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
		ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
		ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
		ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
		ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
		ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
	}

	/* Set the bus id */
	mdio = of_get_parent(phy);

	if (mdio == NULL)
		return -1;

	err = of_address_to_resource(mdio, 0, &res);
	of_node_put(mdio);

	if (err)
		return -1;

	ug_info->mdio_bus = res.start;
3869 3870 3871 3872 3873 3874 3875

	printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
		ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
		ug_info->uf_info.irq);

	if (ug_info == NULL) {
		ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__,
3876
			  ucc_num);
3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897
		return -ENODEV;
	}

	/* Create an ethernet device instance */
	dev = alloc_etherdev(sizeof(*ugeth));

	if (dev == NULL)
		return -ENOMEM;

	ugeth = netdev_priv(dev);
	spin_lock_init(&ugeth->lock);

	dev_set_drvdata(device, dev);

	/* Set the dev->base_addr to the gfar reg region */
	dev->base_addr = (unsigned long)(ug_info->uf_info.regs);

	SET_MODULE_OWNER(dev);
	SET_NETDEV_DEV(dev, device);

	/* Fill in the dev structure */
L
Li Yang 已提交
3898
	uec_set_ethtool_ops(dev);
3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912
	dev->open = ucc_geth_open;
	dev->hard_start_xmit = ucc_geth_start_xmit;
	dev->tx_timeout = ucc_geth_timeout;
	dev->watchdog_timeo = TX_TIMEOUT;
#ifdef CONFIG_UGETH_NAPI
	dev->poll = ucc_geth_poll;
	dev->weight = UCC_GETH_DEV_WEIGHT;
#endif				/* CONFIG_UGETH_NAPI */
	dev->stop = ucc_geth_close;
	dev->get_stats = ucc_geth_get_stats;
//    dev->change_mtu = ucc_geth_change_mtu;
	dev->mtu = 1500;
	dev->set_multicast_list = ucc_geth_set_multi;

3913 3914 3915 3916
	ugeth->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
	ugeth->phy_interface = phy_interface;
	ugeth->max_speed = max_speed;

3917 3918 3919 3920 3921 3922 3923 3924
	err = register_netdev(dev);
	if (err) {
		ugeth_err("%s: Cannot register net device, aborting.",
			  dev->name);
		free_netdev(dev);
		return err;
	}

T
Timur Tabi 已提交
3925
	mac_addr = of_get_mac_address(np);
3926 3927
	if (mac_addr)
		memcpy(dev->dev_addr, mac_addr, 6);
3928

3929 3930 3931
	ugeth->ug_info = ug_info;
	ugeth->dev = dev;

3932 3933 3934
	return 0;
}

3935
static int ucc_geth_remove(struct of_device* ofdev)
3936
{
3937
	struct device *device = &ofdev->dev;
3938 3939 3940 3941 3942 3943 3944 3945 3946 3947
	struct net_device *dev = dev_get_drvdata(device);
	struct ucc_geth_private *ugeth = netdev_priv(dev);

	dev_set_drvdata(device, NULL);
	ucc_geth_memclean(ugeth);
	free_netdev(dev);

	return 0;
}

3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962
static struct of_device_id ucc_geth_match[] = {
	{
		.type = "network",
		.compatible = "ucc_geth",
	},
	{},
};

MODULE_DEVICE_TABLE(of, ucc_geth_match);

static struct of_platform_driver ucc_geth_driver = {
	.name		= DRV_NAME,
	.match_table	= ucc_geth_match,
	.probe		= ucc_geth_probe,
	.remove		= ucc_geth_remove,
3963 3964 3965 3966
};

static int __init ucc_geth_init(void)
{
3967 3968 3969 3970 3971 3972
	int i, ret;

	ret = uec_mdio_init();

	if (ret)
		return ret;
3973

3974 3975 3976 3977 3978
	printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
	for (i = 0; i < 8; i++)
		memcpy(&(ugeth_info[i]), &ugeth_primary_info,
		       sizeof(ugeth_primary_info));

3979 3980 3981 3982 3983 3984
	ret = of_register_platform_driver(&ucc_geth_driver);

	if (ret)
		uec_mdio_exit();

	return ret;
3985 3986 3987 3988
}

static void __exit ucc_geth_exit(void)
{
3989
	of_unregister_platform_driver(&ucc_geth_driver);
3990
	uec_mdio_exit();
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}

module_init(ucc_geth_init);
module_exit(ucc_geth_exit);

MODULE_AUTHOR("Freescale Semiconductor, Inc");
MODULE_DESCRIPTION(DRV_DESC);
K
Kim Phillips 已提交
3998
MODULE_VERSION(DRV_VERSION);
3999
MODULE_LICENSE("GPL");