irq.c 8.7 KB
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/*
 * Common interrupt code for 32 and 64 bit
 */
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
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#include <linux/of.h>
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#include <linux/seq_file.h>
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#include <linux/smp.h>
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#include <linux/ftrace.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/irq.h>
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#include <asm/idle.h>
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#include <asm/mce.h>
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#include <asm/hw_irq.h>
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atomic_t irq_err_count;

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/* Function pointer for generic interrupt vector handling */
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void (*x86_platform_ipi_callback)(void) = NULL;
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/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
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	if (printk_ratelimit())
		pr_err("unexpected IRQ trap at vector %02x\n", irq);
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	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But only ack when the APIC is enabled -AK
	 */
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	ack_APIC_irq();
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}

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#define irq_stats(x)		(&per_cpu(irq_stat, x))
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/*
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 * /proc/interrupts printing for arch specific interrupts
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 */
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
	int j;

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	seq_printf(p, "%*s: ", prec, "NMI");
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	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
	seq_printf(p, "  Non-maskable interrupts\n");
#ifdef CONFIG_X86_LOCAL_APIC
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	seq_printf(p, "%*s: ", prec, "LOC");
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	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
	seq_printf(p, "  Local timer interrupts\n");
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	seq_printf(p, "%*s: ", prec, "SPU");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
	seq_printf(p, "  Spurious interrupts\n");
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	seq_printf(p, "%*s: ", prec, "PMI");
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	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
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	seq_printf(p, "  Performance monitoring interrupts\n");
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	seq_printf(p, "%*s: ", prec, "IWI");
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	for_each_online_cpu(j)
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		seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
	seq_printf(p, "  IRQ work interrupts\n");
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	seq_printf(p, "%*s: ", prec, "RTR");
	for_each_online_cpu(j)
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		seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
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	seq_printf(p, "  APIC ICR read retries\n");
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#endif
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	if (x86_platform_ipi_callback) {
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		seq_printf(p, "%*s: ", prec, "PLT");
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		for_each_online_cpu(j)
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			seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
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		seq_printf(p, "  Platform interrupts\n");
	}
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#ifdef CONFIG_SMP
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	seq_printf(p, "%*s: ", prec, "RES");
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	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
	seq_printf(p, "  Rescheduling interrupts\n");
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	seq_printf(p, "%*s: ", prec, "CAL");
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	for_each_online_cpu(j)
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		seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
					irq_stats(j)->irq_tlb_count);
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	seq_printf(p, "  Function call interrupts\n");
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	seq_printf(p, "%*s: ", prec, "TLB");
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	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
	seq_printf(p, "  TLB shootdowns\n");
#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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	seq_printf(p, "%*s: ", prec, "TRM");
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	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
	seq_printf(p, "  Thermal event interrupts\n");
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#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
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	seq_printf(p, "%*s: ", prec, "THR");
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	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
	seq_printf(p, "  Threshold APIC interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE
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	seq_printf(p, "%*s: ", prec, "MCE");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
	seq_printf(p, "  Machine check exceptions\n");
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	seq_printf(p, "%*s: ", prec, "MCP");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
	seq_printf(p, "  Machine check polls\n");
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#endif
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	seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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#if defined(CONFIG_X86_IO_APIC)
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	seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
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#endif
	return 0;
}

/*
 * /proc/stat helpers
 */
u64 arch_irq_stat_cpu(unsigned int cpu)
{
	u64 sum = irq_stats(cpu)->__nmi_count;

#ifdef CONFIG_X86_LOCAL_APIC
	sum += irq_stats(cpu)->apic_timer_irqs;
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	sum += irq_stats(cpu)->irq_spurious_count;
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	sum += irq_stats(cpu)->apic_perf_irqs;
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	sum += irq_stats(cpu)->apic_irq_work_irqs;
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	sum += irq_stats(cpu)->icr_read_retry_count;
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#endif
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	if (x86_platform_ipi_callback)
		sum += irq_stats(cpu)->x86_platform_ipis;
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#ifdef CONFIG_SMP
	sum += irq_stats(cpu)->irq_resched_count;
	sum += irq_stats(cpu)->irq_call_count;
#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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	sum += irq_stats(cpu)->irq_thermal_count;
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#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
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	sum += irq_stats(cpu)->irq_threshold_count;
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#endif
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#ifdef CONFIG_X86_MCE
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	sum += per_cpu(mce_exception_count, cpu);
	sum += per_cpu(mce_poll_count, cpu);
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#endif
	return sum;
}

u64 arch_irq_stat(void)
{
	u64 sum = atomic_read(&irq_err_count);

#ifdef CONFIG_X86_IO_APIC
	sum += atomic_read(&irq_mis_count);
#endif
	return sum;
}
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/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/* high bit used in ret_from_ code  */
	unsigned vector = ~regs->orig_ax;
	unsigned irq;

	irq_enter();
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	exit_idle();
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	irq = __this_cpu_read(vector_irq[vector]);
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	if (!handle_irq(irq, regs)) {
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		ack_APIC_irq();
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		if (printk_ratelimit())
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			pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
				__func__, smp_processor_id(), vector, irq);
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	}

	irq_exit();

	set_irq_regs(old_regs);
	return 1;
}

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/*
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 * Handler for X86_PLATFORM_IPI_VECTOR.
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 */
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void smp_x86_platform_ipi(struct pt_regs *regs)
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{
	struct pt_regs *old_regs = set_irq_regs(regs);

	ack_APIC_irq();

	irq_enter();

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	exit_idle();

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	inc_irq_stat(x86_platform_ipis);
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	if (x86_platform_ipi_callback)
		x86_platform_ipi_callback();
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	irq_exit();

	set_irq_regs(old_regs);
}

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EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
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#ifdef CONFIG_HOTPLUG_CPU
/* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
void fixup_irqs(void)
{
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	unsigned int irq, vector;
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	static int warned;
	struct irq_desc *desc;
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	struct irq_data *data;
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	struct irq_chip *chip;
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	for_each_irq_desc(irq, desc) {
		int break_affinity = 0;
		int set_affinity = 1;
		const struct cpumask *affinity;

		if (!desc)
			continue;
		if (irq == 2)
			continue;

		/* interrupt's are disabled at this point */
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		raw_spin_lock(&desc->lock);
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		data = irq_desc_get_irq_data(desc);
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		affinity = data->affinity;
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		if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
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		    cpumask_subset(affinity, cpu_online_mask)) {
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			raw_spin_unlock(&desc->lock);
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			continue;
		}

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		/*
		 * Complete the irq move. This cpu is going down and for
		 * non intr-remapping case, we can't wait till this interrupt
		 * arrives at this cpu before completing the irq move.
		 */
		irq_force_complete_move(irq);

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		if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
			break_affinity = 1;
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			affinity = cpu_online_mask;
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		}

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		chip = irq_data_get_irq_chip(data);
		if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
			chip->irq_mask(data);
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		if (chip->irq_set_affinity)
			chip->irq_set_affinity(data, affinity, true);
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		else if (!(warned++))
			set_affinity = 0;

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		/*
		 * We unmask if the irq was not marked masked by the
		 * core code. That respects the lazy irq disable
		 * behaviour.
		 */
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		if (!irqd_can_move_in_process_context(data) &&
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		    !irqd_irq_masked(data) && chip->irq_unmask)
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			chip->irq_unmask(data);
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		raw_spin_unlock(&desc->lock);
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		if (break_affinity && set_affinity)
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			pr_notice("Broke affinity for irq %i\n", irq);
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		else if (!set_affinity)
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			pr_notice("Cannot set affinity for irq %i\n", irq);
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	}

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	/*
	 * We can remove mdelay() and then send spuriuous interrupts to
	 * new cpu targets for all the irqs that were handled previously by
	 * this cpu. While it works, I have seen spurious interrupt messages
	 * (nothing wrong but still...).
	 *
	 * So for now, retain mdelay(1) and check the IRR and then send those
	 * interrupts to new targets as this cpu is already offlined...
	 */
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	mdelay(1);
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	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
		unsigned int irr;

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		if (__this_cpu_read(vector_irq[vector]) < 0)
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			continue;

		irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
		if (irr  & (1 << (vector % 32))) {
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			irq = __this_cpu_read(vector_irq[vector]);
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			desc = irq_to_desc(irq);
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			data = irq_desc_get_irq_data(desc);
			chip = irq_data_get_irq_chip(data);
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			raw_spin_lock(&desc->lock);
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			if (chip->irq_retrigger)
				chip->irq_retrigger(data);
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			raw_spin_unlock(&desc->lock);
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		}
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		__this_cpu_write(vector_irq[vector], -1);
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	}
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}
#endif