init.c 25.1 KB
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/*
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 * Copyright (c) 2008-2011 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/ath9k_platform.h>
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#include "ath9k.h"

static char *dev_info = "ath9k";

MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
module_param_named(debug, ath9k_debug, uint, 0);
MODULE_PARM_DESC(debug, "Debugging mask");

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int ath9k_modparam_nohwcrypt;
module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
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MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");

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int led_blink;
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module_param_named(blink, led_blink, int, 0444);
MODULE_PARM_DESC(blink, "Enable LED blink on activity");

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static int ath9k_btcoex_enable;
module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");

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bool is_ath9k_unloaded;
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/* We use the hw_value as an index into our private channel structure */

#define CHAN2G(_freq, _idx)  { \
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	.band = IEEE80211_BAND_2GHZ, \
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	.center_freq = (_freq), \
	.hw_value = (_idx), \
	.max_power = 20, \
}

#define CHAN5G(_freq, _idx) { \
	.band = IEEE80211_BAND_5GHZ, \
	.center_freq = (_freq), \
	.hw_value = (_idx), \
	.max_power = 20, \
}

/* Some 2 GHz radios are actually tunable on 2312-2732
 * on 5 MHz steps, we support the channels which we know
 * we have calibration data for all cards though to make
 * this static */
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static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
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	CHAN2G(2412, 0), /* Channel 1 */
	CHAN2G(2417, 1), /* Channel 2 */
	CHAN2G(2422, 2), /* Channel 3 */
	CHAN2G(2427, 3), /* Channel 4 */
	CHAN2G(2432, 4), /* Channel 5 */
	CHAN2G(2437, 5), /* Channel 6 */
	CHAN2G(2442, 6), /* Channel 7 */
	CHAN2G(2447, 7), /* Channel 8 */
	CHAN2G(2452, 8), /* Channel 9 */
	CHAN2G(2457, 9), /* Channel 10 */
	CHAN2G(2462, 10), /* Channel 11 */
	CHAN2G(2467, 11), /* Channel 12 */
	CHAN2G(2472, 12), /* Channel 13 */
	CHAN2G(2484, 13), /* Channel 14 */
};

/* Some 5 GHz radios are actually tunable on XXXX-YYYY
 * on 5 MHz steps, we support the channels which we know
 * we have calibration data for all cards though to make
 * this static */
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static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
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	/* _We_ call this UNII 1 */
	CHAN5G(5180, 14), /* Channel 36 */
	CHAN5G(5200, 15), /* Channel 40 */
	CHAN5G(5220, 16), /* Channel 44 */
	CHAN5G(5240, 17), /* Channel 48 */
	/* _We_ call this UNII 2 */
	CHAN5G(5260, 18), /* Channel 52 */
	CHAN5G(5280, 19), /* Channel 56 */
	CHAN5G(5300, 20), /* Channel 60 */
	CHAN5G(5320, 21), /* Channel 64 */
	/* _We_ call this "Middle band" */
	CHAN5G(5500, 22), /* Channel 100 */
	CHAN5G(5520, 23), /* Channel 104 */
	CHAN5G(5540, 24), /* Channel 108 */
	CHAN5G(5560, 25), /* Channel 112 */
	CHAN5G(5580, 26), /* Channel 116 */
	CHAN5G(5600, 27), /* Channel 120 */
	CHAN5G(5620, 28), /* Channel 124 */
	CHAN5G(5640, 29), /* Channel 128 */
	CHAN5G(5660, 30), /* Channel 132 */
	CHAN5G(5680, 31), /* Channel 136 */
	CHAN5G(5700, 32), /* Channel 140 */
	/* _We_ call this UNII 3 */
	CHAN5G(5745, 33), /* Channel 149 */
	CHAN5G(5765, 34), /* Channel 153 */
	CHAN5G(5785, 35), /* Channel 157 */
	CHAN5G(5805, 36), /* Channel 161 */
	CHAN5G(5825, 37), /* Channel 165 */
};

/* Atheros hardware rate code addition for short premble */
#define SHPCHECK(__hw_rate, __flags) \
	((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)

#define RATE(_bitrate, _hw_rate, _flags) {              \
	.bitrate        = (_bitrate),                   \
	.flags          = (_flags),                     \
	.hw_value       = (_hw_rate),                   \
	.hw_value_short = (SHPCHECK(_hw_rate, _flags))  \
}

static struct ieee80211_rate ath9k_legacy_rates[] = {
	RATE(10, 0x1b, 0),
	RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
	RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
	RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
	RATE(60, 0x0b, 0),
	RATE(90, 0x0f, 0),
	RATE(120, 0x0a, 0),
	RATE(180, 0x0e, 0),
	RATE(240, 0x09, 0),
	RATE(360, 0x0d, 0),
	RATE(480, 0x08, 0),
	RATE(540, 0x0c, 0),
};

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#ifdef CONFIG_MAC80211_LEDS
static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
	{ .throughput = 0 * 1024, .blink_time = 334 },
	{ .throughput = 1 * 1024, .blink_time = 260 },
	{ .throughput = 5 * 1024, .blink_time = 220 },
	{ .throughput = 10 * 1024, .blink_time = 190 },
	{ .throughput = 20 * 1024, .blink_time = 170 },
	{ .throughput = 50 * 1024, .blink_time = 150 },
	{ .throughput = 70 * 1024, .blink_time = 130 },
	{ .throughput = 100 * 1024, .blink_time = 110 },
	{ .throughput = 200 * 1024, .blink_time = 80 },
	{ .throughput = 300 * 1024, .blink_time = 50 },
};
#endif

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static void ath9k_deinit_softc(struct ath_softc *sc);
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/*
 * Read and write, they both share the same lock. We do this to serialize
 * reads and writes on Atheros 802.11n PCI devices only. This is required
 * as the FIFO on these devices can only accept sanely 2 requests.
 */

static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
{
	struct ath_hw *ah = (struct ath_hw *) hw_priv;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_softc *sc = (struct ath_softc *) common->priv;

	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
		unsigned long flags;
		spin_lock_irqsave(&sc->sc_serial_rw, flags);
		iowrite32(val, sc->mem + reg_offset);
		spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
	} else
		iowrite32(val, sc->mem + reg_offset);
}

static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
{
	struct ath_hw *ah = (struct ath_hw *) hw_priv;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	u32 val;

	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
		unsigned long flags;
		spin_lock_irqsave(&sc->sc_serial_rw, flags);
		val = ioread32(sc->mem + reg_offset);
		spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
	} else
		val = ioread32(sc->mem + reg_offset);
	return val;
}

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static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
				    u32 set, u32 clr)
{
	u32 val;

	val = ioread32(sc->mem + reg_offset);
	val &= ~clr;
	val |= set;
	iowrite32(val, sc->mem + reg_offset);

	return val;
}

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static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
{
	struct ath_hw *ah = (struct ath_hw *) hw_priv;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	unsigned long uninitialized_var(flags);
	u32 val;

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	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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		spin_lock_irqsave(&sc->sc_serial_rw, flags);
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		val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
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		spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
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	} else
		val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
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	return val;
}

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/**************************/
/*     Initialization     */
/**************************/

static void setup_ht_cap(struct ath_softc *sc,
			 struct ieee80211_sta_ht_cap *ht_info)
{
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	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
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	u8 tx_streams, rx_streams;
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	int i, max_streams;
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	ht_info->ht_supported = true;
	ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
		       IEEE80211_HT_CAP_SM_PS |
		       IEEE80211_HT_CAP_SGI_40 |
		       IEEE80211_HT_CAP_DSSSCCK40;

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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
		ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;

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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
		ht_info->cap |= IEEE80211_HT_CAP_SGI_20;

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	ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
	ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;

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	if (AR_SREV_9330(ah) || AR_SREV_9485(ah))
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		max_streams = 1;
	else if (AR_SREV_9300_20_OR_LATER(ah))
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		max_streams = 3;
	else
		max_streams = 2;

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	if (AR_SREV_9280_20_OR_LATER(ah)) {
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		if (max_streams >= 2)
			ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
		ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
	}

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	/* set up supported mcs set */
	memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
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	tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
	rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
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	ath_dbg(common, ATH_DBG_CONFIG,
		"TX streams %d, RX streams: %d\n",
		tx_streams, rx_streams);
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	if (tx_streams != rx_streams) {
		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
		ht_info->mcs.tx_params |= ((tx_streams - 1) <<
				IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
	}

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	for (i = 0; i < rx_streams; i++)
		ht_info->mcs.rx_mask[i] = 0xff;
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	ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
}

static int ath9k_reg_notifier(struct wiphy *wiphy,
			      struct regulatory_request *request)
{
	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
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	struct ath_softc *sc = hw->priv;
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	struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);

	return ath_reg_notifier_apply(wiphy, request, reg);
}

/*
 *  This function will allocate both the DMA descriptor structure, and the
 *  buffers it contains.  These are used to contain the descriptors used
 *  by the system.
*/
int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
		      struct list_head *head, const char *name,
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		      int nbuf, int ndesc, bool is_tx)
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{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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	u8 *ds;
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	struct ath_buf *bf;
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	int i, bsize, error, desc_len;
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	ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
		name, nbuf, ndesc);
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	INIT_LIST_HEAD(head);
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	if (is_tx)
		desc_len = sc->sc_ah->caps.tx_desc_len;
	else
		desc_len = sizeof(struct ath_desc);

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	/* ath_desc must be a multiple of DWORDs */
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	if ((desc_len % 4) != 0) {
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		ath_err(common, "ath_desc not DWORD aligned\n");
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		BUG_ON((desc_len % 4) != 0);
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		error = -ENOMEM;
		goto fail;
	}

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	dd->dd_desc_len = desc_len * nbuf * ndesc;
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	/*
	 * Need additional DMA memory because we can't use
	 * descriptors that cross the 4K page boundary. Assume
	 * one skipped descriptor per 4K page.
	 */
	if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
		u32 ndesc_skipped =
			ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
		u32 dma_len;

		while (ndesc_skipped) {
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			dma_len = ndesc_skipped * desc_len;
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			dd->dd_desc_len += dma_len;

			ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
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		}
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	}

	/* allocate descriptors */
	dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
					 &dd->dd_desc_paddr, GFP_KERNEL);
	if (dd->dd_desc == NULL) {
		error = -ENOMEM;
		goto fail;
	}
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	ds = (u8 *) dd->dd_desc;
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	ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
		name, ds, (u32) dd->dd_desc_len,
		ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
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	/* allocate buffers */
	bsize = sizeof(struct ath_buf) * nbuf;
	bf = kzalloc(bsize, GFP_KERNEL);
	if (bf == NULL) {
		error = -ENOMEM;
		goto fail2;
	}
	dd->dd_bufptr = bf;

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	for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
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		bf->bf_desc = ds;
		bf->bf_daddr = DS2PHYS(dd, ds);

		if (!(sc->sc_ah->caps.hw_caps &
		      ATH9K_HW_CAP_4KB_SPLITTRANS)) {
			/*
			 * Skip descriptor addresses which can cause 4KB
			 * boundary crossing (addr + length) with a 32 dword
			 * descriptor fetch.
			 */
			while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
				BUG_ON((caddr_t) bf->bf_desc >=
				       ((caddr_t) dd->dd_desc +
					dd->dd_desc_len));

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				ds += (desc_len * ndesc);
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				bf->bf_desc = ds;
				bf->bf_daddr = DS2PHYS(dd, ds);
			}
		}
		list_add_tail(&bf->list, head);
	}
	return 0;
fail2:
	dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
			  dd->dd_desc_paddr);
fail:
	memset(dd, 0, sizeof(*dd));
	return error;
}

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void ath9k_init_crypto(struct ath_softc *sc)
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{
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	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	int i = 0;
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	/* Get the hardware key cache size. */
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	common->keymax = AR_KEYTABLE_SIZE;
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	/*
	 * Reset the key cache since some parts do not
	 * reset the contents on initial power up.
	 */
	for (i = 0; i < common->keymax; i++)
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		ath_hw_keyreset(common, (u16) i);
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	/*
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	 * Check whether the separate key cache entries
	 * are required to handle both tx+rx MIC keys.
	 * With split mic keys the number of stations is limited
	 * to 27 otherwise 59.
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	 */
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	if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
		common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
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}

static int ath9k_init_btcoex(struct ath_softc *sc)
{
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	struct ath_txq *txq;
	int r;
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	switch (sc->sc_ah->btcoex_hw.scheme) {
	case ATH_BTCOEX_CFG_NONE:
		break;
	case ATH_BTCOEX_CFG_2WIRE:
		ath9k_hw_btcoex_init_2wire(sc->sc_ah);
		break;
	case ATH_BTCOEX_CFG_3WIRE:
		ath9k_hw_btcoex_init_3wire(sc->sc_ah);
		r = ath_init_btcoex_timer(sc);
		if (r)
			return -1;
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		txq = sc->tx.txq_map[WME_AC_BE];
		ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
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		sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
		break;
	default:
		WARN_ON(1);
		break;
	}

	return 0;
}

static int ath9k_init_queues(struct ath_softc *sc)
{
	int i = 0;

	sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
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	sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);

	sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
	ath_cabq_update(sc);

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	for (i = 0; i < WME_NUM_AC; i++) {
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		sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
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		sc->tx.txq_map[i]->mac80211_qnum = i;
	}
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	return 0;
}

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static int ath9k_init_channels_rates(struct ath_softc *sc)
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{
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	void *channels;

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	BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
		     ARRAY_SIZE(ath9k_5ghz_chantable) !=
		     ATH9K_NUM_CHANNELS);

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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
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		channels = kmemdup(ath9k_2ghz_chantable,
			sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
		if (!channels)
		    return -ENOMEM;

		sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
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		sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
		sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
			ARRAY_SIZE(ath9k_2ghz_chantable);
		sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
		sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
			ARRAY_SIZE(ath9k_legacy_rates);
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	}

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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
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		channels = kmemdup(ath9k_5ghz_chantable,
			sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
		if (!channels) {
			if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
				kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
			return -ENOMEM;
		}

		sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
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		sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
		sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
			ARRAY_SIZE(ath9k_5ghz_chantable);
		sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
			ath9k_legacy_rates + 4;
		sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
			ARRAY_SIZE(ath9k_legacy_rates) - 4;
	}
518
	return 0;
S
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519
}
S
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520

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521 522 523 524 525
static void ath9k_init_misc(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	int i = 0;
	setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
S
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526 527 528

	sc->config.txpowlimit = ATH_TXPOWER_MAX;

S
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529
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
S
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530 531 532 533
		sc->sc_flags |= SC_OP_TXAGGR;
		sc->sc_flags |= SC_OP_RXAGGR;
	}

S
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534 535
	common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
	common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
S
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536

537
	ath9k_hw_set_diversity(sc->sc_ah, true);
S
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538
	sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
S
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539

540
	memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
S
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541

S
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542
	sc->beacon.slottime = ATH9K_SLOT_TIME_9;
S
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543

544
	for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
S
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545
		sc->beacon.bslot[i] = NULL;
546 547 548

	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
		sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
S
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549
}
S
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550

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static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
			    const struct ath_bus_ops *bus_ops)
{
554
	struct ath9k_platform_data *pdata = sc->dev->platform_data;
S
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555 556 557 558
	struct ath_hw *ah = NULL;
	struct ath_common *common;
	int ret = 0, i;
	int csz = 0;
S
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559

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560 561 562 563
	ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
	if (!ah)
		return -ENOMEM;

B
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564
	ah->hw = sc->hw;
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565 566
	ah->hw_version.devid = devid;
	ah->hw_version.subsysid = subsysid;
567 568
	ah->reg_ops.read = ath9k_ioread32;
	ah->reg_ops.write = ath9k_iowrite32;
569
	ah->reg_ops.rmw = ath9k_reg_rmw;
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570 571
	sc->sc_ah = ah;

572
	if (!pdata) {
573
		ah->ah_flags |= AH_USE_EEPROM;
574 575 576 577 578
		sc->sc_ah->led_pin = -1;
	} else {
		sc->sc_ah->gpio_mask = pdata->gpio_mask;
		sc->sc_ah->gpio_val = pdata->gpio_val;
		sc->sc_ah->led_pin = pdata->led_pin;
579
		ah->is_clk_25mhz = pdata->is_clk_25mhz;
580
		ah->get_mac_revision = pdata->get_mac_revision;
581
		ah->external_reset = pdata->external_reset;
582
	}
583

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584
	common = ath9k_hw_common(ah);
585
	common->ops = &ah->reg_ops;
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586 587 588 589 590
	common->bus_ops = bus_ops;
	common->ah = ah;
	common->hw = sc->hw;
	common->priv = sc;
	common->debug_mask = ath9k_debug;
591
	common->btcoex_enabled = ath9k_btcoex_enable == 1;
592
	common->disable_ani = false;
593
	spin_lock_init(&common->cc_lock);
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594 595 596 597

	spin_lock_init(&sc->sc_serial_rw);
	spin_lock_init(&sc->sc_pm_lock);
	mutex_init(&sc->mutex);
598 599 600 601
#ifdef CONFIG_ATH9K_DEBUGFS
	spin_lock_init(&sc->nodes_lock);
	INIT_LIST_HEAD(&sc->nodes);
#endif
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602 603 604 605 606 607 608 609 610 611 612
	tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
	tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
		     (unsigned long)sc);

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	ath_read_cachesize(common, &csz);
	common->cachelsz = csz << 2; /* convert to bytes */

613
	/* Initializes the hardware for all supported chipsets */
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614
	ret = ath9k_hw_init(ah);
615
	if (ret)
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616
		goto err_hw;
S
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617

618 619 620
	if (pdata && pdata->macaddr)
		memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);

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621 622 623 624 625 626 627 628
	ret = ath9k_init_queues(sc);
	if (ret)
		goto err_queues;

	ret =  ath9k_init_btcoex(sc);
	if (ret)
		goto err_btcoex;

629 630 631 632
	ret = ath9k_init_channels_rates(sc);
	if (ret)
		goto err_btcoex;

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633 634 635
	ath9k_init_crypto(sc);
	ath9k_init_misc(sc);

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636
	return 0;
S
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637 638

err_btcoex:
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639 640 641
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);
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642 643 644
err_queues:
	ath9k_hw_deinit(ah);
err_hw:
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645

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646 647 648 649
	kfree(ah);
	sc->sc_ah = NULL;

	return ret;
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650 651
}

652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672
static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
{
	struct ieee80211_supported_band *sband;
	struct ieee80211_channel *chan;
	struct ath_hw *ah = sc->sc_ah;
	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
	int i;

	sband = &sc->sbands[band];
	for (i = 0; i < sband->n_channels; i++) {
		chan = &sband->channels[i];
		ah->curchan = &ah->channels[chan->hw_value];
		ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
		ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
		chan->max_power = reg->max_power_level / 2;
	}
}

static void ath9k_init_txpower_limits(struct ath_softc *sc)
{
	struct ath_hw *ah = sc->sc_ah;
673
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
674 675
	struct ath9k_channel *curchan = ah->curchan;

676
	ah->txchainmask = common->tx_chainmask;
677 678 679 680 681 682 683 684
	if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
		ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
	if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
		ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);

	ah->curchan = curchan;
}

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685
void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
S
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686
{
S
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687 688
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);

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689 690 691 692 693
	hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
		IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
		IEEE80211_HW_SIGNAL_DBM |
		IEEE80211_HW_SUPPORTS_PS |
		IEEE80211_HW_PS_NULLFUNC_STACK |
694
		IEEE80211_HW_SPECTRUM_MGMT |
695
		IEEE80211_HW_REPORTS_TX_ACK_STATUS;
S
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696

697 698 699
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
		 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;

700
	if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
S
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701 702 703
		hw->flags |= IEEE80211_HW_MFP_CAPABLE;

	hw->wiphy->interface_modes =
J
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704 705
		BIT(NL80211_IFTYPE_P2P_GO) |
		BIT(NL80211_IFTYPE_P2P_CLIENT) |
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706
		BIT(NL80211_IFTYPE_AP) |
B
Bill Jordan 已提交
707
		BIT(NL80211_IFTYPE_WDS) |
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708 709 710 711
		BIT(NL80211_IFTYPE_STATION) |
		BIT(NL80211_IFTYPE_ADHOC) |
		BIT(NL80211_IFTYPE_MESH_POINT);

712 713
	if (AR_SREV_5416(sc->sc_ah))
		hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
S
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714

J
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715 716
	hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;

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717 718 719 720
	hw->queues = 4;
	hw->max_rates = 4;
	hw->channel_change_time = 5000;
	hw->max_listen_interval = 10;
721
	hw->max_rate_tries = 10;
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722 723 724
	hw->sta_data_size = sizeof(struct ath_node);
	hw->vif_data_size = sizeof(struct ath_vif);

725
#ifdef CONFIG_ATH9K_RATE_CONTROL
S
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726
	hw->rate_control_algorithm = "ath9k_rate_control";
727
#endif
S
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728

729
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
S
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730 731
		hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
			&sc->sbands[IEEE80211_BAND_2GHZ];
732
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
S
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733 734
		hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
			&sc->sbands[IEEE80211_BAND_5GHZ];
S
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735 736

	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
737
		if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
S
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738
			setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
739
		if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
S
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740 741 742 743
			setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
	}

	SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
S
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744 745
}

S
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746
int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
S
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747 748 749 750 751
		    const struct ath_bus_ops *bus_ops)
{
	struct ieee80211_hw *hw = sc->hw;
	struct ath_common *common;
	struct ath_hw *ah;
S
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752
	int error = 0;
S
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753 754
	struct ath_regulatory *reg;

S
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755 756
	/* Bring up device */
	error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
S
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757
	if (error != 0)
S
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758
		goto error_init;
S
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759 760 761

	ah = sc->sc_ah;
	common = ath9k_hw_common(ah);
S
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762
	ath9k_set_hw_capab(sc, hw);
S
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763

S
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764
	/* Initialize regulatory */
S
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765 766 767
	error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
			      ath9k_reg_notifier);
	if (error)
S
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768
		goto error_regd;
S
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769 770 771

	reg = &common->regulatory;

S
Sujith 已提交
772
	/* Setup TX DMA */
S
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773 774
	error = ath_tx_init(sc, ATH_TXBUF);
	if (error != 0)
S
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775
		goto error_tx;
S
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776

S
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777
	/* Setup RX DMA */
S
Sujith 已提交
778 779
	error = ath_rx_init(sc, ATH_RXBUF);
	if (error != 0)
S
Sujith 已提交
780
		goto error_rx;
S
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781

782 783
	ath9k_init_txpower_limits(sc);

784 785 786 787 788 789 790
#ifdef CONFIG_MAC80211_LEDS
	/* must be initialized before ieee80211_register_hw */
	sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
		IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
		ARRAY_SIZE(ath9k_tpt_blink));
#endif

S
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791
	/* Register with mac80211 */
S
Sujith 已提交
792
	error = ieee80211_register_hw(hw);
S
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793 794
	if (error)
		goto error_register;
S
Sujith 已提交
795

796 797
	error = ath9k_init_debug(ah);
	if (error) {
798
		ath_err(common, "Unable to create debugfs files\n");
799 800 801
		goto error_world;
	}

S
Sujith 已提交
802
	/* Handle world regulatory */
S
Sujith 已提交
803 804 805
	if (!ath_is_world_regd(reg)) {
		error = regulatory_hint(hw->wiphy, reg->alpha2);
		if (error)
S
Sujith 已提交
806
			goto error_world;
S
Sujith 已提交
807 808
	}

809
	INIT_WORK(&sc->hw_check_work, ath_hw_check);
810
	INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
811
	INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
812
	sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
S
Sujith 已提交
813

S
Sujith 已提交
814
	ath_init_leds(sc);
S
Sujith 已提交
815 816 817 818
	ath_start_rfkill_poll(sc);

	return 0;

S
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819 820 821 822 823 824 825 826 827 828 829
error_world:
	ieee80211_unregister_hw(hw);
error_register:
	ath_rx_cleanup(sc);
error_rx:
	ath_tx_cleanup(sc);
error_tx:
	/* Nothing */
error_regd:
	ath9k_deinit_softc(sc);
error_init:
S
Sujith 已提交
830 831 832 833 834 835 836
	return error;
}

/*****************************/
/*     De-Initialization     */
/*****************************/

S
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837
static void ath9k_deinit_softc(struct ath_softc *sc)
S
Sujith 已提交
838
{
S
Sujith 已提交
839
	int i = 0;
S
Sujith 已提交
840

841 842 843 844 845 846
	if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
		kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);

	if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
		kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);

S
Sujith 已提交
847 848 849
        if ((sc->btcoex.no_stomp_timer) &&
	    sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
		ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
S
Sujith 已提交
850

S
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851 852 853 854 855 856
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);

	ath9k_hw_deinit(sc->sc_ah);

S
Sujith 已提交
857 858
	kfree(sc->sc_ah);
	sc->sc_ah = NULL;
S
Sujith 已提交
859 860
}

S
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861
void ath9k_deinit_device(struct ath_softc *sc)
S
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862 863 864 865 866 867
{
	struct ieee80211_hw *hw = sc->hw;

	ath9k_ps_wakeup(sc);

	wiphy_rfkill_stop_polling(sc->hw->wiphy);
S
Sujith 已提交
868
	ath_deinit_leds(sc);
S
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869

870 871
	ath9k_ps_restore(sc);

S
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872 873 874
	ieee80211_unregister_hw(hw);
	ath_rx_cleanup(sc);
	ath_tx_cleanup(sc);
S
Sujith 已提交
875
	ath9k_deinit_softc(sc);
S
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876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912
}

void ath_descdma_cleanup(struct ath_softc *sc,
			 struct ath_descdma *dd,
			 struct list_head *head)
{
	dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
			  dd->dd_desc_paddr);

	INIT_LIST_HEAD(head);
	kfree(dd->dd_bufptr);
	memset(dd, 0, sizeof(*dd));
}

/************************/
/*     Module Hooks     */
/************************/

static int __init ath9k_init(void)
{
	int error;

	/* Register rate control algorithm */
	error = ath_rate_control_register();
	if (error != 0) {
		printk(KERN_ERR
			"ath9k: Unable to register rate control "
			"algorithm: %d\n",
			error);
		goto err_out;
	}

	error = ath_pci_init();
	if (error < 0) {
		printk(KERN_ERR
			"ath9k: No PCI devices found, driver not installed.\n");
		error = -ENODEV;
913
		goto err_rate_unregister;
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914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935
	}

	error = ath_ahb_init();
	if (error < 0) {
		error = -ENODEV;
		goto err_pci_exit;
	}

	return 0;

 err_pci_exit:
	ath_pci_exit();

 err_rate_unregister:
	ath_rate_control_unregister();
 err_out:
	return error;
}
module_init(ath9k_init);

static void __exit ath9k_exit(void)
{
936
	is_ath9k_unloaded = true;
S
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937 938 939 940 941 942
	ath_ahb_exit();
	ath_pci_exit();
	ath_rate_control_unregister();
	printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
}
module_exit(ath9k_exit);