trans.c 82.1 KB
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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
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 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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 * Copyright(c) 2016 Intel Deutschland GmbH
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
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 * in the file called COPYING.
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 *
 * Contact Information:
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 *  Intel Linux Wireless <linuxwifi@intel.com>
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 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
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 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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 * Copyright(c) 2016 Intel Deutschland GmbH
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 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
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#include <linux/pci.h>
#include <linux/pci-aspm.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/sched.h>
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#include <linux/bitops.h>
#include <linux/gfp.h>
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#include <linux/vmalloc.h>
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#include <linux/pm_runtime.h>
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#include "iwl-drv.h"
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#include "iwl-trans.h"
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#include "iwl-csr.h"
#include "iwl-prph.h"
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#include "iwl-scd.h"
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#include "iwl-agn-hw.h"
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#include "iwl-fw-error-dump.h"
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#include "internal.h"
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#include "iwl-fh.h"
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/* extended range in FW SRAM */
#define IWL_FW_MEM_EXTENDED_START	0x40000
#define IWL_FW_MEM_EXTENDED_END		0x57FFF

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static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (!trans_pcie->fw_mon_page)
		return;

	dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
		       trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
	__free_pages(trans_pcie->fw_mon_page,
		     get_order(trans_pcie->fw_mon_size));
	trans_pcie->fw_mon_page = NULL;
	trans_pcie->fw_mon_phys = 0;
	trans_pcie->fw_mon_size = 0;
}

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static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
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{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	struct page *page = NULL;
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	dma_addr_t phys;
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	u32 size = 0;
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	u8 power;

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	if (!max_power) {
		/* default max_power is maximum */
		max_power = 26;
	} else {
		max_power += 11;
	}

	if (WARN(max_power > 26,
		 "External buffer size for monitor is too big %d, check the FW TLV\n",
		 max_power))
		return;

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	if (trans_pcie->fw_mon_page) {
		dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
					   trans_pcie->fw_mon_size,
					   DMA_FROM_DEVICE);
		return;
	}

	phys = 0;
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	for (power = max_power; power >= 11; power--) {
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		int order;

		size = BIT(power);
		order = get_order(size);
		page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
				   order);
		if (!page)
			continue;

		phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
				    DMA_FROM_DEVICE);
		if (dma_mapping_error(trans->dev, phys)) {
			__free_pages(page, order);
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			page = NULL;
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			continue;
		}
		IWL_INFO(trans,
			 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
			 size, order);
		break;
	}

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	if (WARN_ON_ONCE(!page))
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		return;

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	if (power != max_power)
		IWL_ERR(trans,
			"Sorry - debug buffer is only %luK while you requested %luK\n",
			(unsigned long)BIT(power - 10),
			(unsigned long)BIT(max_power - 10));

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	trans_pcie->fw_mon_page = page;
	trans_pcie->fw_mon_phys = phys;
	trans_pcie->fw_mon_size = size;
}

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static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
{
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
		    ((reg & 0x0000ffff) | (2 << 28)));
	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
}

static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
{
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
		    ((reg & 0x0000ffff) | (3 << 28)));
}

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static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
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{
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	if (trans->cfg->apmg_not_supported)
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		return;

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	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
	else
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
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}

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/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041

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static void iwl_pcie_apm_config(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	u16 lctl;
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	u16 cap;
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	/*
	 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
	 * Check if BIOS (or OS) enabled L1-ASPM on this device.
	 * If so (likely), disable L0S, so device moves directly L0->L1;
	 *    costs negligible amount of power savings.
	 * If not (unlikely), enable L0S, so there is at least some
	 *    power savings, even without L1.
	 */
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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	if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
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		iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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	else
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		iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
	trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
	dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
		 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
		 trans->ltr_enabled ? "En" : "Dis");
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}

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/*
 * Start up NIC's basic functionality after it has been reset
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 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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 * NOTE:  This does not load uCode nor start the embedded processor
 */
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static int iwl_pcie_apm_init(struct iwl_trans *trans)
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{
	int ret = 0;
	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");

	/*
	 * Use "set_bit" below rather than "write", to preserve any hardware
	 * bits already set by default after reset.
	 */

	/* Disable L0S exit timer (platform NMI Work/Around) */
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	if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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	/*
	 * Disable L0s without affecting L1;
	 *  don't wait for ICH L0s (ICH bug W/A)
	 */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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	/* Set FH wait threshold to maximum (HW error during stress W/A) */
	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);

	/*
	 * Enable HAP INTA (interrupt from management bus) to
	 * wake device's PCI Express link L1a -> L0s
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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	iwl_pcie_apm_config(trans);
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	/* Configure analog phase-lock-loop before activating to D0A */
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	if (trans->cfg->base_params->pll_cfg_val)
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		iwl_set_bit(trans, CSR_ANA_PLL_CFG,
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			    trans->cfg->base_params->pll_cfg_val);
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	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is supported, e.g. iwl_write_prph()
	 * and accesses to uCode SRAM.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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	if (ret < 0) {
		IWL_DEBUG_INFO(trans, "Failed to init the card\n");
		goto out;
	}

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	if (trans->cfg->host_interrupt_operation_mode) {
		/*
		 * This is a bit of an abuse - This is needed for 7260 / 3160
		 * only check host_interrupt_operation_mode even if this is
		 * not related to host_interrupt_operation_mode.
		 *
		 * Enable the oscillator to count wake up time for L1 exit. This
		 * consumes slightly more power (100uA) - but allows to be sure
		 * that we wake up from L1 on time.
		 *
		 * This looks weird: read twice the same register, discard the
		 * value, set a bit, and yet again, read that same register
		 * just to discard the value. But that's the way the hardware
		 * seems to like it.
		 */
		iwl_read_prph(trans, OSC_CLK);
		iwl_read_prph(trans, OSC_CLK);
		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
		iwl_read_prph(trans, OSC_CLK);
		iwl_read_prph(trans, OSC_CLK);
	}

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	/*
	 * Enable DMA clock and wait for it to stabilize.
	 *
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	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
	 * bits do not disable clocks.  This preserves any hardware
	 * bits already set by default in "CLK_CTRL_REG" after reset.
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	 */
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	if (!trans->cfg->apmg_not_supported) {
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		iwl_write_prph(trans, APMG_CLK_EN_REG,
			       APMG_CLK_VAL_DMA_CLK_RQT);
		udelay(20);

		/* Disable L1-Active */
		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);

		/* Clear the interrupt in APMG if the NIC is in RFKILL */
		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
			       APMG_RTC_INT_STT_RFKILL);
	}
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	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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out:
	return ret;
}

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/*
 * Enable LP XTAL to avoid HW bug where device may consume much power if
 * FW is not loaded after device reset. LP XTAL is disabled by default
 * after device HW reset. Do it only if XTAL is fed by internal source.
 * Configure device's "persistence" mode to avoid resetting XTAL again when
 * SHRD_HW_RST occurs in S3.
 */
static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
{
	int ret;
	u32 apmg_gp1_reg;
	u32 apmg_xtal_cfg_reg;
	u32 dl_cfg_reg;

	/* Force XTAL ON */
	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
				 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);

	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is possible.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   25000);
	if (WARN_ON(ret < 0)) {
		IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
		/* Release XTAL ON request */
		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
					   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
		return;
	}

	/*
	 * Clear "disable persistence" to avoid LP XTAL resetting when
	 * SHRD_HW_RST is applied in S3.
	 */
	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);

	/*
	 * Force APMG XTAL to be active to prevent its disabling by HW
	 * caused by APMG idle state.
	 */
	apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
						    SHR_APMG_XTAL_CFG_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
				 apmg_xtal_cfg_reg |
				 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);

	/*
	 * Reset entire device again - do controller reset (results in
	 * SHRD_HW_RST). Turn MAC off before proceeding.
	 */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/* Enable LP XTAL by indirect access through CSR */
	apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
				 SHR_APMG_GP1_WF_XTAL_LP_EN |
				 SHR_APMG_GP1_CHICKEN_BIT_SELECT);

	/* Clear delay line clock power up */
	dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
				 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);

	/*
	 * Enable persistence mode to avoid LP XTAL resetting when
	 * SHRD_HW_RST is applied in S3.
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
		    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/* Activates XTAL resources monitor */
	__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
				 CSR_MONITOR_XTAL_RESOURCES);

	/* Release XTAL ON request */
	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
	udelay(10);

	/* Release APMG XTAL */
	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
				 apmg_xtal_cfg_reg &
				 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
}

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static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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{
	int ret = 0;

	/* stop device's busmaster DMA activity */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);

	ret = iwl_poll_bit(trans, CSR_RESET,
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			   CSR_RESET_REG_FLAG_MASTER_DISABLED,
			   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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	if (ret < 0)
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		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");

	IWL_DEBUG_INFO(trans, "stop master\n");

	return ret;
}

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static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
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{
	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");

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	if (op_mode_leave) {
		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
			iwl_pcie_apm_init(trans);

		/* inform ME that we are leaving */
		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
					  APMG_PCIDEV_STT_VAL_WAKE_ME);
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		else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
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			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
				    CSR_HW_IF_CONFIG_REG_PREPARE |
				    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
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			mdelay(1);
			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
		}
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		mdelay(5);
	}

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	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
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	/* Stop device's DMA activity */
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	iwl_pcie_apm_stop_master(trans);
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	if (trans->cfg->lp_xtal_workaround) {
		iwl_pcie_apm_lp_xtal_enable(trans);
		return;
	}

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	/* Reset the entire device */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
}

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static int iwl_pcie_nic_init(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	/* nic_init */
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	spin_lock(&trans_pcie->irq_lock);
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	iwl_pcie_apm_init(trans);
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	spin_unlock(&trans_pcie->irq_lock);
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	iwl_pcie_set_pwr(trans, false);
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	iwl_op_mode_nic_config(trans->op_mode);
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	/* Allocate the RX queue, or reset if it is already allocated */
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	iwl_pcie_rx_init(trans);
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	/* Allocate or reset and init all Tx and Command queues */
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	if (iwl_pcie_tx_init(trans))
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		return -ENOMEM;

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	if (trans->cfg->base_params->shadow_reg_enable) {
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		/* enable shadow regs in HW */
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		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
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		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
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	}

	return 0;
}

#define HW_READY_TIMEOUT (50)

/* Note: returns poll_bit return value, which is >= 0 if success */
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static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
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{
	int ret;

557
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
558
		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
559 560

	/* See if we got it */
561
	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
562 563 564
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   HW_READY_TIMEOUT);
565

566 567 568
	if (ret >= 0)
		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);

569
	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
570 571 572 573
	return ret;
}

/* Note: returns standard 0/-ERROR code */
574
static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
575 576
{
	int ret;
577
	int t = 0;
578
	int iter;
579

580
	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
581

582
	ret = iwl_pcie_set_hw_ready(trans);
583
	/* If the card is ready, exit 0 */
584 585 586
	if (ret >= 0)
		return 0;

587 588 589 590
	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
	msleep(1);

591 592 593 594 595 596 597
	for (iter = 0; iter < 10; iter++) {
		/* If HW is not ready, prepare the conditions to check again */
		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
			    CSR_HW_IF_CONFIG_REG_PREPARE);

		do {
			ret = iwl_pcie_set_hw_ready(trans);
598 599
			if (ret >= 0)
				return 0;
600

601 602 603 604 605
			usleep_range(200, 1000);
			t += 200;
		} while (t < 150000);
		msleep(25);
	}
606

607
	IWL_ERR(trans, "Couldn't prepare the card\n");
608 609 610 611

	return ret;
}

612 613 614
/*
 * ucode
 */
615
static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
J
Johannes Berg 已提交
616
				   dma_addr_t phy_addr, u32 byte_cnt)
617
{
618
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
619
	unsigned long flags;
620 621
	int ret;

622
	trans_pcie->ucode_write_complete = false;
623

624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650
	if (!iwl_trans_grab_nic_access(trans, &flags))
		return -EIO;

	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);

	iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
		    dst_addr);

	iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
		    phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);

	iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
		    (iwl_get_dma_hi_addr(phy_addr)
			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);

	iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
		    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);

	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
		    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);

	iwl_trans_release_nic_access(trans, &flags);
651

652 653
	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
				 trans_pcie->ucode_write_complete, 5 * HZ);
654
	if (!ret) {
J
Johannes Berg 已提交
655
		IWL_ERR(trans, "Failed to load firmware chunk!\n");
656 657 658 659 660 661
		return -ETIMEDOUT;
	}

	return 0;
}

662
static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
J
Johannes Berg 已提交
663
			    const struct fw_desc *section)
664
{
J
Johannes Berg 已提交
665 666
	u8 *v_addr;
	dma_addr_t p_addr;
667
	u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
668 669
	int ret = 0;

J
Johannes Berg 已提交
670 671 672
	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
		     section_num);

673 674 675 676 677 678 679 680 681 682
	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
				    GFP_KERNEL | __GFP_NOWARN);
	if (!v_addr) {
		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
		chunk_sz = PAGE_SIZE;
		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
					    &p_addr, GFP_KERNEL);
		if (!v_addr)
			return -ENOMEM;
	}
J
Johannes Berg 已提交
683

684
	for (offset = 0; offset < section->len; offset += chunk_sz) {
685 686
		u32 copy_size, dst_addr;
		bool extended_addr = false;
J
Johannes Berg 已提交
687

688
		copy_size = min_t(u32, chunk_sz, section->len - offset);
689 690 691 692 693 694 695 696 697
		dst_addr = section->offset + offset;

		if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
		    dst_addr <= IWL_FW_MEM_EXTENDED_END)
			extended_addr = true;

		if (extended_addr)
			iwl_set_bits_prph(trans, LMPM_CHICK,
					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
698

J
Johannes Berg 已提交
699
		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
700 701 702 703 704 705 706
		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
						   copy_size);

		if (extended_addr)
			iwl_clear_bits_prph(trans, LMPM_CHICK,
					    LMPM_CHICK_EXTENDED_ADDR_SPACE);

J
Johannes Berg 已提交
707 708 709 710 711
		if (ret) {
			IWL_ERR(trans,
				"Could not load the [%d] uCode section\n",
				section_num);
			break;
D
David Spinadel 已提交
712
		}
J
Johannes Berg 已提交
713 714
	}

715
	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
J
Johannes Berg 已提交
716 717 718
	return ret;
}

719 720 721 722 723 724 725 726 727
/*
 * Driver Takes the ownership on secure machine before FW load
 * and prevent race with the BT load.
 * W/A for ROM bug. (should be remove in the next Si step)
 */
static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
{
	u32 val, loop = 1000;

728 729 730 731 732
	/*
	 * Check the RSA semaphore is accessible.
	 * If the HW isn't locked and the rsa semaphore isn't accessible,
	 * we are in trouble.
	 */
733 734
	val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
	if (val & (BIT(1) | BIT(17))) {
735 736
		IWL_INFO(trans,
			 "can't access the RSA semaphore it is write protected\n");
737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759
		return 0;
	}

	/* take ownership on the AUX IF */
	iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
	iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);

	do {
		iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
		val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
		if (val == 0x1) {
			iwl_write_prph(trans, RSA_ENABLE, 0);
			return 0;
		}

		udelay(10);
		loop--;
	} while (loop > 0);

	IWL_ERR(trans, "Failed to take ownership on secure machine\n");
	return -EIO;
}

760 761 762 763
static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
					   const struct fw_img *image,
					   int cpu,
					   int *first_ucode_section)
764 765
{
	int shift_param;
766 767
	int i, ret = 0, sec_num = 0x1;
	u32 val, last_read_idx = 0;
768 769 770

	if (cpu == 1) {
		shift_param = 0;
771
		*first_ucode_section = 0;
772 773
	} else {
		shift_param = 16;
774
		(*first_ucode_section)++;
775 776
	}

777 778 779
	for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
		last_read_idx = i;

780 781 782 783 784 785
		/*
		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
		 * CPU1 to CPU2.
		 * PAGING_SEPARATOR_SECTION delimiter - separate between
		 * CPU2 non paged to CPU2 paging sec.
		 */
786
		if (!image->sec[i].data ||
787 788
		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
789 790 791
			IWL_DEBUG_FW(trans,
				     "Break since Data not valid or Empty section, sec = %d\n",
				     i);
792
			break;
793 794
		}

795 796 797
		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
		if (ret)
			return ret;
798 799 800 801 802 803

		/* Notify the ucode of the loaded section number and status */
		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
		val = val | (sec_num << shift_param);
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
		sec_num = (sec_num << 1) | 0x1;
804 805
	}

806 807
	*first_ucode_section = last_read_idx;

808 809 810 811 812
	if (cpu == 1)
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
	else
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);

813 814
	return 0;
}
815

816 817
static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
				      const struct fw_img *image,
818 819
				      int cpu,
				      int *first_ucode_section)
820 821 822
{
	int shift_param;
	int i, ret = 0;
823
	u32 last_read_idx = 0;
824 825 826

	if (cpu == 1) {
		shift_param = 0;
827
		*first_ucode_section = 0;
828 829
	} else {
		shift_param = 16;
830
		(*first_ucode_section)++;
831 832
	}

833 834 835
	for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
		last_read_idx = i;

836 837 838 839 840 841
		/*
		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
		 * CPU1 to CPU2.
		 * PAGING_SEPARATOR_SECTION delimiter - separate between
		 * CPU2 non paged to CPU2 paging sec.
		 */
842
		if (!image->sec[i].data ||
843 844
		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
845 846 847
			IWL_DEBUG_FW(trans,
				     "Break since Data not valid or Empty section, sec = %d\n",
				     i);
848
			break;
849 850
		}

851 852 853
		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
		if (ret)
			return ret;
854 855
	}

856 857 858 859 860 861 862 863
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		iwl_set_bits_prph(trans,
				  CSR_UCODE_LOAD_STATUS_ADDR,
				  (LMPM_CPU_UCODE_LOADING_COMPLETED |
				   LMPM_CPU_HDRS_LOADING_COMPLETED |
				   LMPM_CPU_UCODE_LOADING_STARTED) <<
					shift_param);

864 865
	*first_ucode_section = last_read_idx;

866 867 868
	return 0;
}

869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
static void iwl_pcie_apply_destination(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
	int i;

	if (dest->version)
		IWL_ERR(trans,
			"DBG DEST version is %d - expect issues\n",
			dest->version);

	IWL_INFO(trans, "Applying debug destination %s\n",
		 get_fw_dbg_mode_string(dest->monitor_mode));

	if (dest->monitor_mode == EXTERNAL_MODE)
884
		iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
	else
		IWL_WARN(trans, "PCI should have external buffer debug\n");

	for (i = 0; i < trans->dbg_dest_reg_num; i++) {
		u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
		u32 val = le32_to_cpu(dest->reg_ops[i].val);

		switch (dest->reg_ops[i].op) {
		case CSR_ASSIGN:
			iwl_write32(trans, addr, val);
			break;
		case CSR_SETBIT:
			iwl_set_bit(trans, addr, BIT(val));
			break;
		case CSR_CLEARBIT:
			iwl_clear_bit(trans, addr, BIT(val));
			break;
		case PRPH_ASSIGN:
			iwl_write_prph(trans, addr, val);
			break;
		case PRPH_SETBIT:
			iwl_set_bits_prph(trans, addr, BIT(val));
			break;
		case PRPH_CLEARBIT:
			iwl_clear_bits_prph(trans, addr, BIT(val));
			break;
911 912 913 914 915 916 917 918
		case PRPH_BLOCKBIT:
			if (iwl_read_prph(trans, addr) & BIT(val)) {
				IWL_ERR(trans,
					"BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
					val, addr);
				goto monitor;
			}
			break;
919 920 921 922 923 924 925
		default:
			IWL_ERR(trans, "FW debug - unknown OP %d\n",
				dest->reg_ops[i].op);
			break;
		}
	}

926
monitor:
927 928 929
	if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
			       trans_pcie->fw_mon_phys >> dest->base_shift);
930 931 932 933 934 935 936 937 938 939
		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
				       (trans_pcie->fw_mon_phys +
					trans_pcie->fw_mon_size - 256) >>
						dest->end_shift);
		else
			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
				       (trans_pcie->fw_mon_phys +
					trans_pcie->fw_mon_size) >>
						dest->end_shift);
940 941 942
	}
}

943
static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
944
				const struct fw_img *image)
945
{
946
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
947
	int ret = 0;
948
	int first_ucode_section;
949

950
	IWL_DEBUG_FW(trans, "working with %s CPU\n",
951 952
		     image->is_dual_cpus ? "Dual" : "Single");

953 954 955 956
	/* load to FW the binary non secured sections of CPU1 */
	ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
	if (ret)
		return ret;
957 958

	if (image->is_dual_cpus) {
959 960 961 962
		/* set CPU2 header address */
		iwl_write_prph(trans,
			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
963

964
		/* load to FW the binary sections of CPU2 */
965 966
		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
						 &first_ucode_section);
967 968
		if (ret)
			return ret;
969
	}
970

971 972 973
	/* supported for 7000 only for the moment */
	if (iwlwifi_mod_params.fw_monitor &&
	    trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
974
		iwl_pcie_alloc_fw_monitor(trans, 0);
975 976 977 978 979 980 981 982

		if (trans_pcie->fw_mon_size) {
			iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
				       trans_pcie->fw_mon_phys >> 4);
			iwl_write_prph(trans, MON_BUFF_END_ADDR,
				       (trans_pcie->fw_mon_phys +
					trans_pcie->fw_mon_size) >> 4);
		}
983 984
	} else if (trans->dbg_dest_tlv) {
		iwl_pcie_apply_destination(trans);
985 986
	}

987
	/* release CPU reset */
988
	iwl_write32(trans, CSR_RESET, 0);
989

990 991
	return 0;
}
992

993 994
static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
					  const struct fw_img *image)
995 996 997 998 999 1000 1001
{
	int ret = 0;
	int first_ucode_section;

	IWL_DEBUG_FW(trans, "working with %s CPU\n",
		     image->is_dual_cpus ? "Dual" : "Single");

1002 1003 1004
	if (trans->dbg_dest_tlv)
		iwl_pcie_apply_destination(trans);

1005 1006 1007 1008 1009
	/* TODO: remove in the next Si step */
	ret = iwl_pcie_rsa_race_bug_wa(trans);
	if (ret)
		return ret;

1010 1011 1012 1013 1014
	/* configure the ucode to be ready to get the secured image */
	/* release CPU reset */
	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);

	/* load to FW the binary Secured sections of CPU1 */
1015 1016
	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
					      &first_ucode_section);
1017 1018 1019 1020
	if (ret)
		return ret;

	/* load to FW the binary sections of CPU2 */
1021 1022
	return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
					       &first_ucode_section);
1023 1024
}

1025
static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1026
{
1027
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1028 1029
	bool hw_rfkill, was_hw_rfkill;

1030 1031 1032 1033 1034 1035 1036
	lockdep_assert_held(&trans_pcie->mutex);

	if (trans_pcie->is_down)
		return;

	trans_pcie->is_down = true;

1037
	was_hw_rfkill = iwl_is_rfkill_set(trans);
1038

1039
	/* tell the device to stop sending interrupts */
1040
	spin_lock(&trans_pcie->irq_lock);
1041
	iwl_disable_interrupts(trans);
1042
	spin_unlock(&trans_pcie->irq_lock);
1043

1044
	/* device going down, Stop using ICT table */
1045
	iwl_pcie_disable_ict(trans);
1046 1047 1048 1049 1050 1051 1052 1053

	/*
	 * If a HW restart happens during firmware loading,
	 * then the firmware loading might call this function
	 * and later it might be called again due to the
	 * restart. So don't process again if the device is
	 * already dead.
	 */
1054
	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1055 1056
		IWL_DEBUG_INFO(trans,
			       "DEVICE_ENABLED bit was set and is now cleared\n");
1057
		iwl_pcie_tx_stop(trans);
1058
		iwl_pcie_rx_stop(trans);
1059

1060
		/* Power-down device's busmaster DMA clocks */
1061
		if (!trans->cfg->apmg_not_supported) {
1062 1063 1064 1065
			iwl_write_prph(trans, APMG_CLK_DIS_REG,
				       APMG_CLK_VAL_DMA_CLK_RQT);
			udelay(5);
		}
1066 1067 1068
	}

	/* Make sure (redundant) we've released our request to stay awake */
1069
	iwl_clear_bit(trans, CSR_GP_CNTRL,
1070
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1071 1072

	/* Stop the device, and put it in low power state */
1073
	iwl_pcie_apm_stop(trans, false);
1074

1075 1076 1077 1078 1079 1080 1081 1082 1083 1084
	/* stop and reset the on-board processor */
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
	udelay(20);

	/*
	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
	 * This is a bug in certain verions of the hardware.
	 * Certain devices also keep sending HW RF kill interrupt all
	 * the time, unless the interrupt is ACKed even if the interrupt
	 * should be masked. Re-ACK all the interrupts here.
1085
	 */
1086
	spin_lock(&trans_pcie->irq_lock);
1087
	iwl_disable_interrupts(trans);
1088
	spin_unlock(&trans_pcie->irq_lock);
1089

D
Don Fry 已提交
1090
	/* clear all status bits */
1091 1092 1093 1094
	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
	clear_bit(STATUS_INT_ENABLED, &trans->status);
	clear_bit(STATUS_TPOWER_PMI, &trans->status);
	clear_bit(STATUS_RFKILL, &trans->status);
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106

	/*
	 * Even if we stop the HW, we still want the RF kill
	 * interrupt
	 */
	iwl_enable_rfkill_int(trans);

	/*
	 * Check again since the RF kill state may have changed while
	 * all the interrupts were disabled, in this case we couldn't
	 * receive the RF kill interrupt and update the state in the
	 * op_mode.
1107 1108 1109 1110 1111 1112
	 * Don't call the op_mode if the rkfill state hasn't changed.
	 * This allows the op_mode to call stop_device from the rfkill
	 * notification without endless recursion. Under very rare
	 * circumstances, we might have a small recursion if the rfkill
	 * state changed exactly now while we were called from stop_device.
	 * This is very unlikely but can happen and is supported.
1113 1114 1115
	 */
	hw_rfkill = iwl_is_rfkill_set(trans);
	if (hw_rfkill)
1116
		set_bit(STATUS_RFKILL, &trans->status);
1117
	else
1118
		clear_bit(STATUS_RFKILL, &trans->status);
1119
	if (hw_rfkill != was_hw_rfkill)
1120
		iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1121

1122
	/* re-take ownership to prevent other users from stealing the device */
1123
	iwl_pcie_prepare_card_hw(trans);
1124 1125
}

1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (trans_pcie->msix_enabled) {
		int i;

		for (i = 0; i < trans_pcie->allocated_vector; i++)
			synchronize_irq(trans_pcie->msix_entries[i].vector);
	} else {
		synchronize_irq(trans_pcie->pci_dev->irq);
	}
}

1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165
static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
				   const struct fw_img *fw, bool run_in_rfkill)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	bool hw_rfkill;
	int ret;

	/* This may fail if AMT took ownership of the device */
	if (iwl_pcie_prepare_card_hw(trans)) {
		IWL_WARN(trans, "Exit HW not ready\n");
		ret = -EIO;
		goto out;
	}

	iwl_enable_rfkill_int(trans);

	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);

	/*
	 * We enabled the RF-Kill interrupt and the handler may very
	 * well be running. Disable the interrupts to make sure no other
	 * interrupt can be fired.
	 */
	iwl_disable_interrupts(trans);

	/* Make sure it finished running */
1166
	iwl_pcie_synchronize_irqs(trans);
1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185

	mutex_lock(&trans_pcie->mutex);

	/* If platform's RF_KILL switch is NOT set to KILL */
	hw_rfkill = iwl_is_rfkill_set(trans);
	if (hw_rfkill)
		set_bit(STATUS_RFKILL, &trans->status);
	else
		clear_bit(STATUS_RFKILL, &trans->status);
	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
	if (hw_rfkill && !run_in_rfkill) {
		ret = -ERFKILL;
		goto out;
	}

	/* Someone called stop_device, don't try to start_fw */
	if (trans_pcie->is_down) {
		IWL_WARN(trans,
			 "Can't start_fw since the HW hasn't been started\n");
1186
		ret = -EIO;
1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245
		goto out;
	}

	/* make sure rfkill handshake bits are cleared */
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);

	/* clear (again), then enable host interrupts */
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);

	ret = iwl_pcie_nic_init(trans);
	if (ret) {
		IWL_ERR(trans, "Unable to init nic\n");
		goto out;
	}

	/*
	 * Now, we load the firmware and don't want to be interrupted, even
	 * by the RF-Kill interrupt (hence mask all the interrupt besides the
	 * FH_TX interrupt which is needed to load the firmware). If the
	 * RF-Kill switch is toggled, we will find out after having loaded
	 * the firmware and return the proper value to the caller.
	 */
	iwl_enable_fw_load_int(trans);

	/* really make sure rfkill handshake bits are cleared */
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);

	/* Load the given image to the HW */
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		ret = iwl_pcie_load_given_ucode_8000(trans, fw);
	else
		ret = iwl_pcie_load_given_ucode(trans, fw);
	iwl_enable_interrupts(trans);

	/* re-check RF-Kill state since we may have missed the interrupt */
	hw_rfkill = iwl_is_rfkill_set(trans);
	if (hw_rfkill)
		set_bit(STATUS_RFKILL, &trans->status);
	else
		clear_bit(STATUS_RFKILL, &trans->status);

	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
	if (hw_rfkill && !run_in_rfkill)
		ret = -ERFKILL;

out:
	mutex_unlock(&trans_pcie->mutex);
	return ret;
}

static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
{
	iwl_pcie_reset_ict(trans);
	iwl_pcie_tx_start(trans, scd_addr);
}

1246 1247 1248 1249 1250 1251 1252 1253 1254
static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	mutex_lock(&trans_pcie->mutex);
	_iwl_trans_pcie_stop_device(trans, low_power);
	mutex_unlock(&trans_pcie->mutex);
}

1255 1256
void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
{
1257 1258 1259 1260 1261
	struct iwl_trans_pcie __maybe_unused *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	lockdep_assert_held(&trans_pcie->mutex);

1262
	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1263
		_iwl_trans_pcie_stop_device(trans, true);
1264 1265
}

1266 1267
static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
				      bool reset)
1268
{
1269
	if (!reset) {
1270 1271 1272 1273 1274
		/* Enable persistence mode to avoid reset */
		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
			    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
	}

1275
	iwl_disable_interrupts(trans);
1276 1277 1278 1279 1280 1281 1282 1283

	/*
	 * in testing mode, the host stays awake and the
	 * hardware won't be reset (not even partially)
	 */
	if (test)
		return;

1284 1285
	iwl_pcie_disable_ict(trans);

1286
	iwl_pcie_synchronize_irqs(trans);
1287

1288 1289
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1290 1291 1292
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

1293
	if (reset) {
1294 1295 1296 1297 1298 1299 1300
		/*
		 * reset TX queues -- some of their registers reset during S3
		 * so if we don't reset everything here the D3 image would try
		 * to execute some invalid memory upon resume
		 */
		iwl_trans_pcie_tx_reset(trans);
	}
1301 1302 1303 1304 1305

	iwl_pcie_set_pwr(trans, true);
}

static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1306
				    enum iwl_d3_status *status,
1307
				    bool test,  bool reset)
1308 1309 1310 1311
{
	u32 val;
	int ret;

1312 1313 1314 1315 1316 1317
	if (test) {
		iwl_enable_interrupts(trans);
		*status = IWL_D3_STATUS_ALIVE;
		return 0;
	}

1318 1319 1320 1321 1322 1323
	/*
	 * Also enables interrupts - none will happen as the device doesn't
	 * know we're waking it up, only when the opmode actually tells it
	 * after this call.
	 */
	iwl_pcie_reset_ict(trans);
1324
	iwl_enable_interrupts(trans);
1325 1326 1327 1328

	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

1329 1330 1331
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		udelay(2);

1332 1333 1334 1335
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   25000);
1336
	if (ret < 0) {
1337 1338 1339 1340
		IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
		return ret;
	}

1341 1342
	iwl_pcie_set_pwr(trans, false);

1343
	if (!reset) {
1344 1345 1346 1347
		iwl_clear_bit(trans, CSR_GP_CNTRL,
			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	} else {
		iwl_trans_pcie_tx_reset(trans);
1348

1349 1350 1351 1352 1353 1354
		ret = iwl_pcie_rx_init(trans);
		if (ret) {
			IWL_ERR(trans,
				"Failed to resume the device (RX reset)\n");
			return ret;
		}
1355 1356
	}

1357 1358 1359 1360 1361 1362
	val = iwl_read32(trans, CSR_RESET);
	if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
		*status = IWL_D3_STATUS_RESET;
	else
		*status = IWL_D3_STATUS_ALIVE;

1363
	return 0;
1364 1365
}

1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468
struct iwl_causes_list {
	u32 cause_num;
	u32 mask_reg;
	u8 addr;
};

static struct iwl_causes_list causes_list[] = {
	{MSIX_FH_INT_CAUSES_D2S_CH0_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0},
	{MSIX_FH_INT_CAUSES_D2S_CH1_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0x1},
	{MSIX_FH_INT_CAUSES_S2D,		CSR_MSIX_FH_INT_MASK_AD, 0x3},
	{MSIX_FH_INT_CAUSES_FH_ERR,		CSR_MSIX_FH_INT_MASK_AD, 0x5},
	{MSIX_HW_INT_CAUSES_REG_ALIVE,		CSR_MSIX_HW_INT_MASK_AD, 0x10},
	{MSIX_HW_INT_CAUSES_REG_WAKEUP,		CSR_MSIX_HW_INT_MASK_AD, 0x11},
	{MSIX_HW_INT_CAUSES_REG_CT_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x16},
	{MSIX_HW_INT_CAUSES_REG_RF_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x17},
	{MSIX_HW_INT_CAUSES_REG_PERIODIC,	CSR_MSIX_HW_INT_MASK_AD, 0x18},
	{MSIX_HW_INT_CAUSES_REG_SW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x29},
	{MSIX_HW_INT_CAUSES_REG_SCD,		CSR_MSIX_HW_INT_MASK_AD, 0x2A},
	{MSIX_HW_INT_CAUSES_REG_FH_TX,		CSR_MSIX_HW_INT_MASK_AD, 0x2B},
	{MSIX_HW_INT_CAUSES_REG_HW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x2D},
	{MSIX_HW_INT_CAUSES_REG_HAP,		CSR_MSIX_HW_INT_MASK_AD, 0x2E},
};

static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
{
	u32 val, max_rx_vector, i;
	struct iwl_trans *trans = trans_pcie->trans;

	max_rx_vector = trans_pcie->allocated_vector - 1;

	if (!trans_pcie->msix_enabled)
		return;

	iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);

	/*
	 * Each cause from the list above and the RX causes is represented as
	 * a byte in the IVAR table. We access the first (N - 1) bytes and map
	 * them to the (N - 1) vectors so these vectors will be used as rx
	 * vectors. Then access all non rx causes and map them to the
	 * default queue (N'th queue).
	 */
	for (i = 0; i < max_rx_vector; i++) {
		iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i));
		iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD,
			      BIT(MSIX_FH_INT_CAUSES_Q(i)));
	}

	for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
		val = trans_pcie->default_irq_num |
			MSIX_NON_AUTO_CLEAR_CAUSE;
		iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
		iwl_clear_bit(trans, causes_list[i].mask_reg,
			      causes_list[i].cause_num);
	}
	trans_pcie->fh_init_mask =
		~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
	trans_pcie->fh_mask = trans_pcie->fh_init_mask;
	trans_pcie->hw_init_mask =
		~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
	trans_pcie->hw_mask = trans_pcie->hw_init_mask;
}

static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
					struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	u16 pci_cmd;
	int max_vector;
	int ret, i;

	if (trans->cfg->mq_rx_supported) {
		max_vector = min_t(u32, (num_possible_cpus() + 1),
				   IWL_MAX_RX_HW_QUEUES);
		for (i = 0; i < max_vector; i++)
			trans_pcie->msix_entries[i].entry = i;

		ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
					    MSIX_MIN_INTERRUPT_VECTORS,
					    max_vector);
		if (ret > 1) {
			IWL_DEBUG_INFO(trans,
				       "Enable MSI-X allocate %d interrupt vector\n",
				       ret);
			trans_pcie->allocated_vector = ret;
			trans_pcie->default_irq_num =
				trans_pcie->allocated_vector - 1;
			trans_pcie->trans->num_rx_queues =
				trans_pcie->allocated_vector - 1;
			trans_pcie->msix_enabled = true;

			return;
		}
		IWL_DEBUG_INFO(trans,
			       "ret = %d %s move to msi mode\n", ret,
			       (ret == 1) ?
			       "can't allocate more than 1 interrupt vector" :
			       "failed to enable msi-x mode");
		pci_disable_msix(pdev);
	}

	ret = pci_enable_msi(pdev);
	if (ret) {
1469
		dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512
		/* enable rfkill interrupt: hw bug w/a */
		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
		}
	}
}

static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
				      struct iwl_trans_pcie *trans_pcie)
{
	int i, last_vector;

	last_vector = trans_pcie->trans->num_rx_queues;

	for (i = 0; i < trans_pcie->allocated_vector; i++) {
		int ret;

		ret = request_threaded_irq(trans_pcie->msix_entries[i].vector,
					   iwl_pcie_msix_isr,
					   (i == last_vector) ?
					   iwl_pcie_irq_msix_handler :
					   iwl_pcie_irq_rx_msix_handler,
					   IRQF_SHARED,
					   DRV_NAME,
					   &trans_pcie->msix_entries[i]);
		if (ret) {
			int j;

			IWL_ERR(trans_pcie->trans,
				"Error allocating IRQ %d\n", i);
			for (j = 0; j < i; j++)
				free_irq(trans_pcie->msix_entries[i].vector,
					 &trans_pcie->msix_entries[i]);
			pci_disable_msix(pdev);
			return ret;
		}
	}

	return 0;
}

1513
static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1514
{
1515
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1516
	bool hw_rfkill;
J
Johannes Berg 已提交
1517
	int err;
1518

1519 1520
	lockdep_assert_held(&trans_pcie->mutex);

1521
	err = iwl_pcie_prepare_card_hw(trans);
1522
	if (err) {
1523
		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
J
Johannes Berg 已提交
1524
		return err;
1525
	}
1526

1527
	/* Reset the entire device */
1528
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1529 1530 1531

	usleep_range(10, 15);

1532
	iwl_pcie_apm_init(trans);
1533

1534
	iwl_pcie_init_msix(trans_pcie);
1535 1536 1537
	/* From now on, the op_mode will be kept updated about RF kill state */
	iwl_enable_rfkill_int(trans);

1538 1539 1540
	/* Set is_down to false here so that...*/
	trans_pcie->is_down = false;

1541
	hw_rfkill = iwl_is_rfkill_set(trans);
1542
	if (hw_rfkill)
1543
		set_bit(STATUS_RFKILL, &trans->status);
1544
	else
1545
		clear_bit(STATUS_RFKILL, &trans->status);
1546
	/* ... rfkill can call stop_device and set it false if needed */
1547
	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1548

1549 1550 1551 1552
	/* Make sure we sync here, because we'll need full access later */
	if (low_power)
		pm_runtime_resume(trans->dev);

J
Johannes Berg 已提交
1553
	return 0;
1554 1555
}

1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int ret;

	mutex_lock(&trans_pcie->mutex);
	ret = _iwl_trans_pcie_start_hw(trans, low_power);
	mutex_unlock(&trans_pcie->mutex);

	return ret;
}

1568
static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1569
{
1570
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1571

1572 1573
	mutex_lock(&trans_pcie->mutex);

1574
	/* disable interrupts - don't enable HW RF kill interrupt */
1575
	spin_lock(&trans_pcie->irq_lock);
1576
	iwl_disable_interrupts(trans);
1577
	spin_unlock(&trans_pcie->irq_lock);
1578

1579
	iwl_pcie_apm_stop(trans, true);
1580

1581
	spin_lock(&trans_pcie->irq_lock);
1582
	iwl_disable_interrupts(trans);
1583
	spin_unlock(&trans_pcie->irq_lock);
1584

E
Emmanuel Grumbach 已提交
1585
	iwl_pcie_disable_ict(trans);
1586

1587
	mutex_unlock(&trans_pcie->mutex);
1588

1589
	iwl_pcie_synchronize_irqs(trans);
1590 1591
}

1592 1593
static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
{
1594
	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1595 1596 1597 1598
}

static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
{
1599
	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1600 1601 1602 1603
}

static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
{
1604
	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1605 1606
}

1607 1608
static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
{
A
Amnon Paz 已提交
1609 1610
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
			       ((reg & 0x000FFFFF) | (3 << 24)));
1611 1612 1613 1614 1615 1616 1617
	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
}

static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
				      u32 val)
{
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
A
Amnon Paz 已提交
1618
			       ((addr & 0x000FFFFF) | (3 << 24)));
1619 1620 1621
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
}

1622
static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1623
				     const struct iwl_trans_config *trans_cfg)
1624 1625 1626 1627
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1628
	trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1629
	trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1630 1631 1632 1633 1634 1635 1636
	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
		trans_pcie->n_no_reclaim_cmds = 0;
	else
		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
	if (trans_pcie->n_no_reclaim_cmds)
		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1637

1638 1639 1640
	trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
	trans_pcie->rx_page_order =
		iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1641

1642
	trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1643
	trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1644
	trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1645
	trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1646

1647 1648 1649
	trans->command_groups = trans_cfg->command_groups;
	trans->command_groups_size = trans_cfg->command_groups_size;

1650 1651 1652 1653 1654
	/* Initialize NAPI here - it should be before registering to mac80211
	 * in the opmode but after the HW struct is allocated.
	 * As this function may be called again in some corner cases don't
	 * do anything if NAPI was already initialized.
	 */
1655
	if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1656
		init_dummy_netdev(&trans_pcie->napi_dev);
1657 1658
}

1659
void iwl_trans_pcie_free(struct iwl_trans *trans)
1660
{
1661
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1662
	int i;
1663

1664
	iwl_pcie_synchronize_irqs(trans);
1665

1666
	iwl_pcie_tx_free(trans);
1667
	iwl_pcie_rx_free(trans);
1668

1669 1670 1671 1672 1673 1674 1675 1676 1677
	if (trans_pcie->msix_enabled) {
		for (i = 0; i < trans_pcie->allocated_vector; i++)
			free_irq(trans_pcie->msix_entries[i].vector,
				 &trans_pcie->msix_entries[i]);

		pci_disable_msix(trans_pcie->pci_dev);
		trans_pcie->msix_enabled = false;
	} else {
		free_irq(trans_pcie->pci_dev->irq, trans);
1678

1679 1680 1681 1682
		iwl_pcie_free_ict(trans);

		pci_disable_msi(trans_pcie->pci_dev);
	}
1683
	iounmap(trans_pcie->hw_base);
1684 1685 1686
	pci_release_regions(trans_pcie->pci_dev);
	pci_disable_device(trans_pcie->pci_dev);

1687 1688
	iwl_pcie_free_fw_monitor(trans);

1689 1690 1691 1692 1693 1694 1695 1696 1697
	for_each_possible_cpu(i) {
		struct iwl_tso_hdr_page *p =
			per_cpu_ptr(trans_pcie->tso_hdr_page, i);

		if (p->page)
			__free_page(p->page);
	}

	free_percpu(trans_pcie->tso_hdr_page);
1698
	mutex_destroy(&trans_pcie->mutex);
1699
	iwl_trans_free(trans);
1700 1701
}

D
Don Fry 已提交
1702 1703 1704
static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
{
	if (state)
1705
		set_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
1706
	else
1707
		clear_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
1708 1709
}

1710 1711
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
					   unsigned long *flags)
1712 1713
{
	int ret;
1714 1715 1716
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1717

1718
	if (trans_pcie->cmd_hold_nic_awake)
1719 1720
		goto out;

1721
	/* this bit wakes up the NIC */
1722 1723
	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
				 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1724 1725
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		udelay(2);
1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751

	/*
	 * These bits say the device is running, and should keep running for
	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	 * but they do not indicate that embedded SRAM is restored yet;
	 * 3945 and 4965 have volatile SRAM, and must save/restore contents
	 * to/from host DRAM when sleeping/waking for power-saving.
	 * Each direction takes approximately 1/4 millisecond; with this
	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	 * series of register accesses are expected (e.g. reading Event Log),
	 * to keep device from sleeping.
	 *
	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	 * SRAM is okay/restored.  We don't check that here because this call
	 * is just for hardware register access; but GP1 MAC_SLEEP check is a
	 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	 *
	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
	 * and do not save/restore SRAM when power cycling.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
			   (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
			    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	if (unlikely(ret < 0)) {
		iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1752 1753 1754 1755 1756
		WARN_ONCE(1,
			  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
			  iwl_read32(trans, CSR_GP_CNTRL));
		spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
		return false;
1757 1758
	}

1759
out:
1760 1761 1762 1763
	/*
	 * Fool sparse by faking we release the lock - sparse will
	 * track nic_access anyway.
	 */
1764
	__release(&trans_pcie->reg_lock);
1765 1766 1767
	return true;
}

1768 1769
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
					      unsigned long *flags)
1770
{
1771
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1772

1773
	lockdep_assert_held(&trans_pcie->reg_lock);
1774 1775 1776 1777 1778

	/*
	 * Fool sparse by faking we acquiring the lock - sparse will
	 * track nic_access anyway.
	 */
1779
	__acquire(&trans_pcie->reg_lock);
1780

1781
	if (trans_pcie->cmd_hold_nic_awake)
1782 1783
		goto out;

1784 1785
	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1786 1787 1788 1789 1790 1791 1792
	/*
	 * Above we read the CSR_GP_CNTRL register, which will flush
	 * any previous writes, but we need the write that clears the
	 * MAC_ACCESS_REQ bit to be performed before any other writes
	 * scheduled on different CPUs (after we drop reg_lock).
	 */
	mmiowb();
1793
out:
1794
	spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1795 1796
}

1797 1798 1799 1800 1801 1802 1803
static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
				   void *buf, int dwords)
{
	unsigned long flags;
	int offs, ret = 0;
	u32 *vals = buf;

1804
	if (iwl_trans_grab_nic_access(trans, &flags)) {
1805 1806 1807
		iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
		for (offs = 0; offs < dwords; offs++)
			vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1808
		iwl_trans_release_nic_access(trans, &flags);
1809 1810 1811 1812 1813 1814 1815
	} else {
		ret = -EBUSY;
	}
	return ret;
}

static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1816
				    const void *buf, int dwords)
1817 1818 1819
{
	unsigned long flags;
	int offs, ret = 0;
1820
	const u32 *vals = buf;
1821

1822
	if (iwl_trans_grab_nic_access(trans, &flags)) {
1823 1824
		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
		for (offs = 0; offs < dwords; offs++)
E
Emmanuel Grumbach 已提交
1825 1826
			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
				    vals ? vals[offs] : 0);
1827
		iwl_trans_release_nic_access(trans, &flags);
1828 1829 1830 1831 1832
	} else {
		ret = -EBUSY;
	}
	return ret;
}
1833

1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887
static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
					    unsigned long txqs,
					    bool freeze)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int queue;

	for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
		struct iwl_txq *txq = &trans_pcie->txq[queue];
		unsigned long now;

		spin_lock_bh(&txq->lock);

		now = jiffies;

		if (txq->frozen == freeze)
			goto next_queue;

		IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
				    freeze ? "Freezing" : "Waking", queue);

		txq->frozen = freeze;

		if (txq->q.read_ptr == txq->q.write_ptr)
			goto next_queue;

		if (freeze) {
			if (unlikely(time_after(now,
						txq->stuck_timer.expires))) {
				/*
				 * The timer should have fired, maybe it is
				 * spinning right now on the lock.
				 */
				goto next_queue;
			}
			/* remember how long until the timer fires */
			txq->frozen_expiry_remainder =
				txq->stuck_timer.expires - now;
			del_timer(&txq->stuck_timer);
			goto next_queue;
		}

		/*
		 * Wake a non-empty queue -> arm timer with the
		 * remainder before it froze
		 */
		mod_timer(&txq->stuck_timer,
			  now + txq->frozen_expiry_remainder);

next_queue:
		spin_unlock_bh(&txq->lock);
	}
}

1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914
static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int i;

	for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
		struct iwl_txq *txq = &trans_pcie->txq[i];

		if (i == trans_pcie->cmd_queue)
			continue;

		spin_lock_bh(&txq->lock);

		if (!block && !(WARN_ON_ONCE(!txq->block))) {
			txq->block--;
			if (!txq->block) {
				iwl_write32(trans, HBUS_TARG_WRPTR,
					    txq->q.write_ptr | (i << 8));
			}
		} else if (block) {
			txq->block++;
		}

		spin_unlock_bh(&txq->lock);
	}
}

1915 1916
#define IWL_FLUSH_WAIT_MS	2000

1917
static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1918
{
1919
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1920
	struct iwl_txq *txq;
1921 1922 1923
	struct iwl_queue *q;
	int cnt;
	unsigned long now = jiffies;
1924 1925
	u32 scd_sram_addr;
	u8 buf[16];
1926 1927 1928
	int ret = 0;

	/* waiting for all the tx frames complete might take a while */
1929
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1930 1931
		u8 wr_ptr;

W
Wey-Yi Guy 已提交
1932
		if (cnt == trans_pcie->cmd_queue)
1933
			continue;
1934 1935 1936 1937
		if (!test_bit(cnt, trans_pcie->queue_used))
			continue;
		if (!(BIT(cnt) & txq_bm))
			continue;
1938 1939

		IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1940
		txq = &trans_pcie->txq[cnt];
1941
		q = &txq->q;
1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952
		wr_ptr = ACCESS_ONCE(q->write_ptr);

		while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
		       !time_after(jiffies,
				   now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
			u8 write_ptr = ACCESS_ONCE(q->write_ptr);

			if (WARN_ONCE(wr_ptr != write_ptr,
				      "WR pointer moved while flushing %d -> %d\n",
				      wr_ptr, write_ptr))
				return -ETIMEDOUT;
1953
			msleep(1);
1954
		}
1955 1956

		if (q->read_ptr != q->write_ptr) {
1957 1958
			IWL_ERR(trans,
				"fail to flush all tx fifo queues Q %d\n", cnt);
1959 1960 1961
			ret = -ETIMEDOUT;
			break;
		}
1962
		IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1963
	}
1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996

	if (!ret)
		return 0;

	IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
		txq->q.read_ptr, txq->q.write_ptr);

	scd_sram_addr = trans_pcie->scd_base_addr +
			SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
	iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));

	iwl_print_hex_error(trans, buf, sizeof(buf));

	for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
		IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
			iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));

	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
		u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
		u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
		bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
		u32 tbl_dw =
			iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
					     SCD_TRANS_TBL_OFFSET_QUEUE(cnt));

		if (cnt & 0x1)
			tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
		else
			tbl_dw = tbl_dw & 0x0000FFFF;

		IWL_ERR(trans,
			"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
			cnt, active ? "" : "in", fifo, tbl_dw,
1997 1998
			iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
				(TFD_QUEUE_SIZE_MAX - 1),
1999 2000 2001
			iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
	}

2002 2003 2004
	return ret;
}

2005 2006 2007
static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
					 u32 mask, u32 value)
{
2008
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2009 2010
	unsigned long flags;

2011
	spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2012
	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2013
	spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2014 2015
}

2016 2017 2018 2019 2020 2021 2022
void iwl_trans_pcie_ref(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (iwlwifi_mod_params.d0i3_disable)
		return;

2023
	pm_runtime_get(&trans_pcie->pci_dev->dev);
2024 2025 2026 2027 2028

#ifdef CONFIG_PM
	IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
		      atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
#endif /* CONFIG_PM */
2029 2030 2031 2032 2033 2034 2035 2036 2037
}

void iwl_trans_pcie_unref(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (iwlwifi_mod_params.d0i3_disable)
		return;

2038 2039 2040
	pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
	pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);

2041 2042 2043 2044
#ifdef CONFIG_PM
	IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
		      atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
#endif /* CONFIG_PM */
2045 2046
}

2047 2048
static const char *get_csr_string(int cmd)
{
J
Johannes Berg 已提交
2049
#define IWL_CMD(x) case x: return #x
2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072
	switch (cmd) {
	IWL_CMD(CSR_HW_IF_CONFIG_REG);
	IWL_CMD(CSR_INT_COALESCING);
	IWL_CMD(CSR_INT);
	IWL_CMD(CSR_INT_MASK);
	IWL_CMD(CSR_FH_INT_STATUS);
	IWL_CMD(CSR_GPIO_IN);
	IWL_CMD(CSR_RESET);
	IWL_CMD(CSR_GP_CNTRL);
	IWL_CMD(CSR_HW_REV);
	IWL_CMD(CSR_EEPROM_REG);
	IWL_CMD(CSR_EEPROM_GP);
	IWL_CMD(CSR_OTP_GP_REG);
	IWL_CMD(CSR_GIO_REG);
	IWL_CMD(CSR_GP_UCODE_REG);
	IWL_CMD(CSR_GP_DRIVER_REG);
	IWL_CMD(CSR_UCODE_DRV_GP1);
	IWL_CMD(CSR_UCODE_DRV_GP2);
	IWL_CMD(CSR_LED_REG);
	IWL_CMD(CSR_DRAM_INT_TBL_REG);
	IWL_CMD(CSR_GIO_CHICKEN_BITS);
	IWL_CMD(CSR_ANA_PLL_CFG);
	IWL_CMD(CSR_HW_REV_WA_REG);
2073
	IWL_CMD(CSR_MONITOR_STATUS_REG);
2074 2075 2076 2077
	IWL_CMD(CSR_DBG_HPET_MEM_REG);
	default:
		return "UNKNOWN";
	}
J
Johannes Berg 已提交
2078
#undef IWL_CMD
2079 2080
}

2081
void iwl_pcie_dump_csr(struct iwl_trans *trans)
2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
{
	int i;
	static const u32 csr_tbl[] = {
		CSR_HW_IF_CONFIG_REG,
		CSR_INT_COALESCING,
		CSR_INT,
		CSR_INT_MASK,
		CSR_FH_INT_STATUS,
		CSR_GPIO_IN,
		CSR_RESET,
		CSR_GP_CNTRL,
		CSR_HW_REV,
		CSR_EEPROM_REG,
		CSR_EEPROM_GP,
		CSR_OTP_GP_REG,
		CSR_GIO_REG,
		CSR_GP_UCODE_REG,
		CSR_GP_DRIVER_REG,
		CSR_UCODE_DRV_GP1,
		CSR_UCODE_DRV_GP2,
		CSR_LED_REG,
		CSR_DRAM_INT_TBL_REG,
		CSR_GIO_CHICKEN_BITS,
		CSR_ANA_PLL_CFG,
2106
		CSR_MONITOR_STATUS_REG,
2107 2108 2109 2110 2111 2112 2113 2114 2115
		CSR_HW_REV_WA_REG,
		CSR_DBG_HPET_MEM_REG
	};
	IWL_ERR(trans, "CSR values:\n");
	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
		"CSR_INT_PERIODIC_REG)\n");
	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
		IWL_ERR(trans, "  %25s: 0X%08x\n",
			get_csr_string(csr_tbl[i]),
2116
			iwl_read32(trans, csr_tbl[i]));
2117 2118 2119
	}
}

2120 2121 2122
#ifdef CONFIG_IWLWIFI_DEBUGFS
/* create and remove of files */
#define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
2123
	if (!debugfs_create_file(#name, mode, parent, trans,		\
2124
				 &iwl_dbgfs_##name##_ops))		\
2125
		goto err;						\
2126 2127 2128 2129 2130 2131
} while (0)

/* file operation */
#define DEBUGFS_READ_FILE_OPS(name)					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.read = iwl_dbgfs_##name##_read,				\
2132
	.open = simple_open,						\
2133 2134 2135
	.llseek = generic_file_llseek,					\
};

2136 2137 2138
#define DEBUGFS_WRITE_FILE_OPS(name)                                    \
static const struct file_operations iwl_dbgfs_##name##_ops = {          \
	.write = iwl_dbgfs_##name##_write,                              \
2139
	.open = simple_open,						\
2140 2141 2142
	.llseek = generic_file_llseek,					\
};

2143 2144 2145 2146
#define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.write = iwl_dbgfs_##name##_write,				\
	.read = iwl_dbgfs_##name##_read,				\
2147
	.open = simple_open,						\
2148 2149 2150 2151
	.llseek = generic_file_llseek,					\
};

static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2152 2153
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
2154
{
2155
	struct iwl_trans *trans = file->private_data;
2156
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2157
	struct iwl_txq *txq;
2158 2159 2160 2161 2162
	struct iwl_queue *q;
	char *buf;
	int pos = 0;
	int cnt;
	int ret;
2163 2164
	size_t bufsz;

2165
	bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2166

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Johannes Berg 已提交
2167
	if (!trans_pcie->txq)
2168
		return -EAGAIN;
J
Johannes Berg 已提交
2169

2170 2171 2172 2173
	buf = kzalloc(bufsz, GFP_KERNEL);
	if (!buf)
		return -ENOMEM;

2174
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2175
		txq = &trans_pcie->txq[cnt];
2176 2177
		q = &txq->q;
		pos += scnprintf(buf + pos, bufsz - pos,
2178
				"hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2179
				cnt, q->read_ptr, q->write_ptr,
2180
				!!test_bit(cnt, trans_pcie->queue_used),
2181
				 !!test_bit(cnt, trans_pcie->queue_stopped),
2182
				 txq->need_update, txq->frozen,
2183
				 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2184 2185 2186 2187 2188 2189 2190
	}
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2191 2192 2193
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
{
2194
	struct iwl_trans *trans = file->private_data;
2195
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231
	char *buf;
	int pos = 0, i, ret;
	size_t bufsz = sizeof(buf);

	bufsz = sizeof(char) * 121 * trans->num_rx_queues;

	if (!trans_pcie->rxq)
		return -EAGAIN;

	buf = kzalloc(bufsz, GFP_KERNEL);
	if (!buf)
		return -ENOMEM;

	for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
		struct iwl_rxq *rxq = &trans_pcie->rxq[i];

		pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
				 i);
		pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
				 rxq->read);
		pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
				 rxq->write);
		pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
				 rxq->write_actual);
		pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
				 rxq->need_update);
		pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
				 rxq->free_count);
		if (rxq->rb_stts) {
			pos += scnprintf(buf + pos, bufsz - pos,
					 "\tclosed_rb_num: %u\n",
					 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
					 0x0FFF);
		} else {
			pos += scnprintf(buf + pos, bufsz - pos,
					 "\tclosed_rb_num: Not Allocated\n");
2232
		}
2233
	}
2234 2235 2236 2237
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);

	return ret;
2238 2239
}

2240 2241
static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
					char __user *user_buf,
2242 2243
					size_t count, loff_t *ppos)
{
2244
	struct iwl_trans *trans = file->private_data;
2245
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2246 2247 2248 2249 2250 2251 2252 2253
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	int pos = 0;
	char *buf;
	int bufsz = 24 * 64; /* 24 items * 64 char per item */
	ssize_t ret;

	buf = kzalloc(bufsz, GFP_KERNEL);
J
Johannes Berg 已提交
2254
	if (!buf)
2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302
		return -ENOMEM;

	pos += scnprintf(buf + pos, bufsz - pos,
			"Interrupt Statistics Report:\n");

	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
		isr_stats->hw);
	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
		isr_stats->sw);
	if (isr_stats->sw || isr_stats->hw) {
		pos += scnprintf(buf + pos, bufsz - pos,
			"\tLast Restarting Code:  0x%X\n",
			isr_stats->err_code);
	}
#ifdef CONFIG_IWLWIFI_DEBUG
	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
		isr_stats->sch);
	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
		isr_stats->alive);
#endif
	pos += scnprintf(buf + pos, bufsz - pos,
		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);

	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
		isr_stats->ctkill);

	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
		isr_stats->wakeup);

	pos += scnprintf(buf + pos, bufsz - pos,
		"Rx command responses:\t\t %u\n", isr_stats->rx);

	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
		isr_stats->tx);

	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
		isr_stats->unhandled);

	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
					 const char __user *user_buf,
					 size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;
2303
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	char buf[8];
	int buf_size;
	u32 reset_flag;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%x", &reset_flag) != 1)
		return -EFAULT;
	if (reset_flag == 0)
		memset(isr_stats, 0, sizeof(*isr_stats));

	return count;
}

2322
static ssize_t iwl_dbgfs_csr_write(struct file *file,
2323 2324
				   const char __user *user_buf,
				   size_t count, loff_t *ppos)
2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337
{
	struct iwl_trans *trans = file->private_data;
	char buf[8];
	int buf_size;
	int csr;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%d", &csr) != 1)
		return -EFAULT;

2338
	iwl_pcie_dump_csr(trans);
2339 2340 2341 2342 2343

	return count;
}

static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2344 2345
				     char __user *user_buf,
				     size_t count, loff_t *ppos)
2346 2347
{
	struct iwl_trans *trans = file->private_data;
2348
	char *buf = NULL;
2349
	ssize_t ret;
2350

2351 2352 2353 2354 2355 2356 2357
	ret = iwl_dump_fh(trans, &buf);
	if (ret < 0)
		return ret;
	if (!buf)
		return -EINVAL;
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
	kfree(buf);
2358 2359 2360
	return ret;
}

2361
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2362
DEBUGFS_READ_FILE_OPS(fh_reg);
2363 2364
DEBUGFS_READ_FILE_OPS(rx_queue);
DEBUGFS_READ_FILE_OPS(tx_queue);
2365
DEBUGFS_WRITE_FILE_OPS(csr);
2366

2367 2368
/* Create the debugfs files and directories */
int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2369
{
2370 2371
	struct dentry *dir = trans->dbgfs_dir;

2372 2373
	DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
	DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2374
	DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2375 2376
	DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
	DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2377
	return 0;
2378 2379 2380 2381

err:
	IWL_ERR(trans, "failed to create the trans debugfs entry\n");
	return -ENOMEM;
2382
}
2383
#endif /*CONFIG_IWLWIFI_DEBUGFS */
2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395

static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
{
	u32 cmdlen = 0;
	int i;

	for (i = 0; i < IWL_NUM_OF_TBS; i++)
		cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);

	return cmdlen;
}

2396 2397 2398 2399 2400 2401
static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
				   struct iwl_fw_error_dump_data **data,
				   int allocated_rb_nums)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2402 2403
	/* Dump RBs is supported only for pre-9000 devices (1 queue) */
	struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437
	u32 i, r, j, rb_len = 0;

	spin_lock(&rxq->lock);

	r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;

	for (i = rxq->read, j = 0;
	     i != r && j < allocated_rb_nums;
	     i = (i + 1) & RX_QUEUE_MASK, j++) {
		struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
		struct iwl_fw_error_dump_rb *rb;

		dma_unmap_page(trans->dev, rxb->page_dma, max_len,
			       DMA_FROM_DEVICE);

		rb_len += sizeof(**data) + sizeof(*rb) + max_len;

		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
		(*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
		rb = (void *)(*data)->data;
		rb->index = cpu_to_le32(i);
		memcpy(rb->data, page_address(rxb->page), max_len);
		/* remap the page for the free benefit */
		rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
						     max_len,
						     DMA_FROM_DEVICE);

		*data = iwl_fw_error_next_data(*data);
	}

	spin_unlock(&rxq->lock);

	return rb_len;
}
2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458
#define IWL_CSR_TO_DUMP (0x250)

static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
				   struct iwl_fw_error_dump_data **data)
{
	u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
	__le32 *val;
	int i;

	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
	(*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
	val = (void *)(*data)->data;

	for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));

	*data = iwl_fw_error_next_data(*data);

	return csr_len;
}

2459 2460 2461 2462 2463 2464 2465 2466
static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
				       struct iwl_fw_error_dump_data **data)
{
	u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
	unsigned long flags;
	__le32 *val;
	int i;

2467
	if (!iwl_trans_grab_nic_access(trans, &flags))
2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483
		return 0;

	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
	(*data)->len = cpu_to_le32(fh_regs_len);
	val = (void *)(*data)->data;

	for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));

	iwl_trans_release_nic_access(trans, &flags);

	*data = iwl_fw_error_next_data(*data);

	return sizeof(**data) + fh_regs_len;
}

2484 2485 2486 2487 2488 2489 2490 2491 2492 2493
static u32
iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
				 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
				 u32 monitor_len)
{
	u32 buf_size_in_dwords = (monitor_len >> 2);
	u32 *buffer = (u32 *)fw_mon_data->data;
	unsigned long flags;
	u32 i;

2494
	if (!iwl_trans_grab_nic_access(trans, &flags))
2495 2496
		return 0;

2497
	iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2498
	for (i = 0; i < buf_size_in_dwords; i++)
2499 2500 2501
		buffer[i] = iwl_read_prph_no_grab(trans,
				MON_DMARB_RD_DATA_ADDR);
	iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2502 2503 2504 2505 2506 2507

	iwl_trans_release_nic_access(trans, &flags);

	return monitor_len;
}

2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587
static u32
iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
			    struct iwl_fw_error_dump_data **data,
			    u32 monitor_len)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	u32 len = 0;

	if ((trans_pcie->fw_mon_page &&
	     trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
	    trans->dbg_dest_tlv) {
		struct iwl_fw_error_dump_fw_mon *fw_mon_data;
		u32 base, write_ptr, wrap_cnt;

		/* If there was a dest TLV - use the values from there */
		if (trans->dbg_dest_tlv) {
			write_ptr =
				le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
			wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
			base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
		} else {
			base = MON_BUFF_BASE_ADDR;
			write_ptr = MON_BUFF_WRPTR;
			wrap_cnt = MON_BUFF_CYCLE_CNT;
		}

		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
		fw_mon_data = (void *)(*data)->data;
		fw_mon_data->fw_mon_wr_ptr =
			cpu_to_le32(iwl_read_prph(trans, write_ptr));
		fw_mon_data->fw_mon_cycle_cnt =
			cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
		fw_mon_data->fw_mon_base_ptr =
			cpu_to_le32(iwl_read_prph(trans, base));

		len += sizeof(**data) + sizeof(*fw_mon_data);
		if (trans_pcie->fw_mon_page) {
			/*
			 * The firmware is now asserted, it won't write anything
			 * to the buffer. CPU can take ownership to fetch the
			 * data. The buffer will be handed back to the device
			 * before the firmware will be restarted.
			 */
			dma_sync_single_for_cpu(trans->dev,
						trans_pcie->fw_mon_phys,
						trans_pcie->fw_mon_size,
						DMA_FROM_DEVICE);
			memcpy(fw_mon_data->data,
			       page_address(trans_pcie->fw_mon_page),
			       trans_pcie->fw_mon_size);

			monitor_len = trans_pcie->fw_mon_size;
		} else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
			/*
			 * Update pointers to reflect actual values after
			 * shifting
			 */
			base = iwl_read_prph(trans, base) <<
			       trans->dbg_dest_tlv->base_shift;
			iwl_trans_read_mem(trans, base, fw_mon_data->data,
					   monitor_len / sizeof(u32));
		} else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
			monitor_len =
				iwl_trans_pci_dump_marbh_monitor(trans,
								 fw_mon_data,
								 monitor_len);
		} else {
			/* Didn't match anything - output no monitor data */
			monitor_len = 0;
		}

		len += monitor_len;
		(*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
	}

	return len;
}

static struct iwl_trans_dump_data
*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2588
			  const struct iwl_fw_dbg_trigger_tlv *trigger)
2589 2590 2591 2592 2593
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	struct iwl_fw_error_dump_data *data;
	struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
	struct iwl_fw_error_dump_txcmd *txcmd;
2594
	struct iwl_trans_dump_data *dump_data;
2595
	u32 len, num_rbs;
2596
	u32 monitor_len;
2597
	int i, ptr;
2598 2599
	bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
			!trans->cfg->mq_rx_supported;
2600

2601 2602 2603 2604 2605
	/* transport dump header */
	len = sizeof(*dump_data);

	/* host commands */
	len += sizeof(*data) +
2606 2607
		cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);

2608
	/* FW monitor */
2609
	if (trans_pcie->fw_mon_page) {
2610
		len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624
		       trans_pcie->fw_mon_size;
		monitor_len = trans_pcie->fw_mon_size;
	} else if (trans->dbg_dest_tlv) {
		u32 base, end;

		base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
		end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);

		base = iwl_read_prph(trans, base) <<
		       trans->dbg_dest_tlv->base_shift;
		end = iwl_read_prph(trans, end) <<
		      trans->dbg_dest_tlv->end_shift;

		/* Make "end" point to the actual end */
2625 2626
		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
		    trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2627 2628 2629 2630 2631 2632 2633
			end += (1 << trans->dbg_dest_tlv->end_shift);
		monitor_len = end - base;
		len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
		       monitor_len;
	} else {
		monitor_len = 0;
	}
2634

2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653
	if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
		dump_data = vzalloc(len);
		if (!dump_data)
			return NULL;

		data = (void *)dump_data->data;
		len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
		dump_data->len = len;

		return dump_data;
	}

	/* CSR registers */
	len += sizeof(*data) + IWL_CSR_TO_DUMP;

	/* FH registers */
	len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);

	if (dump_rbs) {
2654 2655
		/* Dump RBs is supported only for pre-9000 devices (1 queue) */
		struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2656
		/* RBs */
2657
		num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2658
				      & 0x0FFF;
2659
		num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2660 2661 2662 2663 2664
		len += num_rbs * (sizeof(*data) +
				  sizeof(struct iwl_fw_error_dump_rb) +
				  (PAGE_SIZE << trans_pcie->rx_page_order));
	}

2665 2666 2667
	dump_data = vzalloc(len);
	if (!dump_data)
		return NULL;
2668 2669

	len = 0;
2670
	data = (void *)dump_data->data;
2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694
	data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
	txcmd = (void *)data->data;
	spin_lock_bh(&cmdq->lock);
	ptr = cmdq->q.write_ptr;
	for (i = 0; i < cmdq->q.n_window; i++) {
		u8 idx = get_cmd_index(&cmdq->q, ptr);
		u32 caplen, cmdlen;

		cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
		caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);

		if (cmdlen) {
			len += sizeof(*txcmd) + caplen;
			txcmd->cmdlen = cpu_to_le32(cmdlen);
			txcmd->caplen = cpu_to_le32(caplen);
			memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
			txcmd = (void *)((u8 *)txcmd->data + caplen);
		}

		ptr = iwl_queue_dec_wrap(ptr);
	}
	spin_unlock_bh(&cmdq->lock);

	data->len = cpu_to_le32(len);
2695
	len += sizeof(*data);
2696 2697
	data = iwl_fw_error_next_data(data);

2698
	len += iwl_trans_pcie_dump_csr(trans, &data);
2699
	len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2700 2701
	if (dump_rbs)
		len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2702

2703
	len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2704

2705 2706 2707
	dump_data->len = len;

	return dump_data;
2708
}
2709

2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725
#ifdef CONFIG_PM_SLEEP
static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
{
	if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
		return iwl_pci_fw_enter_d0i3(trans);

	return 0;
}

static void iwl_trans_pcie_resume(struct iwl_trans *trans)
{
	if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
		iwl_pci_fw_exit_d0i3(trans);
}
#endif /* CONFIG_PM_SLEEP */

2726
static const struct iwl_trans_ops trans_ops_pcie = {
2727
	.start_hw = iwl_trans_pcie_start_hw,
2728
	.op_mode_leave = iwl_trans_pcie_op_mode_leave,
2729
	.fw_alive = iwl_trans_pcie_fw_alive,
2730
	.start_fw = iwl_trans_pcie_start_fw,
2731
	.stop_device = iwl_trans_pcie_stop_device,
2732

2733 2734
	.d3_suspend = iwl_trans_pcie_d3_suspend,
	.d3_resume = iwl_trans_pcie_d3_resume,
2735

2736 2737 2738 2739 2740
#ifdef CONFIG_PM_SLEEP
	.suspend = iwl_trans_pcie_suspend,
	.resume = iwl_trans_pcie_resume,
#endif /* CONFIG_PM_SLEEP */

2741
	.send_cmd = iwl_trans_pcie_send_hcmd,
2742

2743
	.tx = iwl_trans_pcie_tx,
2744
	.reclaim = iwl_trans_pcie_reclaim,
2745

2746
	.txq_disable = iwl_trans_pcie_txq_disable,
2747
	.txq_enable = iwl_trans_pcie_txq_enable,
2748

2749
	.wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2750
	.freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2751
	.block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2752

2753 2754 2755
	.write8 = iwl_trans_pcie_write8,
	.write32 = iwl_trans_pcie_write32,
	.read32 = iwl_trans_pcie_read32,
2756 2757
	.read_prph = iwl_trans_pcie_read_prph,
	.write_prph = iwl_trans_pcie_write_prph,
2758 2759
	.read_mem = iwl_trans_pcie_read_mem,
	.write_mem = iwl_trans_pcie_write_mem,
2760
	.configure = iwl_trans_pcie_configure,
D
Don Fry 已提交
2761
	.set_pmi = iwl_trans_pcie_set_pmi,
2762
	.grab_nic_access = iwl_trans_pcie_grab_nic_access,
2763 2764
	.release_nic_access = iwl_trans_pcie_release_nic_access,
	.set_bits_mask = iwl_trans_pcie_set_bits_mask,
2765

2766 2767 2768
	.ref = iwl_trans_pcie_ref,
	.unref = iwl_trans_pcie_unref,

2769
	.dump_data = iwl_trans_pcie_dump_data,
2770
};
2771

2772
struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2773 2774
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg)
2775 2776 2777
{
	struct iwl_trans_pcie *trans_pcie;
	struct iwl_trans *trans;
2778
	int ret, addr_size;
2779

2780 2781 2782 2783
	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
				&pdev->dev, cfg, &trans_ops_pcie, 0);
	if (!trans)
		return ERR_PTR(-ENOMEM);
2784

J
Johannes Berg 已提交
2785 2786
	trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;

2787 2788 2789
	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->trans = trans;
J
Johannes Berg 已提交
2790
	spin_lock_init(&trans_pcie->irq_lock);
2791
	spin_lock_init(&trans_pcie->reg_lock);
2792
	mutex_init(&trans_pcie->mutex);
2793
	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2794 2795 2796 2797 2798
	trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
	if (!trans_pcie->tso_hdr_page) {
		ret = -ENOMEM;
		goto out_no_pci;
	}
2799

2800 2801
	ret = pci_enable_device(pdev);
	if (ret)
J
Johannes Berg 已提交
2802 2803
		goto out_no_pci;

2804 2805 2806 2807 2808 2809 2810 2811 2812 2813
	if (!cfg->base_params->pcie_l1_allowed) {
		/*
		 * W/A - seems to solve weird behavior. We need to remove this
		 * if we don't want to stay in L1 all the time. This wastes a
		 * lot of power.
		 */
		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
				       PCIE_LINK_STATE_L1 |
				       PCIE_LINK_STATE_CLKPM);
	}
2814

2815 2816 2817 2818 2819
	if (cfg->mq_rx_supported)
		addr_size = 64;
	else
		addr_size = 36;

2820 2821
	pci_set_master(pdev);

2822
	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2823
	if (!ret)
2824 2825
		ret = pci_set_consistent_dma_mask(pdev,
						  DMA_BIT_MASK(addr_size));
2826 2827 2828 2829
	if (ret) {
		ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (!ret)
			ret = pci_set_consistent_dma_mask(pdev,
2830
							  DMA_BIT_MASK(32));
2831
		/* both attempts failed: */
2832
		if (ret) {
2833
			dev_err(&pdev->dev, "No suitable DMA available\n");
2834 2835 2836 2837
			goto out_pci_disable_device;
		}
	}

2838 2839
	ret = pci_request_regions(pdev, DRV_NAME);
	if (ret) {
2840
		dev_err(&pdev->dev, "pci_request_regions failed\n");
2841 2842 2843
		goto out_pci_disable_device;
	}

2844
	trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2845
	if (!trans_pcie->hw_base) {
2846
		dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2847
		ret = -ENODEV;
2848 2849 2850 2851 2852 2853 2854
		goto out_pci_release_regions;
	}

	/* We disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state */
	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);

2855 2856 2857 2858
	trans->dev = &pdev->dev;
	trans_pcie->pci_dev = pdev;
	iwl_disable_interrupts(trans);

2859
	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2860 2861 2862 2863 2864 2865
	/*
	 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
	 * changed, and now the revision step also includes bit 0-1 (no more
	 * "dash" value). To keep hw_rev backwards compatible - we'll store it
	 * in the old format.
	 */
2866 2867 2868
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
		unsigned long flags;

2869
		trans->hw_rev = (trans->hw_rev & 0xfff0) |
2870
				(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2871

2872 2873 2874 2875 2876 2877
		ret = iwl_pcie_prepare_card_hw(trans);
		if (ret) {
			IWL_WARN(trans, "Exit HW not ready\n");
			goto out_pci_disable_msi;
		}

2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894
		/*
		 * in-order to recognize C step driver should read chip version
		 * id located at the AUX bus MISC address space.
		 */
		iwl_set_bit(trans, CSR_GP_CNTRL,
			    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
		udelay(2);

		ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
				   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
				   25000);
		if (ret < 0) {
			IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
			goto out_pci_disable_msi;
		}

2895
		if (iwl_trans_grab_nic_access(trans, &flags)) {
2896 2897
			u32 hw_step;

2898
			hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2899
			hw_step |= ENABLE_WFPM;
2900 2901
			iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
			hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2902 2903 2904 2905 2906 2907 2908 2909
			hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
			if (hw_step == 0x3)
				trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
						(SILICON_C_STEP << 2);
			iwl_trans_release_nic_access(trans, &flags);
		}
	}

2910
	iwl_pcie_set_interrupt_capa(pdev, trans);
E
Emmanuel Grumbach 已提交
2911
	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2912 2913
	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2914

2915
	/* Initialize the wait queue for commands */
2916
	init_waitqueue_head(&trans_pcie->wait_command_queue);
2917

2918 2919
	init_waitqueue_head(&trans_pcie->d0i3_waitq);

2920 2921 2922 2923 2924 2925 2926
	if (trans_pcie->msix_enabled) {
		if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
			goto out_pci_release_regions;
	 } else {
		ret = iwl_pcie_alloc_ict(trans);
		if (ret)
			goto out_pci_disable_msi;
J
Johannes Berg 已提交
2927

2928 2929 2930 2931 2932 2933 2934 2935 2936
		ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
					   iwl_pcie_irq_handler,
					   IRQF_SHARED, DRV_NAME, trans);
		if (ret) {
			IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
			goto out_free_ict;
		}
		trans_pcie->inta_mask = CSR_INI_SET_MASK;
	 }
2937

2938 2939 2940 2941 2942 2943
#ifdef CONFIG_IWLWIFI_PCIE_RTPM
	trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
#else
	trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
#endif /* CONFIG_IWLWIFI_PCIE_RTPM */

2944 2945
	return trans;

J
Johannes Berg 已提交
2946 2947
out_free_ict:
	iwl_pcie_free_ict(trans);
2948 2949
out_pci_disable_msi:
	pci_disable_msi(pdev);
2950 2951 2952 2953 2954
out_pci_release_regions:
	pci_release_regions(pdev);
out_pci_disable_device:
	pci_disable_device(pdev);
out_no_pci:
2955
	free_percpu(trans_pcie->tso_hdr_page);
2956
	iwl_trans_free(trans);
2957
	return ERR_PTR(ret);
2958
}