patch_ca0132.c 209.0 KB
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/*
 * HD audio interface patch for Creative CA0132 chip
 *
 * Copyright (c) 2011, Creative Technology Ltd.
 *
 * Based on patch_ca0110.c
 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
 *
 *  This driver is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This driver is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/init.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/mutex.h>
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#include <linux/module.h>
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#include <linux/firmware.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
#include <linux/io.h>
#include <linux/pci.h>
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#include <sound/core.h>
#include "hda_codec.h"
#include "hda_local.h"
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#include "hda_auto_parser.h"
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#include "hda_jack.h"
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#include "ca0132_regs.h"

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/* Enable this to see controls for tuning purpose. */
/*#define ENABLE_TUNING_CONTROLS*/

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#ifdef ENABLE_TUNING_CONTROLS
#include <sound/tlv.h>
#endif

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#define FLOAT_ZERO	0x00000000
#define FLOAT_ONE	0x3f800000
#define FLOAT_TWO	0x40000000
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#define FLOAT_THREE     0x40400000
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#define FLOAT_EIGHT     0x41000000
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#define FLOAT_MINUS_5	0xc0a00000

#define UNSOL_TAG_DSP	0x16

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#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)

#define DMA_TRANSFER_FRAME_SIZE_NWORDS		8
#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS	32
#define DMA_OVERLAY_FRAME_SIZE_NWORDS		2

#define MASTERCONTROL				0x80
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#define MASTERCONTROL_ALLOC_DMA_CHAN		10
#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS	60
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#define WIDGET_CHIP_CTRL      0x15
#define WIDGET_DSP_CTRL       0x16

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#define MEM_CONNID_MICIN1     3
#define MEM_CONNID_MICIN2     5
#define MEM_CONNID_MICOUT1    12
#define MEM_CONNID_MICOUT2    14
#define MEM_CONNID_WUH        10
#define MEM_CONNID_DSP        16
#define MEM_CONNID_DMIC       100

#define SCP_SET    0
#define SCP_GET    1

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#define EFX_FILE   "ctefx.bin"
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#define SBZ_EFX_FILE   "ctefx-sbz.bin"
#define R3DI_EFX_FILE  "ctefx-r3di.bin"
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#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
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MODULE_FIRMWARE(EFX_FILE);
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MODULE_FIRMWARE(SBZ_EFX_FILE);
MODULE_FIRMWARE(R3DI_EFX_FILE);
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#endif
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static const char *const dirstr[2] = { "Playback", "Capture" };
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#define NUM_OF_OUTPUTS 3
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enum {
	SPEAKER_OUT,
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	HEADPHONE_OUT,
	SURROUND_OUT
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};

enum {
	DIGITAL_MIC,
	LINE_MIC_IN
};

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/* Strings for Input Source Enum Control */
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static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
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#define IN_SRC_NUM_OF_INPUTS 3
enum {
	REAR_MIC,
	REAR_LINE_IN,
	FRONT_MIC,
};

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enum {
#define VNODE_START_NID    0x80
	VNID_SPK = VNODE_START_NID,			/* Speaker vnid */
	VNID_MIC,
	VNID_HP_SEL,
	VNID_AMIC1_SEL,
	VNID_HP_ASEL,
	VNID_AMIC1_ASEL,
	VNODE_END_NID,
#define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)

#define EFFECT_START_NID    0x90
#define OUT_EFFECT_START_NID    EFFECT_START_NID
	SURROUND = OUT_EFFECT_START_NID,
	CRYSTALIZER,
	DIALOG_PLUS,
	SMART_VOLUME,
	X_BASS,
	EQUALIZER,
	OUT_EFFECT_END_NID,
#define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)

#define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
	ECHO_CANCELLATION = IN_EFFECT_START_NID,
	VOICE_FOCUS,
	MIC_SVM,
	NOISE_REDUCTION,
	IN_EFFECT_END_NID,
#define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)

	VOICEFX = IN_EFFECT_END_NID,
	PLAY_ENHANCEMENT,
	CRYSTAL_VOICE,
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	EFFECT_END_NID,
	OUTPUT_SOURCE_ENUM,
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	INPUT_SOURCE_ENUM,
	XBASS_XOVER,
	EQ_PRESET_ENUM,
	SMART_VOLUME_ENUM,
	MIC_BOOST_ENUM
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#define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
};

/* Effects values size*/
#define EFFECT_VALS_MAX_COUNT 12

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/*
 * Default values for the effect slider controls, they are in order of their
 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 * X-bass.
 */
static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
/* Amount of effect level sliders for ca0132_alt controls. */
#define EFFECT_LEVEL_SLIDERS 5

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/* Latency introduced by DSP blocks in milliseconds. */
#define DSP_CAPTURE_INIT_LATENCY        0
#define DSP_CRYSTAL_VOICE_LATENCY       124
#define DSP_PLAYBACK_INIT_LATENCY       13
#define DSP_PLAY_ENHANCEMENT_LATENCY    30
#define DSP_SPEAKER_OUT_LATENCY         7

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struct ct_effect {
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	char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
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	hda_nid_t nid;
	int mid; /*effect module ID*/
	int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
	int direct; /* 0:output; 1:input*/
	int params; /* number of default non-on/off params */
	/*effect default values, 1st is on/off. */
	unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
};

#define EFX_DIR_OUT 0
#define EFX_DIR_IN  1

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static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
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	{ .name = "Surround",
	  .nid = SURROUND,
	  .mid = 0x96,
	  .reqs = {0, 1},
	  .direct = EFX_DIR_OUT,
	  .params = 1,
	  .def_vals = {0x3F800000, 0x3F2B851F}
	},
	{ .name = "Crystalizer",
	  .nid = CRYSTALIZER,
	  .mid = 0x96,
	  .reqs = {7, 8},
	  .direct = EFX_DIR_OUT,
	  .params = 1,
	  .def_vals = {0x3F800000, 0x3F266666}
	},
	{ .name = "Dialog Plus",
	  .nid = DIALOG_PLUS,
	  .mid = 0x96,
	  .reqs = {2, 3},
	  .direct = EFX_DIR_OUT,
	  .params = 1,
	  .def_vals = {0x00000000, 0x3F000000}
	},
	{ .name = "Smart Volume",
	  .nid = SMART_VOLUME,
	  .mid = 0x96,
	  .reqs = {4, 5, 6},
	  .direct = EFX_DIR_OUT,
	  .params = 2,
	  .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
	},
	{ .name = "X-Bass",
	  .nid = X_BASS,
	  .mid = 0x96,
	  .reqs = {24, 23, 25},
	  .direct = EFX_DIR_OUT,
	  .params = 2,
	  .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
	},
	{ .name = "Equalizer",
	  .nid = EQUALIZER,
	  .mid = 0x96,
	  .reqs = {9, 10, 11, 12, 13, 14,
			15, 16, 17, 18, 19, 20},
	  .direct = EFX_DIR_OUT,
	  .params = 11,
	  .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
		       0x00000000, 0x00000000, 0x00000000, 0x00000000,
		       0x00000000, 0x00000000, 0x00000000, 0x00000000}
	},
	{ .name = "Echo Cancellation",
	  .nid = ECHO_CANCELLATION,
	  .mid = 0x95,
	  .reqs = {0, 1, 2, 3},
	  .direct = EFX_DIR_IN,
	  .params = 3,
	  .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
	},
	{ .name = "Voice Focus",
	  .nid = VOICE_FOCUS,
	  .mid = 0x95,
	  .reqs = {6, 7, 8, 9},
	  .direct = EFX_DIR_IN,
	  .params = 3,
	  .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
	},
	{ .name = "Mic SVM",
	  .nid = MIC_SVM,
	  .mid = 0x95,
	  .reqs = {44, 45},
	  .direct = EFX_DIR_IN,
	  .params = 1,
	  .def_vals = {0x00000000, 0x3F3D70A4}
	},
	{ .name = "Noise Reduction",
	  .nid = NOISE_REDUCTION,
	  .mid = 0x95,
	  .reqs = {4, 5},
	  .direct = EFX_DIR_IN,
	  .params = 1,
	  .def_vals = {0x3F800000, 0x3F000000}
	},
	{ .name = "VoiceFX",
	  .nid = VOICEFX,
	  .mid = 0x95,
	  .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
	  .direct = EFX_DIR_IN,
	  .params = 8,
	  .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
		       0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
		       0x00000000}
	}
};

/* Tuning controls */
#ifdef ENABLE_TUNING_CONTROLS

enum {
#define TUNING_CTL_START_NID  0xC0
	WEDGE_ANGLE = TUNING_CTL_START_NID,
	SVM_LEVEL,
	EQUALIZER_BAND_0,
	EQUALIZER_BAND_1,
	EQUALIZER_BAND_2,
	EQUALIZER_BAND_3,
	EQUALIZER_BAND_4,
	EQUALIZER_BAND_5,
	EQUALIZER_BAND_6,
	EQUALIZER_BAND_7,
	EQUALIZER_BAND_8,
	EQUALIZER_BAND_9,
	TUNING_CTL_END_NID
#define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
};

struct ct_tuning_ctl {
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	char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
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	hda_nid_t parent_nid;
	hda_nid_t nid;
	int mid; /*effect module ID*/
	int req; /*effect module request*/
	int direct; /* 0:output; 1:input*/
	unsigned int def_val;/*effect default values*/
};

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static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
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	{ .name = "Wedge Angle",
	  .parent_nid = VOICE_FOCUS,
	  .nid = WEDGE_ANGLE,
	  .mid = 0x95,
	  .req = 8,
	  .direct = EFX_DIR_IN,
	  .def_val = 0x41F00000
	},
	{ .name = "SVM Level",
	  .parent_nid = MIC_SVM,
	  .nid = SVM_LEVEL,
	  .mid = 0x95,
	  .req = 45,
	  .direct = EFX_DIR_IN,
	  .def_val = 0x3F3D70A4
	},
	{ .name = "EQ Band0",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_0,
	  .mid = 0x96,
	  .req = 11,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band1",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_1,
	  .mid = 0x96,
	  .req = 12,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band2",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_2,
	  .mid = 0x96,
	  .req = 13,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band3",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_3,
	  .mid = 0x96,
	  .req = 14,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band4",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_4,
	  .mid = 0x96,
	  .req = 15,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band5",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_5,
	  .mid = 0x96,
	  .req = 16,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band6",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_6,
	  .mid = 0x96,
	  .req = 17,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band7",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_7,
	  .mid = 0x96,
	  .req = 18,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band8",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_8,
	  .mid = 0x96,
	  .req = 19,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	},
	{ .name = "EQ Band9",
	  .parent_nid = EQUALIZER,
	  .nid = EQUALIZER_BAND_9,
	  .mid = 0x96,
	  .req = 20,
	  .direct = EFX_DIR_OUT,
	  .def_val = 0x00000000
	}
};
#endif

/* Voice FX Presets */
#define VOICEFX_MAX_PARAM_COUNT 9

struct ct_voicefx {
	char *name;
	hda_nid_t nid;
	int mid;
	int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
};

struct ct_voicefx_preset {
	char *name; /*preset name*/
	unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
};

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static const struct ct_voicefx ca0132_voicefx = {
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	.name = "VoiceFX Capture Switch",
	.nid = VOICEFX,
	.mid = 0x95,
	.reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
};

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static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
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	{ .name = "Neutral",
	  .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
		    0x44FA0000, 0x3F800000, 0x3F800000,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "Female2Male",
	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
		    0x44FA0000, 0x3F19999A, 0x3F866666,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "Male2Female",
	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
		    0x450AC000, 0x4017AE14, 0x3F6B851F,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "ScrappyKid",
	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
		    0x44FA0000, 0x40400000, 0x3F28F5C3,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "Elderly",
	  .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
		    0x44E10000, 0x3FB33333, 0x3FB9999A,
		    0x3F800000, 0x3E3A2E43, 0x00000000 }
	},
	{ .name = "Orc",
	  .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
		    0x45098000, 0x3F266666, 0x3FC00000,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "Elf",
	  .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
		    0x45193000, 0x3F8E147B, 0x3F75C28F,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "Dwarf",
	  .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
		    0x45007000, 0x3F451EB8, 0x3F7851EC,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "AlienBrute",
	  .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
		    0x451F6000, 0x3F266666, 0x3FA7D945,
		    0x3F800000, 0x3CF5C28F, 0x00000000 }
	},
	{ .name = "Robot",
	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
		    0x44FA0000, 0x3FB2718B, 0x3F800000,
		    0xBC07010E, 0x00000000, 0x00000000 }
	},
	{ .name = "Marine",
	  .vals = { 0x3F800000, 0x43C20000, 0x44906000,
		    0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
		    0x3F0A3D71, 0x00000000, 0x00000000 }
	},
	{ .name = "Emo",
	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
		    0x44FA0000, 0x3F800000, 0x3F800000,
		    0x3E4CCCCD, 0x00000000, 0x00000000 }
	},
	{ .name = "DeepVoice",
	  .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
		    0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
		    0x3F800000, 0x00000000, 0x00000000 }
	},
	{ .name = "Munchkin",
	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
		    0x44FA0000, 0x3F800000, 0x3F1A043C,
		    0x3F800000, 0x00000000, 0x00000000 }
	}
};

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/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */

#define EQ_PRESET_MAX_PARAM_COUNT 11

struct ct_eq {
	char *name;
	hda_nid_t nid;
	int mid;
	int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
};

struct ct_eq_preset {
	char *name; /*preset name*/
	unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
};

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static const struct ct_eq ca0132_alt_eq_enum = {
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	.name = "FX: Equalizer Preset Switch",
	.nid = EQ_PRESET_ENUM,
	.mid = 0x96,
	.reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
};


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static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
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	{ .name = "Flat",
	 .vals = { 0x00000000, 0x00000000, 0x00000000,
		   0x00000000, 0x00000000, 0x00000000,
		   0x00000000, 0x00000000, 0x00000000,
		   0x00000000, 0x00000000	     }
	},
	{ .name = "Acoustic",
	 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
		   0x40000000, 0x00000000, 0x00000000,
		   0x00000000, 0x00000000, 0x40000000,
		   0x40000000, 0x40000000	     }
	},
	{ .name = "Classical",
	 .vals = { 0x00000000, 0x00000000, 0x40C00000,
		   0x40C00000, 0x40466666, 0x00000000,
		   0x00000000, 0x00000000, 0x00000000,
		   0x40466666, 0x40466666	     }
	},
	{ .name = "Country",
	 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
		   0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
		   0x00000000, 0x00000000, 0x40000000,
		   0x40466666, 0x40800000	     }
	},
	{ .name = "Dance",
	 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
		   0x40466666, 0x40866666, 0xBF99999A,
		   0xBF99999A, 0x00000000, 0x00000000,
		   0x40800000, 0x40800000	     }
	},
	{ .name = "Jazz",
	 .vals = { 0x00000000, 0x00000000, 0x00000000,
		   0x3F8CCCCD, 0x40800000, 0x40800000,
		   0x40800000, 0x00000000, 0x3F8CCCCD,
		   0x40466666, 0x40466666	     }
	},
	{ .name = "New Age",
	 .vals = { 0x00000000, 0x00000000, 0x40000000,
		   0x40000000, 0x00000000, 0x00000000,
		   0x00000000, 0x3F8CCCCD, 0x40000000,
		   0x40000000, 0x40000000	     }
	},
	{ .name = "Pop",
	 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
		   0x40000000, 0x40000000, 0x00000000,
		   0xBF99999A, 0xBF99999A, 0x00000000,
		   0x40466666, 0x40C00000	     }
	},
	{ .name = "Rock",
	 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
		   0x3F8CCCCD, 0x40000000, 0xBF99999A,
		   0xBF99999A, 0x00000000, 0x00000000,
		   0x40800000, 0x40800000	     }
	},
	{ .name = "Vocal",
	 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
		   0xBF99999A, 0x00000000, 0x40466666,
		   0x40800000, 0x40466666, 0x00000000,
		   0x00000000, 0x3F8CCCCD	     }
	}
};

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/* DSP command sequences for ca0132_alt_select_out */
#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
struct ca0132_alt_out_set {
	char *name; /*preset name*/
	unsigned char commands;
	unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
	unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
	unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
};

static const struct ca0132_alt_out_set alt_out_presets[] = {
	{ .name = "Line Out",
	  .commands = 7,
	  .mids = { 0x96, 0x96, 0x96, 0x8F,
		    0x96, 0x96, 0x96 },
	  .reqs = { 0x19, 0x17, 0x18, 0x01,
		    0x1F, 0x15, 0x3A },
	  .vals = { 0x3F000000, 0x42A00000, 0x00000000,
		    0x00000000, 0x00000000, 0x00000000,
		    0x00000000 }
	},
	{ .name = "Headphone",
	  .commands = 7,
	  .mids = { 0x96, 0x96, 0x96, 0x8F,
		    0x96, 0x96, 0x96 },
	  .reqs = { 0x19, 0x17, 0x18, 0x01,
		    0x1F, 0x15, 0x3A },
	  .vals = { 0x3F000000, 0x42A00000, 0x00000000,
		    0x00000000, 0x00000000, 0x00000000,
		    0x00000000 }
	},
	{ .name = "Surround",
	  .commands = 8,
	  .mids = { 0x96, 0x8F, 0x96, 0x96,
		    0x96, 0x96, 0x96, 0x96 },
	  .reqs = { 0x18, 0x01, 0x1F, 0x15,
		    0x3A, 0x1A, 0x1B, 0x1C },
	  .vals = { 0x00000000, 0x00000000, 0x00000000,
		    0x00000000, 0x00000000, 0x00000000,
		    0x00000000, 0x00000000 }
	}
};

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/*
 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 * and I don't know what the third req is, but it's always zero. I assume it's
 * some sort of update or set command to tell the DSP there's new volume info.
 */
#define DSP_VOL_OUT 0
#define DSP_VOL_IN  1

struct ct_dsp_volume_ctl {
	hda_nid_t vnid;
	int mid; /* module ID*/
	unsigned int reqs[3]; /* scp req ID */
};

658
static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
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	{ .vnid = VNID_SPK,
	  .mid = 0x32,
	  .reqs = {3, 4, 2}
	},
	{ .vnid = VNID_MIC,
	  .mid = 0x37,
	  .reqs = {2, 3, 1}
	}
};

669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692
enum hda_cmd_vendor_io {
	/* for DspIO node */
	VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
	VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,

	VENDOR_DSPIO_STATUS                  = 0xF01,
	VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
	VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
	VENDOR_DSPIO_DSP_INIT                = 0x703,
	VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
	VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,

	/* for ChipIO node */
	VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
	VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
	VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
	VENDOR_CHIPIO_DATA_LOW               = 0x300,
	VENDOR_CHIPIO_DATA_HIGH              = 0x400,

	VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
	VENDOR_CHIPIO_STATUS                 = 0xF01,
	VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
	VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,

693 694 695
	VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
	VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,

696
	VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
697
	VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
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	VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
	VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
	VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
	VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
	VENDOR_CHIPIO_FLAG_SET               = 0x70F,
	VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
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	VENDOR_CHIPIO_PARAM_SET              = 0x710,
	VENDOR_CHIPIO_PARAM_GET              = 0xF10,
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	VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
	VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
	VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
	VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,

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	VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
	VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
	VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
	VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,

	VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
	VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
	VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
	VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
	VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
	VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,

	VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
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};

/*
 *  Control flag IDs
 */
enum control_flag_id {
	/* Connection manager stream setup is bypassed/enabled */
	CONTROL_FLAG_C_MGR                  = 0,
	/* DSP DMA is bypassed/enabled */
	CONTROL_FLAG_DMA                    = 1,
	/* 8051 'idle' mode is disabled/enabled */
	CONTROL_FLAG_IDLE_ENABLE            = 2,
	/* Tracker for the SPDIF-in path is bypassed/enabled */
	CONTROL_FLAG_TRACKER                = 3,
	/* DigitalOut to Spdif2Out connection is disabled/enabled */
	CONTROL_FLAG_SPDIF2OUT              = 4,
	/* Digital Microphone is disabled/enabled */
	CONTROL_FLAG_DMIC                   = 5,
	/* ADC_B rate is 48 kHz/96 kHz */
	CONTROL_FLAG_ADC_B_96KHZ            = 6,
	/* ADC_C rate is 48 kHz/96 kHz */
	CONTROL_FLAG_ADC_C_96KHZ            = 7,
	/* DAC rate is 48 kHz/96 kHz (affects all DACs) */
	CONTROL_FLAG_DAC_96KHZ              = 8,
	/* DSP rate is 48 kHz/96 kHz */
	CONTROL_FLAG_DSP_96KHZ              = 9,
	/* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
	CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
	/* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
	CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
	/* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
	CONTROL_FLAG_DECODE_LOOP            = 12,
	/* De-emphasis filter on DAC-1 disabled/enabled */
	CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
	/* De-emphasis filter on DAC-2 disabled/enabled */
	CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
	/* De-emphasis filter on DAC-3 disabled/enabled */
	CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
	/* High-pass filter on ADC_B disabled/enabled */
	CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
	/* High-pass filter on ADC_C disabled/enabled */
	CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
	/* Common mode on Port_A disabled/enabled */
	CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
	/* Common mode on Port_D disabled/enabled */
	CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
	/* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
	CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
	/* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
775
	CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
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	/* ASI rate is 48kHz/96kHz */
	CONTROL_FLAG_ASI_96KHZ              = 22,
	/* DAC power settings able to control attached ports no/yes */
	CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
	/* Clock Stop OK reporting is disabled/enabled */
	CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
	/* Number of control flags */
	CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
};

/*
 * Control parameter IDs
 */
789
enum control_param_id {
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	/* 0: None, 1: Mic1In*/
	CONTROL_PARAM_VIP_SOURCE               = 1,
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	/* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
	CONTROL_PARAM_SPDIF1_SOURCE            = 2,
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	/* Port A output stage gain setting to use when 16 Ohm output
	 * impedance is selected*/
	CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
	/* Port D output stage gain setting to use when 16 Ohm output
	 * impedance is selected*/
	CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
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	/* Stream Control */

	/* Select stream with the given ID */
	CONTROL_PARAM_STREAM_ID                = 24,
	/* Source connection point for the selected stream */
	CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
	/* Destination connection point for the selected stream */
	CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
	/* Number of audio channels in the selected stream */
	CONTROL_PARAM_STREAMS_CHANNELS         = 27,
	/*Enable control for the selected stream */
	CONTROL_PARAM_STREAM_CONTROL           = 28,

	/* Connection Point Control */

	/* Select connection point with the given ID */
	CONTROL_PARAM_CONN_POINT_ID            = 29,
	/* Connection point sample rate */
	CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,

	/* Node Control */

	/* Select HDA node with the given ID */
	CONTROL_PARAM_NODE_ID                  = 31
};

/*
 *  Dsp Io Status codes
 */
enum hda_vendor_status_dspio {
	/* Success */
	VENDOR_STATUS_DSPIO_OK                       = 0x00,
	/* Busy, unable to accept new command, the host must retry */
	VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
	/* SCP command queue is full */
	VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
	/* SCP response queue is empty */
	VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
};

/*
 *  Chip Io Status codes
 */
enum hda_vendor_status_chipio {
	/* Success */
	VENDOR_STATUS_CHIPIO_OK   = 0x00,
	/* Busy, unable to accept new command, the host must retry */
	VENDOR_STATUS_CHIPIO_BUSY = 0x01
};

/*
 *  CA0132 sample rate
 */
enum ca0132_sample_rate {
	SR_6_000        = 0x00,
	SR_8_000        = 0x01,
	SR_9_600        = 0x02,
	SR_11_025       = 0x03,
	SR_16_000       = 0x04,
	SR_22_050       = 0x05,
	SR_24_000       = 0x06,
	SR_32_000       = 0x07,
	SR_44_100       = 0x08,
	SR_48_000       = 0x09,
	SR_88_200       = 0x0A,
	SR_96_000       = 0x0B,
	SR_144_000      = 0x0C,
	SR_176_400      = 0x0D,
	SR_192_000      = 0x0E,
	SR_384_000      = 0x0F,

	SR_COUNT        = 0x10,

	SR_RATE_UNKNOWN = 0x1F
};

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enum dsp_download_state {
	DSP_DOWNLOAD_FAILED = -1,
	DSP_DOWNLOAD_INIT   = 0,
	DSP_DOWNLOADING     = 1,
	DSP_DOWNLOADED      = 2
};

/* retrieve parameters from hda format */
#define get_hdafmt_chs(fmt)	(fmt & 0xf)
#define get_hdafmt_bits(fmt)	((fmt >> 4) & 0x7)
#define get_hdafmt_rate(fmt)	((fmt >> 8) & 0x7f)
#define get_hdafmt_type(fmt)	((fmt >> 15) & 0x1)

/*
 * CA0132 specific
 */

struct ca0132_spec {
895
	const struct snd_kcontrol_new *mixers[5];
896
	unsigned int num_mixers;
897 898
	const struct hda_verb *base_init_verbs;
	const struct hda_verb *base_exit_verbs;
899
	const struct hda_verb *chip_init_verbs;
900
	const struct hda_verb *desktop_init_verbs;
901
	struct hda_verb *spec_init_verbs;
902
	struct auto_pin_cfg autocfg;
903 904

	/* Nodes configurations */
905 906 907
	struct hda_multi_out multiout;
	hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
	hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
908
	unsigned int num_outputs;
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	hda_nid_t input_pins[AUTO_PIN_LAST];
	hda_nid_t adcs[AUTO_PIN_LAST];
	hda_nid_t dig_out;
	hda_nid_t dig_in;
	unsigned int num_inputs;
914 915
	hda_nid_t shared_mic_nid;
	hda_nid_t shared_out_nid;
916
	hda_nid_t unsol_tag_hp;
917
	hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
918
	hda_nid_t unsol_tag_amic1;
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	/* chip access */
	struct mutex chipio_mutex; /* chip access mutex */
	u32 curr_chip_addx;

	/* DSP download related */
	enum dsp_download_state dsp_state;
	unsigned int dsp_stream_id;
	unsigned int wait_scp;
	unsigned int wait_scp_header;
	unsigned int wait_num_data;
	unsigned int scp_resp_header;
	unsigned int scp_resp_data[4];
	unsigned int scp_resp_count;
933
	bool alt_firmware_present;
934
	bool startup_check_entered;
935
	bool dsp_reload;
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	/* mixer and effects related */
	unsigned char dmic_ctl;
	int cur_out_type;
	int cur_mic_type;
	long vnode_lvol[VNODES_COUNT];
	long vnode_rvol[VNODES_COUNT];
	long vnode_lswitch[VNODES_COUNT];
	long vnode_rswitch[VNODES_COUNT];
	long effects_switch[EFFECTS_COUNT];
	long voicefx_val;
	long cur_mic_boost;
948 949 950
	/* ca0132_alt control related values */
	unsigned char in_enum_val;
	unsigned char out_enum_val;
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	unsigned char mic_boost_enum_val;
	unsigned char smart_volume_setting;
	long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
	long xbass_xover_freq;
	long eq_preset_val;
	unsigned int tlv[4];
	struct hda_vmaster_mute_hook vmaster_mute;

959

960 961
	struct hda_codec *codec;
	struct delayed_work unsol_hp_work;
962
	int quirk;
963

964 965 966
#ifdef ENABLE_TUNING_CONTROLS
	long cur_ctl_vals[TUNING_CTLS_COUNT];
#endif
967
	/*
968 969 970
	 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
	 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
	 * things.
971
	 */
972
	bool use_pci_mmio;
973
	void __iomem *mem_base;
974 975 976 977 978 979 980

	/*
	 * Whether or not to use the alt functions like alt_select_out,
	 * alt_select_in, etc. Only used on desktop codecs for now, because of
	 * surround sound support.
	 */
	bool use_alt_functions;
981 982 983 984 985 986 987

	/*
	 * Whether or not to use alt controls:	volume effect sliders, EQ
	 * presets, smart volume presets, and new control names with FX prefix.
	 * Renames PlayEnhancement and CrystalVoice too.
	 */
	bool use_alt_controls;
988 989
};

990 991 992 993 994 995
/*
 * CA0132 quirks table
 */
enum {
	QUIRK_NONE,
	QUIRK_ALIENWARE,
996
	QUIRK_ALIENWARE_M17XR4,
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	QUIRK_SBZ,
	QUIRK_R3DI,
999
	QUIRK_R3D,
1000 1001
};

1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015
static const struct hda_pintbl alienware_pincfgs[] = {
	{ 0x0b, 0x90170110 }, /* Builtin Speaker */
	{ 0x0c, 0x411111f0 }, /* N/A */
	{ 0x0d, 0x411111f0 }, /* N/A */
	{ 0x0e, 0x411111f0 }, /* N/A */
	{ 0x0f, 0x0321101f }, /* HP */
	{ 0x10, 0x411111f0 }, /* Headset?  disabled for now */
	{ 0x11, 0x03a11021 }, /* Mic */
	{ 0x12, 0xd5a30140 }, /* Builtin Mic */
	{ 0x13, 0x411111f0 }, /* N/A */
	{ 0x18, 0x411111f0 }, /* N/A */
	{}
};

1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030
/* Sound Blaster Z pin configs taken from Windows Driver */
static const struct hda_pintbl sbz_pincfgs[] = {
	{ 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
	{ 0x0d, 0x014510f0 }, /* Digital Out */
	{ 0x0e, 0x01c510f0 }, /* SPDIF In */
	{ 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
	{ 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
	{ 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
	{ 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
	{ 0x13, 0x908700f0 }, /* What U Hear In*/
	{ 0x18, 0x50d000f0 }, /* N/A */
	{}
};

1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045
/* Recon3D pin configs taken from Windows Driver */
static const struct hda_pintbl r3d_pincfgs[] = {
	{ 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
	{ 0x0d, 0x014510f0 }, /* Digital Out */
	{ 0x0e, 0x01c520f0 }, /* SPDIF In */
	{ 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
	{ 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
	{ 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
	{ 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
	{ 0x13, 0x908700f0 }, /* What U Hear In*/
	{ 0x18, 0x50d000f0 }, /* N/A */
	{}
};

1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060
/* Recon3D integrated pin configs taken from Windows Driver */
static const struct hda_pintbl r3di_pincfgs[] = {
	{ 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
	{ 0x0d, 0x014510f0 }, /* Digital Out */
	{ 0x0e, 0x41c520f0 }, /* SPDIF In */
	{ 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
	{ 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
	{ 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
	{ 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
	{ 0x13, 0x908700f0 }, /* What U Hear In*/
	{ 0x18, 0x500000f0 }, /* N/A */
	{}
};

1061
static const struct snd_pci_quirk ca0132_quirks[] = {
1062
	SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1063 1064
	SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
	SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1065
	SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1066 1067 1068
	SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
	SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
	SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1069
	SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1070
	SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1071
	SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1072 1073 1074
	{}
};

1075 1076 1077
/*
 * CA0132 codec access
 */
1078
static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111
		unsigned int verb, unsigned int parm, unsigned int *res)
{
	unsigned int response;
	response = snd_hda_codec_read(codec, nid, 0, verb, parm);
	*res = response;

	return ((response == -1) ? -1 : 0);
}

static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
		unsigned short converter_format, unsigned int *res)
{
	return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
				converter_format & 0xffff, res);
}

static int codec_set_converter_stream_channel(struct hda_codec *codec,
				hda_nid_t nid, unsigned char stream,
				unsigned char channel, unsigned int *res)
{
	unsigned char converter_stream_channel = 0;

	converter_stream_channel = (stream << 4) | (channel & 0x0f);
	return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
				converter_stream_channel, res);
}

/* Chip access helper function */
static int chipio_send(struct hda_codec *codec,
		       unsigned int reg,
		       unsigned int data)
{
	unsigned int res;
1112
	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1113 1114 1115 1116 1117 1118 1119

	/* send bits of data specified by reg */
	do {
		res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
					 reg, data);
		if (res == VENDOR_STATUS_CHIPIO_OK)
			return 0;
1120 1121 1122
		msleep(20);
	} while (time_before(jiffies, timeout));

1123 1124 1125 1126 1127 1128 1129 1130 1131
	return -EIO;
}

/*
 * Write chip address through the vendor widget -- NOT protected by the Mutex!
 */
static int chipio_write_address(struct hda_codec *codec,
				unsigned int chip_addx)
{
1132
	struct ca0132_spec *spec = codec->spec;
1133 1134
	int res;

1135 1136 1137
	if (spec->curr_chip_addx == chip_addx)
			return 0;

1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
	/* send low 16 bits of the address */
	res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
			  chip_addx & 0xffff);

	if (res != -EIO) {
		/* send high 16 bits of the address */
		res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
				  chip_addx >> 16);
	}

1148
	spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1149

1150
	return res;
1151 1152 1153 1154 1155 1156 1157
}

/*
 * Write data through the vendor widget -- NOT protected by the Mutex!
 */
static int chipio_write_data(struct hda_codec *codec, unsigned int data)
{
1158
	struct ca0132_spec *spec = codec->spec;
1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169
	int res;

	/* send low 16 bits of the data */
	res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);

	if (res != -EIO) {
		/* send high 16 bits of the data */
		res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
				  data >> 16);
	}

1170 1171 1172
	/*If no error encountered, automatically increment the address
	as per chip behaviour*/
	spec->curr_chip_addx = (res != -EIO) ?
1173
					(spec->curr_chip_addx + 4) : ~0U;
1174 1175 1176
	return res;
}

1177 1178 1179
/*
 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
 */
1180 1181 1182 1183 1184 1185 1186
static int chipio_write_data_multiple(struct hda_codec *codec,
				      const u32 *data,
				      unsigned int count)
{
	int status = 0;

	if (data == NULL) {
1187
		codec_dbg(codec, "chipio_write_data null ptr\n");
1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202
		return -EINVAL;
	}

	while ((count-- != 0) && (status == 0))
		status = chipio_write_data(codec, *data++);

	return status;
}


/*
 * Read data through the vendor widget -- NOT protected by the Mutex!
 */
static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
{
1203
	struct ca0132_spec *spec = codec->spec;
1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220
	int res;

	/* post read */
	res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);

	if (res != -EIO) {
		/* read status */
		res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
	}

	if (res != -EIO) {
		/* read data */
		*data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
					   VENDOR_CHIPIO_HIC_READ_DATA,
					   0);
	}

1221 1222 1223
	/*If no error encountered, automatically increment the address
	as per chip behaviour*/
	spec->curr_chip_addx = (res != -EIO) ?
1224
					(spec->curr_chip_addx + 4) : ~0U;
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253
	return res;
}

/*
 * Write given value to the given address through the chip I/O widget.
 * protected by the Mutex
 */
static int chipio_write(struct hda_codec *codec,
		unsigned int chip_addx, const unsigned int data)
{
	struct ca0132_spec *spec = codec->spec;
	int err;

	mutex_lock(&spec->chipio_mutex);

	/* write the address, and if successful proceed to write data */
	err = chipio_write_address(codec, chip_addx);
	if (err < 0)
		goto exit;

	err = chipio_write_data(codec, data);
	if (err < 0)
		goto exit;

exit:
	mutex_unlock(&spec->chipio_mutex);
	return err;
}

1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
/*
 * Write given value to the given address through the chip I/O widget.
 * not protected by the Mutex
 */
static int chipio_write_no_mutex(struct hda_codec *codec,
		unsigned int chip_addx, const unsigned int data)
{
	int err;


	/* write the address, and if successful proceed to write data */
	err = chipio_write_address(codec, chip_addx);
	if (err < 0)
		goto exit;

	err = chipio_write_data(codec, data);
	if (err < 0)
		goto exit;

exit:
	return err;
}

1277 1278 1279 1280
/*
 * Write multiple values to the given address through the chip I/O widget.
 * protected by the Mutex
 */
1281 1282 1283 1284 1285 1286 1287 1288 1289
static int chipio_write_multiple(struct hda_codec *codec,
				 u32 chip_addx,
				 const u32 *data,
				 unsigned int count)
{
	struct ca0132_spec *spec = codec->spec;
	int status;

	mutex_lock(&spec->chipio_mutex);
1290
	status = chipio_write_address(codec, chip_addx);
1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
	if (status < 0)
		goto error;

	status = chipio_write_data_multiple(codec, data, count);
error:
	mutex_unlock(&spec->chipio_mutex);

	return status;
}

/*
 * Read the given address through the chip I/O widget
 * protected by the Mutex
 */
static int chipio_read(struct hda_codec *codec,
		unsigned int chip_addx, unsigned int *data)
{
	struct ca0132_spec *spec = codec->spec;
	int err;

	mutex_lock(&spec->chipio_mutex);

	/* write the address, and if successful proceed to write data */
	err = chipio_write_address(codec, chip_addx);
	if (err < 0)
		goto exit;

	err = chipio_read_data(codec, data);
	if (err < 0)
		goto exit;

exit:
	mutex_unlock(&spec->chipio_mutex);
	return err;
}

1327 1328 1329
/*
 * Set chip control flags through the chip I/O widget.
 */
1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342
static void chipio_set_control_flag(struct hda_codec *codec,
				    enum control_flag_id flag_id,
				    bool flag_state)
{
	unsigned int val;
	unsigned int flag_bit;

	flag_bit = (flag_state ? 1 : 0);
	val = (flag_bit << 7) | (flag_id);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_FLAG_SET, val);
}

1343 1344 1345
/*
 * Set chip parameters through the chip I/O widget.
 */
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369
static void chipio_set_control_param(struct hda_codec *codec,
		enum control_param_id param_id, int param_val)
{
	struct ca0132_spec *spec = codec->spec;
	int val;

	if ((param_id < 32) && (param_val < 8)) {
		val = (param_val << 5) | (param_id);
		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
				    VENDOR_CHIPIO_PARAM_SET, val);
	} else {
		mutex_lock(&spec->chipio_mutex);
		if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
					    VENDOR_CHIPIO_PARAM_EX_ID_SET,
					    param_id);
			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
					    VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
					    param_val);
		}
		mutex_unlock(&spec->chipio_mutex);
	}
}

1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
/*
 * Set chip parameters through the chip I/O widget. NO MUTEX.
 */
static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
		enum control_param_id param_id, int param_val)
{
	int val;

	if ((param_id < 32) && (param_val < 8)) {
		val = (param_val << 5) | (param_id);
		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
				    VENDOR_CHIPIO_PARAM_SET, val);
	} else {
		if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
					    VENDOR_CHIPIO_PARAM_EX_ID_SET,
					    param_id);
			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
					    VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
					    param_val);
		}
	}
}
1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418
/*
 * Connect stream to a source point, and then connect
 * that source point to a destination point.
 */
static void chipio_set_stream_source_dest(struct hda_codec *codec,
				int streamid, int source_point, int dest_point)
{
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_STREAM_ID, streamid);
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
}

/*
 * Set number of channels in the selected stream.
 */
static void chipio_set_stream_channels(struct hda_codec *codec,
				int streamid, unsigned int channels)
{
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_STREAM_ID, streamid);
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_STREAMS_CHANNELS, channels);
}
1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431

/*
 * Enable/Disable audio stream.
 */
static void chipio_set_stream_control(struct hda_codec *codec,
				int streamid, int enable)
{
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_STREAM_ID, streamid);
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_STREAM_CONTROL, enable);
}

1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444

/*
 * Set sampling rate of the connection point. NO MUTEX.
 */
static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
				int connid, enum ca0132_sample_rate rate)
{
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_CONN_POINT_ID, connid);
	chipio_set_control_param_no_mutex(codec,
			CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
}

1445 1446 1447
/*
 * Set sampling rate of the connection point.
 */
1448 1449 1450 1451 1452 1453 1454 1455
static void chipio_set_conn_rate(struct hda_codec *codec,
				int connid, enum ca0132_sample_rate rate)
{
	chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
	chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
				 rate);
}

1456 1457 1458
/*
 * Enable clocks.
 */
1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484
static void chipio_enable_clocks(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	mutex_lock(&spec->chipio_mutex);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
	mutex_unlock(&spec->chipio_mutex);
}

/*
 * CA0132 DSP IO stuffs
 */
static int dspio_send(struct hda_codec *codec, unsigned int reg,
		      unsigned int data)
{
1485
	int res;
1486
	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1487 1488 1489 1490 1491 1492

	/* send bits of data specified by reg to dsp */
	do {
		res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
		if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
			return res;
1493 1494
		msleep(20);
	} while (time_before(jiffies, timeout));
1495 1496 1497 1498

	return -EIO;
}

1499 1500 1501
/*
 * Wait for DSP to be ready for commands
 */
1502 1503
static void dspio_write_wait(struct hda_codec *codec)
{
1504 1505
	int status;
	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1506 1507

	do {
1508 1509 1510 1511 1512 1513 1514
		status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
						VENDOR_DSPIO_STATUS, 0);
		if ((status == VENDOR_STATUS_DSPIO_OK) ||
		    (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
			break;
		msleep(1);
	} while (time_before(jiffies, timeout));
1515 1516
}

1517 1518 1519
/*
 * Write SCP data to DSP
 */
1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547
static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
{
	struct ca0132_spec *spec = codec->spec;
	int status;

	dspio_write_wait(codec);

	mutex_lock(&spec->chipio_mutex);
	status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
			    scp_data & 0xffff);
	if (status < 0)
		goto error;

	status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
				    scp_data >> 16);
	if (status < 0)
		goto error;

	/* OK, now check if the write itself has executed*/
	status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
				    VENDOR_DSPIO_STATUS, 0);
error:
	mutex_unlock(&spec->chipio_mutex);

	return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
			-EIO : 0;
}

1548 1549 1550
/*
 * Write multiple SCP data to DSP
 */
1551 1552 1553 1554 1555 1556
static int dspio_write_multiple(struct hda_codec *codec,
				unsigned int *buffer, unsigned int size)
{
	int status = 0;
	unsigned int count;

1557
	if (buffer == NULL)
1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570
		return -EINVAL;

	count = 0;
	while (count < size) {
		status = dspio_write(codec, *buffer++);
		if (status != 0)
			break;
		count++;
	}

	return status;
}

1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598
static int dspio_read(struct hda_codec *codec, unsigned int *data)
{
	int status;

	status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
	if (status == -EIO)
		return status;

	status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
	if (status == -EIO ||
	    status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
		return -EIO;

	*data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
				   VENDOR_DSPIO_SCP_READ_DATA, 0);

	return 0;
}

static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
			       unsigned int *buf_size, unsigned int size_count)
{
	int status = 0;
	unsigned int size = *buf_size;
	unsigned int count;
	unsigned int skip_count;
	unsigned int dummy;

1599
	if (buffer == NULL)
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
		return -1;

	count = 0;
	while (count < size && count < size_count) {
		status = dspio_read(codec, buffer++);
		if (status != 0)
			break;
		count++;
	}

	skip_count = count;
	if (status == 0) {
		while (skip_count < size) {
			status = dspio_read(codec, &dummy);
			if (status != 0)
				break;
			skip_count++;
		}
	}
	*buf_size = count;

	return status;
}

1624 1625 1626
/*
 * Construct the SCP header using corresponding fields
 */
1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646
static inline unsigned int
make_scp_header(unsigned int target_id, unsigned int source_id,
		unsigned int get_flag, unsigned int req,
		unsigned int device_flag, unsigned int resp_flag,
		unsigned int error_flag, unsigned int data_size)
{
	unsigned int header = 0;

	header = (data_size & 0x1f) << 27;
	header |= (error_flag & 0x01) << 26;
	header |= (resp_flag & 0x01) << 25;
	header |= (device_flag & 0x01) << 24;
	header |= (req & 0x7f) << 17;
	header |= (get_flag & 0x01) << 16;
	header |= (source_id & 0xff) << 8;
	header |= target_id & 0xff;

	return header;
}

1647 1648 1649
/*
 * Extract corresponding fields from SCP header
 */
1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682
static inline void
extract_scp_header(unsigned int header,
		   unsigned int *target_id, unsigned int *source_id,
		   unsigned int *get_flag, unsigned int *req,
		   unsigned int *device_flag, unsigned int *resp_flag,
		   unsigned int *error_flag, unsigned int *data_size)
{
	if (data_size)
		*data_size = (header >> 27) & 0x1f;
	if (error_flag)
		*error_flag = (header >> 26) & 0x01;
	if (resp_flag)
		*resp_flag = (header >> 25) & 0x01;
	if (device_flag)
		*device_flag = (header >> 24) & 0x01;
	if (req)
		*req = (header >> 17) & 0x7f;
	if (get_flag)
		*get_flag = (header >> 16) & 0x01;
	if (source_id)
		*source_id = (header >> 8) & 0xff;
	if (target_id)
		*target_id = header & 0xff;
}

#define SCP_MAX_DATA_WORDS  (16)

/* Structure to contain any SCP message */
struct scp_msg {
	unsigned int hdr;
	unsigned int data[SCP_MAX_DATA_WORDS];
};

1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714
static void dspio_clear_response_queue(struct hda_codec *codec)
{
	unsigned int dummy = 0;
	int status = -1;

	/* clear all from the response queue */
	do {
		status = dspio_read(codec, &dummy);
	} while (status == 0);
}

static int dspio_get_response_data(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int data = 0;
	unsigned int count;

	if (dspio_read(codec, &data) < 0)
		return -EIO;

	if ((data & 0x00ffffff) == spec->wait_scp_header) {
		spec->scp_resp_header = data;
		spec->scp_resp_count = data >> 27;
		count = spec->wait_num_data;
		dspio_read_multiple(codec, spec->scp_resp_data,
				    &spec->scp_resp_count, count);
		return 0;
	}

	return -EIO;
}

1715 1716 1717
/*
 * Send SCP message to DSP
 */
1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771
static int dspio_send_scp_message(struct hda_codec *codec,
				  unsigned char *send_buf,
				  unsigned int send_buf_size,
				  unsigned char *return_buf,
				  unsigned int return_buf_size,
				  unsigned int *bytes_returned)
{
	struct ca0132_spec *spec = codec->spec;
	int status = -1;
	unsigned int scp_send_size = 0;
	unsigned int total_size;
	bool waiting_for_resp = false;
	unsigned int header;
	struct scp_msg *ret_msg;
	unsigned int resp_src_id, resp_target_id;
	unsigned int data_size, src_id, target_id, get_flag, device_flag;

	if (bytes_returned)
		*bytes_returned = 0;

	/* get scp header from buffer */
	header = *((unsigned int *)send_buf);
	extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
			   &device_flag, NULL, NULL, &data_size);
	scp_send_size = data_size + 1;
	total_size = (scp_send_size * 4);

	if (send_buf_size < total_size)
		return -EINVAL;

	if (get_flag || device_flag) {
		if (!return_buf || return_buf_size < 4 || !bytes_returned)
			return -EINVAL;

		spec->wait_scp_header = *((unsigned int *)send_buf);

		/* swap source id with target id */
		resp_target_id = src_id;
		resp_src_id = target_id;
		spec->wait_scp_header &= 0xffff0000;
		spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
		spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
		spec->wait_scp = 1;
		waiting_for_resp = true;
	}

	status = dspio_write_multiple(codec, (unsigned int *)send_buf,
				      scp_send_size);
	if (status < 0) {
		spec->wait_scp = 0;
		return status;
	}

	if (waiting_for_resp) {
1772
		unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1773 1774 1775
		memset(return_buf, 0, return_buf_size);
		do {
			msleep(20);
1776
		} while (spec->wait_scp && time_before(jiffies, timeout));
1777
		waiting_for_resp = false;
1778
		if (!spec->wait_scp) {
1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793
			ret_msg = (struct scp_msg *)return_buf;
			memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
			memcpy(&ret_msg->data, spec->scp_resp_data,
			       spec->wait_num_data);
			*bytes_returned = (spec->scp_resp_count + 1) * 4;
			status = 0;
		} else {
			status = -EIO;
		}
		spec->wait_scp = 0;
	}

	return status;
}

1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806
/**
 * Prepare and send the SCP message to DSP
 * @codec: the HDA codec
 * @mod_id: ID of the DSP module to send the command
 * @req: ID of request to send to the DSP module
 * @dir: SET or GET
 * @data: pointer to the data to send with the request, request specific
 * @len: length of the data, in bytes
 * @reply: point to the buffer to hold data returned for a reply
 * @reply_len: length of the reply buffer returned from GET
 *
 * Returns zero or a negative error code.
 */
1807
static int dspio_scp(struct hda_codec *codec,
1808 1809
		int mod_id, int src_id, int req, int dir, const void *data,
		unsigned int len, void *reply, unsigned int *reply_len)
1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
{
	int status = 0;
	struct scp_msg scp_send, scp_reply;
	unsigned int ret_bytes, send_size, ret_size;
	unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
	unsigned int reply_data_size;

	memset(&scp_send, 0, sizeof(scp_send));
	memset(&scp_reply, 0, sizeof(scp_reply));

	if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
		return -EINVAL;

	if (dir == SCP_GET && reply == NULL) {
1824
		codec_dbg(codec, "dspio_scp get but has no buffer\n");
1825 1826 1827 1828
		return -EINVAL;
	}

	if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1829
		codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1830 1831 1832
		return -EINVAL;
	}

1833
	scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846
				       0, 0, 0, len/sizeof(unsigned int));
	if (data != NULL && len > 0) {
		len = min((unsigned int)(sizeof(scp_send.data)), len);
		memcpy(scp_send.data, data, len);
	}

	ret_bytes = 0;
	send_size = sizeof(unsigned int) + len;
	status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
					send_size, (unsigned char *)&scp_reply,
					sizeof(scp_reply), &ret_bytes);

	if (status < 0) {
1847
		codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865
		return status;
	}

	/* extract send and reply headers members */
	extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
			   NULL, NULL, NULL, NULL, NULL);
	extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
			   &reply_resp_flag, &reply_error_flag,
			   &reply_data_size);

	if (!send_get_flag)
		return 0;

	if (reply_resp_flag && !reply_error_flag) {
		ret_size = (ret_bytes - sizeof(scp_reply.hdr))
					/ sizeof(unsigned int);

		if (*reply_len < ret_size*sizeof(unsigned int)) {
1866
			codec_dbg(codec, "reply too long for buf\n");
1867 1868
			return -EINVAL;
		} else if (ret_size != reply_data_size) {
1869
			codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1870
			return -EINVAL;
1871 1872 1873
		} else if (!reply) {
			codec_dbg(codec, "NULL reply\n");
			return -EINVAL;
1874 1875 1876 1877 1878
		} else {
			*reply_len = ret_size*sizeof(unsigned int);
			memcpy(reply, scp_reply.data, *reply_len);
		}
	} else {
1879
		codec_dbg(codec, "reply ill-formed or errflag set\n");
1880 1881 1882 1883 1884 1885
		return -EIO;
	}

	return status;
}

1886 1887 1888 1889
/*
 * Set DSP parameters
 */
static int dspio_set_param(struct hda_codec *codec, int mod_id,
1890
			int src_id, int req, const void *data, unsigned int len)
1891
{
1892 1893
	return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
			NULL);
1894 1895 1896
}

static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1897
			int req, const unsigned int data)
1898
{
1899 1900 1901 1902 1903 1904 1905 1906 1907
	return dspio_set_param(codec, mod_id, 0x20, req, &data,
			sizeof(unsigned int));
}

static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
			int req, const unsigned int data)
{
	return dspio_set_param(codec, mod_id, 0x00, req, &data,
			sizeof(unsigned int));
1908 1909
}

1910 1911 1912
/*
 * Allocate a DSP DMA channel via an SCP message
 */
1913 1914 1915 1916 1917
static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
{
	int status = 0;
	unsigned int size = sizeof(dma_chan);

1918
	codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
1919 1920 1921
	status = dspio_scp(codec, MASTERCONTROL, 0x20,
			MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
			dma_chan, &size);
1922 1923

	if (status < 0) {
1924
		codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1925 1926 1927 1928
		return status;
	}

	if ((*dma_chan + 1) == 0) {
1929
		codec_dbg(codec, "no free dma channels to allocate\n");
1930 1931 1932
		return -EBUSY;
	}

1933 1934
	codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
	codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
1935 1936 1937 1938

	return status;
}

1939 1940 1941
/*
 * Free a DSP DMA via an SCP message
 */
1942 1943 1944 1945 1946
static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
{
	int status = 0;
	unsigned int dummy = 0;

1947 1948
	codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
	codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1949

1950 1951 1952
	status = dspio_scp(codec, MASTERCONTROL, 0x20,
			MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
			sizeof(dma_chan), NULL, &dummy);
1953 1954

	if (status < 0) {
1955
		codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1956 1957 1958
		return status;
	}

1959
	codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
1960 1961 1962 1963 1964

	return status;
}

/*
1965
 * (Re)start the DSP
1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998
 */
static int dsp_set_run_state(struct hda_codec *codec)
{
	unsigned int dbg_ctrl_reg;
	unsigned int halt_state;
	int err;

	err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
	if (err < 0)
		return err;

	halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
		      DSP_DBGCNTL_STATE_LOBIT;

	if (halt_state != 0) {
		dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
				  DSP_DBGCNTL_SS_MASK);
		err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
				   dbg_ctrl_reg);
		if (err < 0)
			return err;

		dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
				DSP_DBGCNTL_EXEC_MASK;
		err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
				   dbg_ctrl_reg);
		if (err < 0)
			return err;
	}

	return 0;
}

1999 2000 2001
/*
 * Reset the DSP
 */
2002 2003 2004 2005 2006
static int dsp_reset(struct hda_codec *codec)
{
	unsigned int res;
	int retry = 20;

2007
	codec_dbg(codec, "dsp_reset\n");
2008 2009 2010 2011 2012 2013
	do {
		res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
		retry--;
	} while (res == -EIO && retry);

	if (!retry) {
2014
		codec_dbg(codec, "dsp_reset timeout\n");
2015 2016 2017 2018 2019 2020
		return -EIO;
	}

	return 0;
}

2021 2022 2023
/*
 * Convert chip address to DSP address
 */
2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038
static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
					bool *code, bool *yram)
{
	*code = *yram = false;

	if (UC_RANGE(chip_addx, 1)) {
		*code = true;
		return UC_OFF(chip_addx);
	} else if (X_RANGE_ALL(chip_addx, 1)) {
		return X_OFF(chip_addx);
	} else if (Y_RANGE_ALL(chip_addx, 1)) {
		*yram = true;
		return Y_OFF(chip_addx);
	}

2039
	return INVALID_CHIP_ADDRESS;
2040 2041
}

2042 2043 2044
/*
 * Check if the DSP DMA is active
 */
2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066
static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
{
	unsigned int dma_chnlstart_reg;

	chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);

	return ((dma_chnlstart_reg & (1 <<
			(DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
}

static int dsp_dma_setup_common(struct hda_codec *codec,
				unsigned int chip_addx,
				unsigned int dma_chan,
				unsigned int port_map_mask,
				bool ovly)
{
	int status = 0;
	unsigned int chnl_prop;
	unsigned int dsp_addx;
	unsigned int active;
	bool code, yram;

2067
	codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2068 2069

	if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2070
		codec_dbg(codec, "dma chan num invalid\n");
2071 2072 2073 2074
		return -EINVAL;
	}

	if (dsp_is_dma_active(codec, dma_chan)) {
2075
		codec_dbg(codec, "dma already active\n");
2076 2077 2078 2079 2080 2081
		return -EBUSY;
	}

	dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);

	if (dsp_addx == INVALID_CHIP_ADDRESS) {
2082
		codec_dbg(codec, "invalid chip addr\n");
2083 2084 2085 2086 2087 2088
		return -ENXIO;
	}

	chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
	active = 0;

2089
	codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2090 2091 2092 2093 2094 2095

	if (ovly) {
		status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
				     &chnl_prop);

		if (status < 0) {
2096
			codec_dbg(codec, "read CHNLPROP Reg fail\n");
2097 2098
			return status;
		}
2099
		codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110
	}

	if (!code)
		chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
	else
		chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));

	chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));

	status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
	if (status < 0) {
2111
		codec_dbg(codec, "write CHNLPROP Reg fail\n");
2112 2113
		return status;
	}
2114
	codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2115 2116 2117 2118 2119 2120

	if (ovly) {
		status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
				     &active);

		if (status < 0) {
2121
			codec_dbg(codec, "read ACTIVE Reg fail\n");
2122 2123
			return status;
		}
2124
		codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2125 2126 2127 2128 2129 2130 2131
	}

	active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
		DSPDMAC_ACTIVE_AAR_MASK;

	status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
	if (status < 0) {
2132
		codec_dbg(codec, "write ACTIVE Reg fail\n");
2133 2134 2135
		return status;
	}

2136
	codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2137 2138 2139 2140

	status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
			      port_map_mask);
	if (status < 0) {
2141
		codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2142 2143
		return status;
	}
2144
	codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2145 2146 2147 2148

	status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
			DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
	if (status < 0) {
2149
		codec_dbg(codec, "write IRQCNT Reg fail\n");
2150 2151
		return status;
	}
2152
	codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2153

2154
	codec_dbg(codec,
2155 2156 2157 2158 2159
		   "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
		   "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
		   chip_addx, dsp_addx, dma_chan,
		   port_map_mask, chnl_prop, active);

2160
	codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2161 2162 2163 2164

	return 0;
}

2165 2166 2167
/*
 * Setup the DSP DMA per-transfer-specific registers
 */
2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185
static int dsp_dma_setup(struct hda_codec *codec,
			unsigned int chip_addx,
			unsigned int count,
			unsigned int dma_chan)
{
	int status = 0;
	bool code, yram;
	unsigned int dsp_addx;
	unsigned int addr_field;
	unsigned int incr_field;
	unsigned int base_cnt;
	unsigned int cur_cnt;
	unsigned int dma_cfg = 0;
	unsigned int adr_ofs = 0;
	unsigned int xfr_cnt = 0;
	const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
						DSPDMAC_XFRCNT_BCNT_LOBIT + 1);

2186
	codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2187 2188

	if (count > max_dma_count) {
2189
		codec_dbg(codec, "count too big\n");
2190 2191 2192 2193 2194
		return -EINVAL;
	}

	dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
	if (dsp_addx == INVALID_CHIP_ADDRESS) {
2195
		codec_dbg(codec, "invalid chip addr\n");
2196 2197 2198
		return -ENXIO;
	}

2199
	codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215

	addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
	incr_field   = 0;

	if (!code) {
		addr_field <<= 1;
		if (yram)
			addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);

		incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
	}

	dma_cfg = addr_field + incr_field;
	status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
				dma_cfg);
	if (status < 0) {
2216
		codec_dbg(codec, "write DMACFG Reg fail\n");
2217 2218
		return status;
	}
2219
	codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2220 2221 2222 2223 2224 2225 2226

	adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
							(code ? 0 : 1));

	status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
				adr_ofs);
	if (status < 0) {
2227
		codec_dbg(codec, "write DSPADROFS Reg fail\n");
2228 2229
		return status;
	}
2230
	codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2231 2232 2233 2234 2235 2236 2237 2238 2239 2240

	base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;

	cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;

	xfr_cnt = base_cnt | cur_cnt;

	status = chipio_write(codec,
				DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
	if (status < 0) {
2241
		codec_dbg(codec, "write XFRCNT Reg fail\n");
2242 2243
		return status;
	}
2244
	codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2245

2246
	codec_dbg(codec,
2247 2248 2249 2250
		   "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
		   "ADROFS=0x%x, XFRCNT=0x%x\n",
		   chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);

2251
	codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2252 2253 2254 2255

	return 0;
}

2256 2257 2258
/*
 * Start the DSP DMA
 */
2259 2260 2261 2262 2263 2264
static int dsp_dma_start(struct hda_codec *codec,
			 unsigned int dma_chan, bool ovly)
{
	unsigned int reg = 0;
	int status = 0;

2265
	codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2266 2267 2268 2269 2270 2271

	if (ovly) {
		status = chipio_read(codec,
				     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);

		if (status < 0) {
2272
			codec_dbg(codec, "read CHNLSTART reg fail\n");
2273 2274
			return status;
		}
2275
		codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2276 2277 2278 2279 2280 2281 2282 2283

		reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
				DSPDMAC_CHNLSTART_DIS_MASK);
	}

	status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
			reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
	if (status < 0) {
2284
		codec_dbg(codec, "write CHNLSTART reg fail\n");
2285 2286
		return status;
	}
2287
	codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2288 2289 2290 2291

	return status;
}

2292 2293 2294
/*
 * Stop the DSP DMA
 */
2295 2296 2297 2298 2299 2300
static int dsp_dma_stop(struct hda_codec *codec,
			unsigned int dma_chan, bool ovly)
{
	unsigned int reg = 0;
	int status = 0;

2301
	codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2302 2303 2304 2305 2306 2307

	if (ovly) {
		status = chipio_read(codec,
				     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);

		if (status < 0) {
2308
			codec_dbg(codec, "read CHNLSTART reg fail\n");
2309 2310
			return status;
		}
2311
		codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2312 2313 2314 2315 2316 2317 2318
		reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
				DSPDMAC_CHNLSTART_DIS_MASK);
	}

	status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
			reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
	if (status < 0) {
2319
		codec_dbg(codec, "write CHNLSTART reg fail\n");
2320 2321
		return status;
	}
2322
	codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2323 2324 2325 2326

	return status;
}

2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337
/**
 * Allocate router ports
 *
 * @codec: the HDA codec
 * @num_chans: number of channels in the stream
 * @ports_per_channel: number of ports per channel
 * @start_device: start device
 * @port_map: pointer to the port list to hold the allocated ports
 *
 * Returns zero or a negative error code.
 */
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375
static int dsp_allocate_router_ports(struct hda_codec *codec,
				     unsigned int num_chans,
				     unsigned int ports_per_channel,
				     unsigned int start_device,
				     unsigned int *port_map)
{
	int status = 0;
	int res;
	u8 val;

	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
	if (status < 0)
		return status;

	val = start_device << 6;
	val |= (ports_per_channel - 1) << 4;
	val |= num_chans - 1;

	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
			    val);

	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PORT_ALLOC_SET,
			    MEM_CONNID_DSP);

	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
	if (status < 0)
		return status;

	res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
				VENDOR_CHIPIO_PORT_ALLOC_GET, 0);

	*port_map = res;

	return (res < 0) ? res : 0;
}

2376 2377 2378
/*
 * Free router ports
 */
2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395
static int dsp_free_router_ports(struct hda_codec *codec)
{
	int status = 0;

	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
	if (status < 0)
		return status;

	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PORT_FREE_SET,
			    MEM_CONNID_DSP);

	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);

	return status;
}

2396 2397 2398
/*
 * Allocate DSP ports for the download stream
 */
2399 2400 2401 2402 2403 2404
static int dsp_allocate_ports(struct hda_codec *codec,
			unsigned int num_chans,
			unsigned int rate_multi, unsigned int *port_map)
{
	int status;

2405
	codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2406 2407

	if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2408
		codec_dbg(codec, "bad rate multiple\n");
2409 2410 2411 2412 2413 2414
		return -EINVAL;
	}

	status = dsp_allocate_router_ports(codec, num_chans,
					   rate_multi, 0, port_map);

2415
	codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431

	return status;
}

static int dsp_allocate_ports_format(struct hda_codec *codec,
			const unsigned short fmt,
			unsigned int *port_map)
{
	int status;
	unsigned int num_chans;

	unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
	unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
	unsigned int rate_multi = sample_rate_mul / sample_rate_div;

	if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2432
		codec_dbg(codec, "bad rate multiple\n");
2433 2434 2435 2436 2437 2438 2439 2440 2441 2442
		return -EINVAL;
	}

	num_chans = get_hdafmt_chs(fmt) + 1;

	status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);

	return status;
}

2443 2444 2445 2446 2447 2448 2449
/*
 * free DSP ports
 */
static int dsp_free_ports(struct hda_codec *codec)
{
	int status;

2450
	codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2451 2452 2453

	status = dsp_free_router_ports(codec);
	if (status < 0) {
2454
		codec_dbg(codec, "free router ports fail\n");
2455 2456
		return status;
	}
2457
	codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2458 2459 2460 2461

	return status;
}

2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477
/*
 *  HDA DMA engine stuffs for DSP code download
 */
struct dma_engine {
	struct hda_codec *codec;
	unsigned short m_converter_format;
	struct snd_dma_buffer *dmab;
	unsigned int buf_size;
};


enum dma_state {
	DMA_STATE_STOP  = 0,
	DMA_STATE_RUN   = 1
};

2478
static int dma_convert_to_hda_format(struct hda_codec *codec,
2479 2480
		unsigned int sample_rate,
		unsigned short channels,
2481 2482 2483 2484
		unsigned short *hda_format)
{
	unsigned int format_val;

2485 2486
	format_val = snd_hdac_calc_stream_format(sample_rate,
				channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2487 2488 2489 2490 2491 2492 2493

	if (hda_format)
		*hda_format = (unsigned short)format_val;

	return 0;
}

2494 2495 2496
/*
 *  Reset DMA for DSP download
 */
2497 2498 2499 2500 2501 2502
static int dma_reset(struct dma_engine *dma)
{
	struct hda_codec *codec = dma->codec;
	struct ca0132_spec *spec = codec->spec;
	int status;

2503
	if (dma->dmab->area)
2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516
		snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);

	status = snd_hda_codec_load_dsp_prepare(codec,
			dma->m_converter_format,
			dma->buf_size,
			dma->dmab);
	if (status < 0)
		return status;
	spec->dsp_stream_id = status;
	return 0;
}

static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2517
{
2518 2519 2520 2521 2522 2523 2524 2525 2526 2527
	bool cmd;

	switch (state) {
	case DMA_STATE_STOP:
		cmd = false;
		break;
	case DMA_STATE_RUN:
		cmd = true;
		break;
	default:
2528 2529
		return 0;
	}
2530 2531 2532

	snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
	return 0;
2533 2534
}

2535 2536 2537 2538
static unsigned int dma_get_buffer_size(struct dma_engine *dma)
{
	return dma->dmab->bytes;
}
2539

2540 2541 2542 2543
static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
{
	return dma->dmab->area;
}
2544

2545 2546 2547 2548 2549 2550 2551
static int dma_xfer(struct dma_engine *dma,
		const unsigned int *data,
		unsigned int count)
{
	memcpy(dma->dmab->area, data, count);
	return 0;
}
2552

2553 2554 2555 2556 2557 2558 2559
static void dma_get_converter_format(
		struct dma_engine *dma,
		unsigned short *format)
{
	if (format)
		*format = dma->m_converter_format;
}
2560

2561
static unsigned int dma_get_stream_id(struct dma_engine *dma)
2562
{
2563
	struct ca0132_spec *spec = dma->codec->spec;
2564

2565
	return spec->dsp_stream_id;
2566 2567
}

2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578
struct dsp_image_seg {
	u32 magic;
	u32 chip_addr;
	u32 count;
	u32 data[0];
};

static const u32 g_magic_value = 0x4c46584d;
static const u32 g_chip_addr_magic_value = 0xFFFFFF01;

static bool is_valid(const struct dsp_image_seg *p)
2579
{
2580 2581
	return p->magic == g_magic_value;
}
2582

2583 2584 2585 2586
static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
{
	return g_chip_addr_magic_value == p->chip_addr;
}
2587

2588 2589 2590 2591
static bool is_last(const struct dsp_image_seg *p)
{
	return p->count == 0;
}
2592

2593 2594 2595 2596 2597 2598 2599 2600 2601
static size_t dsp_sizeof(const struct dsp_image_seg *p)
{
	return sizeof(*p) + p->count*sizeof(u32);
}

static const struct dsp_image_seg *get_next_seg_ptr(
				const struct dsp_image_seg *p)
{
	return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2602 2603 2604
}

/*
2605
 * CA0132 chip DSP transfer stuffs.  For DSP download.
2606
 */
2607
#define INVALID_DMA_CHANNEL (~0U)
2608

2609 2610 2611 2612 2613
/*
 * Program a list of address/data pairs via the ChipIO widget.
 * The segment data is in the format of successive pairs of words.
 * These are repeated as indicated by the segment's count field.
 */
2614 2615
static int dspxfr_hci_write(struct hda_codec *codec,
			const struct dsp_image_seg *fls)
2616
{
2617 2618 2619
	int status;
	const u32 *data;
	unsigned int count;
2620

2621
	if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2622
		codec_dbg(codec, "hci_write invalid params\n");
2623
		return -EINVAL;
2624 2625
	}

2626 2627 2628 2629 2630
	count = fls->count;
	data = (u32 *)(fls->data);
	while (count >= 2) {
		status = chipio_write(codec, data[0], data[1]);
		if (status < 0) {
2631
			codec_dbg(codec, "hci_write chipio failed\n");
2632 2633 2634 2635 2636 2637
			return status;
		}
		count -= 2;
		data  += 2;
	}
	return 0;
2638 2639
}

2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654
/**
 * Write a block of data into DSP code or data RAM using pre-allocated
 * DMA engine.
 *
 * @codec: the HDA codec
 * @fls: pointer to a fast load image
 * @reloc: Relocation address for loading single-segment overlays, or 0 for
 *	   no relocation
 * @dma_engine: pointer to DMA engine to be used for DSP download
 * @dma_chan: The number of DMA channels used for DSP download
 * @port_map_mask: port mapping
 * @ovly: TRUE if overlay format is required
 *
 * Returns zero or a negative error code.
 */
2655 2656 2657 2658 2659 2660 2661
static int dspxfr_one_seg(struct hda_codec *codec,
			const struct dsp_image_seg *fls,
			unsigned int reloc,
			struct dma_engine *dma_engine,
			unsigned int dma_chan,
			unsigned int port_map_mask,
			bool ovly)
2662
{
2663
	int status = 0;
2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679
	bool comm_dma_setup_done = false;
	const unsigned int *data;
	unsigned int chip_addx;
	unsigned int words_to_write;
	unsigned int buffer_size_words;
	unsigned char *buffer_addx;
	unsigned short hda_format;
	unsigned int sample_rate_div;
	unsigned int sample_rate_mul;
	unsigned int num_chans;
	unsigned int hda_frame_size_words;
	unsigned int remainder_words;
	const u32 *data_remainder;
	u32 chip_addx_remainder;
	unsigned int run_size_words;
	const struct dsp_image_seg *hci_write = NULL;
2680 2681
	unsigned long timeout;
	bool dma_active;
2682 2683 2684 2685 2686 2687 2688

	if (fls == NULL)
		return -EINVAL;
	if (is_hci_prog_list_seg(fls)) {
		hci_write = fls;
		fls = get_next_seg_ptr(fls);
	}
2689

2690
	if (hci_write && (!fls || is_last(fls))) {
2691
		codec_dbg(codec, "hci_write\n");
2692 2693
		return dspxfr_hci_write(codec, hci_write);
	}
2694

2695
	if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2696
		codec_dbg(codec, "Invalid Params\n");
2697
		return -EINVAL;
2698 2699
	}

2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711
	data = fls->data;
	chip_addx = fls->chip_addr,
	words_to_write = fls->count;

	if (!words_to_write)
		return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
	if (reloc)
		chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);

	if (!UC_RANGE(chip_addx, words_to_write) &&
	    !X_RANGE_ALL(chip_addx, words_to_write) &&
	    !Y_RANGE_ALL(chip_addx, words_to_write)) {
2712
		codec_dbg(codec, "Invalid chip_addx Params\n");
2713
		return -EINVAL;
2714 2715
	}

2716 2717 2718 2719 2720 2721
	buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
					sizeof(u32);

	buffer_addx = dma_get_buffer_addr(dma_engine);

	if (buffer_addx == NULL) {
2722
		codec_dbg(codec, "dma_engine buffer NULL\n");
2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733
		return -EINVAL;
	}

	dma_get_converter_format(dma_engine, &hda_format);
	sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
	sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
	num_chans = get_hdafmt_chs(hda_format) + 1;

	hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
			(num_chans * sample_rate_mul / sample_rate_div));

2734
	if (hda_frame_size_words == 0) {
2735
		codec_dbg(codec, "frmsz zero\n");
2736 2737 2738
		return -EINVAL;
	}

2739 2740 2741 2742
	buffer_size_words = min(buffer_size_words,
				(unsigned int)(UC_RANGE(chip_addx, 1) ?
				65536 : 32768));
	buffer_size_words -= buffer_size_words % hda_frame_size_words;
2743
	codec_dbg(codec,
2744 2745 2746 2747 2748
		   "chpadr=0x%08x frmsz=%u nchan=%u "
		   "rate_mul=%u div=%u bufsz=%u\n",
		   chip_addx, hda_frame_size_words, num_chans,
		   sample_rate_mul, sample_rate_div, buffer_size_words);

2749
	if (buffer_size_words < hda_frame_size_words) {
2750
		codec_dbg(codec, "dspxfr_one_seg:failed\n");
2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763
		return -EINVAL;
	}

	remainder_words = words_to_write % hda_frame_size_words;
	data_remainder = data;
	chip_addx_remainder = chip_addx;

	data += remainder_words;
	chip_addx += remainder_words*sizeof(u32);
	words_to_write -= remainder_words;

	while (words_to_write != 0) {
		run_size_words = min(buffer_size_words, words_to_write);
2764
		codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2765 2766 2767 2768 2769
			    words_to_write, run_size_words, remainder_words);
		dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
		if (!comm_dma_setup_done) {
			status = dsp_dma_stop(codec, dma_chan, ovly);
			if (status < 0)
2770
				return status;
2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785
			status = dsp_dma_setup_common(codec, chip_addx,
						dma_chan, port_map_mask, ovly);
			if (status < 0)
				return status;
			comm_dma_setup_done = true;
		}

		status = dsp_dma_setup(codec, chip_addx,
						run_size_words, dma_chan);
		if (status < 0)
			return status;
		status = dsp_dma_start(codec, dma_chan, ovly);
		if (status < 0)
			return status;
		if (!dsp_is_dma_active(codec, dma_chan)) {
2786
			codec_dbg(codec, "dspxfr:DMA did not start\n");
2787 2788 2789 2790 2791 2792 2793 2794 2795 2796
			return -EIO;
		}
		status = dma_set_state(dma_engine, DMA_STATE_RUN);
		if (status < 0)
			return status;
		if (remainder_words != 0) {
			status = chipio_write_multiple(codec,
						chip_addx_remainder,
						data_remainder,
						remainder_words);
2797 2798
			if (status < 0)
				return status;
2799 2800 2801 2802
			remainder_words = 0;
		}
		if (hci_write) {
			status = dspxfr_hci_write(codec, hci_write);
2803 2804
			if (status < 0)
				return status;
2805 2806
			hci_write = NULL;
		}
2807 2808 2809 2810 2811

		timeout = jiffies + msecs_to_jiffies(2000);
		do {
			dma_active = dsp_is_dma_active(codec, dma_chan);
			if (!dma_active)
2812
				break;
2813 2814 2815 2816 2817
			msleep(20);
		} while (time_before(jiffies, timeout));
		if (dma_active)
			break;

2818
		codec_dbg(codec, "+++++ DMA complete\n");
2819
		dma_set_state(dma_engine, DMA_STATE_STOP);
2820
		status = dma_reset(dma_engine);
2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835

		if (status < 0)
			return status;

		data += run_size_words;
		chip_addx += run_size_words*sizeof(u32);
		words_to_write -= run_size_words;
	}

	if (remainder_words != 0) {
		status = chipio_write_multiple(codec, chip_addx_remainder,
					data_remainder, remainder_words);
	}

	return status;
2836 2837
}

2838 2839 2840 2841 2842 2843 2844
/**
 * Write the entire DSP image of a DSP code/data overlay to DSP memories
 *
 * @codec: the HDA codec
 * @fls_data: pointer to a fast load image
 * @reloc: Relocation address for loading single-segment overlays, or 0 for
 *	   no relocation
2845
 * @sample_rate: sampling rate of the stream used for DSP download
2846
 * @channels: channels of the stream used for DSP download
2847 2848 2849 2850
 * @ovly: TRUE if overlay format is required
 *
 * Returns zero or a negative error code.
 */
2851 2852
static int dspxfr_image(struct hda_codec *codec,
			const struct dsp_image_seg *fls_data,
2853 2854 2855
			unsigned int reloc,
			unsigned int sample_rate,
			unsigned short channels,
2856
			bool ovly)
2857 2858
{
	struct ca0132_spec *spec = codec->spec;
2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870
	int status;
	unsigned short hda_format = 0;
	unsigned int response;
	unsigned char stream_id = 0;
	struct dma_engine *dma_engine;
	unsigned int dma_chan;
	unsigned int port_map_mask;

	if (fls_data == NULL)
		return -EINVAL;

	dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2871 2872
	if (!dma_engine)
		return -ENOMEM;
2873

2874 2875
	dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
	if (!dma_engine->dmab) {
2876 2877
		kfree(dma_engine);
		return -ENOMEM;
2878
	}
2879

2880
	dma_engine->codec = codec;
2881
	dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2882 2883 2884 2885
	dma_engine->m_converter_format = hda_format;
	dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
			DSP_DMA_WRITE_BUFLEN_INIT) * 2;

2886
	dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2887 2888 2889 2890 2891

	status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
					hda_format, &response);

	if (status < 0) {
2892
		codec_dbg(codec, "set converter format fail\n");
2893 2894 2895 2896 2897 2898 2899 2900
		goto exit;
	}

	status = snd_hda_codec_load_dsp_prepare(codec,
				dma_engine->m_converter_format,
				dma_engine->buf_size,
				dma_engine->dmab);
	if (status < 0)
2901
		goto exit;
2902 2903 2904 2905 2906
	spec->dsp_stream_id = status;

	if (ovly) {
		status = dspio_alloc_dma_chan(codec, &dma_chan);
		if (status < 0) {
2907
			codec_dbg(codec, "alloc dmachan fail\n");
2908
			dma_chan = INVALID_DMA_CHANNEL;
2909 2910 2911
			goto exit;
		}
	}
2912

2913 2914 2915 2916
	port_map_mask = 0;
	status = dsp_allocate_ports_format(codec, hda_format,
					&port_map_mask);
	if (status < 0) {
2917
		codec_dbg(codec, "alloc ports fail\n");
2918 2919 2920 2921 2922 2923 2924
		goto exit;
	}

	stream_id = dma_get_stream_id(dma_engine);
	status = codec_set_converter_stream_channel(codec,
			WIDGET_CHIP_CTRL, stream_id, 0, &response);
	if (status < 0) {
2925
		codec_dbg(codec, "set stream chan fail\n");
2926 2927 2928 2929 2930
		goto exit;
	}

	while ((fls_data != NULL) && !is_last(fls_data)) {
		if (!is_valid(fls_data)) {
2931
			codec_dbg(codec, "FLS check fail\n");
2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951
			status = -EINVAL;
			goto exit;
		}
		status = dspxfr_one_seg(codec, fls_data, reloc,
					dma_engine, dma_chan,
					port_map_mask, ovly);
		if (status < 0)
			break;

		if (is_hci_prog_list_seg(fls_data))
			fls_data = get_next_seg_ptr(fls_data);

		if ((fls_data != NULL) && !is_last(fls_data))
			fls_data = get_next_seg_ptr(fls_data);
	}

	if (port_map_mask != 0)
		status = dsp_free_ports(codec);

	if (status < 0)
2952 2953
		goto exit;

2954 2955 2956
	status = codec_set_converter_stream_channel(codec,
				WIDGET_CHIP_CTRL, 0, 0, &response);

2957
exit:
2958 2959 2960
	if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
		dspio_free_dma_chan(codec, dma_chan);

2961
	if (dma_engine->dmab->area)
2962 2963 2964 2965 2966
		snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
	kfree(dma_engine->dmab);
	kfree(dma_engine);

	return status;
2967 2968 2969
}

/*
2970
 * CA0132 DSP download stuffs.
2971
 */
2972
static void dspload_post_setup(struct hda_codec *codec)
2973
{
2974
	struct ca0132_spec *spec = codec->spec;
2975
	codec_dbg(codec, "---- dspload_post_setup ------\n");
2976 2977 2978 2979
	if (!spec->use_alt_functions) {
		/*set DSP speaker to 2.0 configuration*/
		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2980

2981 2982 2983
		/*update write pointer*/
		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
	}
2984
}
2985

2986
/**
2987
 * dspload_image - Download DSP from a DSP Image Fast Load structure.
2988 2989 2990 2991 2992 2993 2994 2995 2996 2997
 *
 * @codec: the HDA codec
 * @fls: pointer to a fast load image
 * @ovly: TRUE if overlay format is required
 * @reloc: Relocation address for loading single-segment overlays, or 0 for
 *	   no relocation
 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
 * @router_chans: number of audio router channels to be allocated (0 means use
 *		  internal defaults; max is 32)
 *
2998 2999 3000 3001
 * Download DSP from a DSP Image Fast Load structure. This structure is a
 * linear, non-constant sized element array of structures, each of which
 * contain the count of the data to be loaded, the data itself, and the
 * corresponding starting chip address of the starting data location.
3002 3003
 * Returns zero or a negative error code.
 */
3004 3005 3006 3007 3008 3009 3010 3011
static int dspload_image(struct hda_codec *codec,
			const struct dsp_image_seg *fls,
			bool ovly,
			unsigned int reloc,
			bool autostart,
			int router_chans)
{
	int status = 0;
3012 3013
	unsigned int sample_rate;
	unsigned short channels;
3014

3015
	codec_dbg(codec, "---- dspload_image begin ------\n");
3016 3017 3018 3019 3020 3021
	if (router_chans == 0) {
		if (!ovly)
			router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
		else
			router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
	}
3022

3023 3024
	sample_rate = 48000;
	channels = (unsigned short)router_chans;
3025

3026 3027 3028
	while (channels > 16) {
		sample_rate *= 2;
		channels /= 2;
3029 3030 3031
	}

	do {
3032
		codec_dbg(codec, "Ready to program DMA\n");
3033 3034 3035 3036 3037 3038
		if (!ovly)
			status = dsp_reset(codec);

		if (status < 0)
			break;

3039
		codec_dbg(codec, "dsp_reset() complete\n");
3040 3041
		status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
				      ovly);
3042 3043 3044 3045

		if (status < 0)
			break;

3046
		codec_dbg(codec, "dspxfr_image() complete\n");
3047 3048 3049 3050 3051
		if (autostart && !ovly) {
			dspload_post_setup(codec);
			status = dsp_set_run_state(codec);
		}

3052
		codec_dbg(codec, "LOAD FINISHED\n");
3053 3054 3055 3056 3057
	} while (0);

	return status;
}

3058
#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069
static bool dspload_is_loaded(struct hda_codec *codec)
{
	unsigned int data = 0;
	int status = 0;

	status = chipio_read(codec, 0x40004, &data);
	if ((status < 0) || (data != 1))
		return false;

	return true;
}
3070 3071 3072
#else
#define dspload_is_loaded(codec)	false
#endif
3073 3074 3075

static bool dspload_wait_loaded(struct hda_codec *codec)
{
3076
	unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3077 3078 3079

	do {
		if (dspload_is_loaded(codec)) {
3080
			codec_info(codec, "ca0132 DSP downloaded and running\n");
3081 3082
			return true;
		}
3083 3084
		msleep(20);
	} while (time_before(jiffies, timeout));
3085

3086
	codec_err(codec, "ca0132 failed to download DSP\n");
3087
	return false;
3088 3089
}

3090 3091 3092 3093
/*
 * Setup GPIO for the other variants of Core3D.
 */

3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111
/*
 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
 * the mmio address 0x320 is used to set GPIO pins. The format for the data
 * The first eight bits are just the number of the pin. So far, I've only seen
 * this number go to 7.
 */
static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
		bool enable)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned short gpio_data;

	gpio_data = gpio_pin & 0xF;
	gpio_data |= ((enable << 8) & 0x100);

	writew(gpio_data, spec->mem_base + 0x320);
}

3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160
/*
 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
 * the card shows as having no GPIO pins.
 */
static void ca0132_gpio_init(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	switch (spec->quirk) {
	case QUIRK_SBZ:
		snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
		snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
		snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
		break;
	case QUIRK_R3DI:
		snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
		snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
		break;
	}

}

/* Sets the GPIO for audio output. */
static void ca0132_gpio_setup(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	switch (spec->quirk) {
	case QUIRK_SBZ:
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_DIRECTION, 0x07);
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_MASK, 0x07);
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_DATA, 0x04);
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_DATA, 0x06);
		break;
	case QUIRK_R3DI:
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_DIRECTION, 0x1E);
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_MASK, 0x1F);
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_DATA, 0x0C);
		break;
	}
}

3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201
/*
 * GPIO control functions for the Recon3D integrated.
 */

enum r3di_gpio_bit {
	/* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
	R3DI_MIC_SELECT_BIT = 1,
	/* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
	R3DI_OUT_SELECT_BIT = 2,
	/*
	 * I dunno what this actually does, but it stays on until the dsp
	 * is downloaded.
	 */
	R3DI_GPIO_DSP_DOWNLOADING = 3,
	/*
	 * Same as above, no clue what it does, but it comes on after the dsp
	 * is downloaded.
	 */
	R3DI_GPIO_DSP_DOWNLOADED = 4
};

enum r3di_mic_select {
	/* Set GPIO bit 1 to 0 for rear mic */
	R3DI_REAR_MIC = 0,
	/* Set GPIO bit 1 to 1 for front microphone*/
	R3DI_FRONT_MIC = 1
};

enum r3di_out_select {
	/* Set GPIO bit 2 to 0 for headphone */
	R3DI_HEADPHONE_OUT = 0,
	/* Set GPIO bit 2 to 1 for speaker */
	R3DI_LINE_OUT = 1
};
enum r3di_dsp_status {
	/* Set GPIO bit 3 to 1 until DSP is downloaded */
	R3DI_DSP_DOWNLOADING = 0,
	/* Set GPIO bit 4 to 1 once DSP is downloaded */
	R3DI_DSP_DOWNLOADED = 1
};

3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242

static void r3di_gpio_mic_set(struct hda_codec *codec,
		enum r3di_mic_select cur_mic)
{
	unsigned int cur_gpio;

	/* Get the current GPIO Data setup */
	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);

	switch (cur_mic) {
	case R3DI_REAR_MIC:
		cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
		break;
	case R3DI_FRONT_MIC:
		cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
		break;
	}
	snd_hda_codec_write(codec, codec->core.afg, 0,
			    AC_VERB_SET_GPIO_DATA, cur_gpio);
}

static void r3di_gpio_out_set(struct hda_codec *codec,
		enum r3di_out_select cur_out)
{
	unsigned int cur_gpio;

	/* Get the current GPIO Data setup */
	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);

	switch (cur_out) {
	case R3DI_HEADPHONE_OUT:
		cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
		break;
	case R3DI_LINE_OUT:
		cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
		break;
	}
	snd_hda_codec_write(codec, codec->core.afg, 0,
			    AC_VERB_SET_GPIO_DATA, cur_gpio);
}

3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271
static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
		enum r3di_dsp_status dsp_status)
{
	unsigned int cur_gpio;

	/* Get the current GPIO Data setup */
	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);

	switch (dsp_status) {
	case R3DI_DSP_DOWNLOADING:
		cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
		snd_hda_codec_write(codec, codec->core.afg, 0,
				AC_VERB_SET_GPIO_DATA, cur_gpio);
		break;
	case R3DI_DSP_DOWNLOADED:
		/* Set DOWNLOADING bit to 0. */
		cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);

		snd_hda_codec_write(codec, codec->core.afg, 0,
				AC_VERB_SET_GPIO_DATA, cur_gpio);

		cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
		break;
	}

	snd_hda_codec_write(codec, codec->core.afg, 0,
			    AC_VERB_SET_GPIO_DATA, cur_gpio);
}

3272 3273 3274
/*
 * PCM callbacks
 */
3275 3276 3277 3278 3279 3280 3281
static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
			struct hda_codec *codec,
			unsigned int stream_tag,
			unsigned int format,
			struct snd_pcm_substream *substream)
{
	struct ca0132_spec *spec = codec->spec;
3282

3283
	snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3284 3285

	return 0;
3286 3287 3288 3289 3290 3291 3292
}

static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
			struct hda_codec *codec,
			struct snd_pcm_substream *substream)
{
	struct ca0132_spec *spec = codec->spec;
3293 3294 3295 3296 3297 3298 3299 3300 3301

	if (spec->dsp_state == DSP_DOWNLOADING)
		return 0;

	/*If Playback effects are on, allow stream some time to flush
	 *effects tail*/
	if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
		msleep(50);

3302
	snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3303 3304

	return 0;
3305 3306
}

3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331
static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
			struct hda_codec *codec,
			struct snd_pcm_substream *substream)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
	struct snd_pcm_runtime *runtime = substream->runtime;

	if (spec->dsp_state != DSP_DOWNLOADED)
		return 0;

	/* Add latency if playback enhancement and either effect is enabled. */
	if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
		if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
		    (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
			latency += DSP_PLAY_ENHANCEMENT_LATENCY;
	}

	/* Applying Speaker EQ adds latency as well. */
	if (spec->cur_out_type == SPEAKER_OUT)
		latency += DSP_SPEAKER_OUT_LATENCY;

	return (latency * runtime->rate) / 1000;
}

3332 3333 3334
/*
 * Digital out
 */
3335 3336 3337
static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
					struct hda_codec *codec,
					struct snd_pcm_substream *substream)
3338 3339
{
	struct ca0132_spec *spec = codec->spec;
3340
	return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3341 3342
}

3343
static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3344 3345 3346 3347 3348 3349
			struct hda_codec *codec,
			unsigned int stream_tag,
			unsigned int format,
			struct snd_pcm_substream *substream)
{
	struct ca0132_spec *spec = codec->spec;
3350 3351
	return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
					     stream_tag, format, substream);
3352 3353
}

3354
static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3355 3356 3357 3358
			struct hda_codec *codec,
			struct snd_pcm_substream *substream)
{
	struct ca0132_spec *spec = codec->spec;
3359
	return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3360 3361
}

3362 3363 3364
static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
					 struct hda_codec *codec,
					 struct snd_pcm_substream *substream)
3365 3366
{
	struct ca0132_spec *spec = codec->spec;
3367
	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3368 3369
}

3370 3371 3372 3373 3374 3375 3376 3377 3378
/*
 * Analog capture
 */
static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
					struct hda_codec *codec,
					unsigned int stream_tag,
					unsigned int format,
					struct snd_pcm_substream *substream)
{
3379
	snd_hda_codec_setup_stream(codec, hinfo->nid,
3380
				   stream_tag, 0, format);
3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393

	return 0;
}

static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
			struct hda_codec *codec,
			struct snd_pcm_substream *substream)
{
	struct ca0132_spec *spec = codec->spec;

	if (spec->dsp_state == DSP_DOWNLOADING)
		return 0;

3394
	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3395 3396 3397
	return 0;
}

3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414
static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
			struct hda_codec *codec,
			struct snd_pcm_substream *substream)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
	struct snd_pcm_runtime *runtime = substream->runtime;

	if (spec->dsp_state != DSP_DOWNLOADED)
		return 0;

	if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
		latency += DSP_CRYSTAL_VOICE_LATENCY;

	return (latency * runtime->rate) / 1000;
}

3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434
/*
 * Controls stuffs.
 */

/*
 * Mixer controls helpers.
 */
#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
	  .name = xname, \
	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
	  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
			SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
			SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
	  .info = ca0132_volume_info, \
	  .get = ca0132_volume_get, \
	  .put = ca0132_volume_put, \
	  .tlv = { .c = ca0132_volume_tlv }, \
	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }

3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452
/*
 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
 * volume put, which is used for setting the DSP volume. This was done because
 * the ca0132 functions were taking too much time and causing lag.
 */
#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
	  .name = xname, \
	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
	  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
			SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
			SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
	  .info = snd_hda_mixer_amp_volume_info, \
	  .get = snd_hda_mixer_amp_volume_get, \
	  .put = ca0132_alt_volume_put, \
	  .tlv = { .c = snd_hda_mixer_amp_tlv }, \
	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }

3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464
#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
	  .name = xname, \
	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
	  .info = snd_hda_mixer_amp_switch_info, \
	  .get = ca0132_switch_get, \
	  .put = ca0132_switch_put, \
	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }

/* stereo */
#define CA0132_CODEC_VOL(xname, nid, dir) \
	CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3465 3466
#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
	CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3467 3468 3469
#define CA0132_CODEC_MUTE(xname, nid, dir) \
	CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)

3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498
/* lookup tables */
/*
 * Lookup table with decibel values for the DSP. When volume is changed in
 * Windows, the DSP is also sent the dB value in floating point. In Windows,
 * these values have decimal points, probably because the Windows driver
 * actually uses floating point. We can't here, so I made a lookup table of
 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
 * DAC's, and 9 is the maximum.
 */
static const unsigned int float_vol_db_lookup[] = {
0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
0x40C00000, 0x40E00000, 0x41000000, 0x41100000
};

3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546
/*
 * This table counts from float 0 to 1 in increments of .01, which is
 * useful for a few different sliders.
 */
static const unsigned int float_zero_to_one_lookup[] = {
0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
};

/*
 * This table counts from float 10 to 1000, which is the range of the x-bass
 * crossover slider in Windows.
 */
static const unsigned int float_xbass_xover_lookup[] = {
0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
0x44728000, 0x44750000, 0x44778000, 0x447A0000
};

3547
/* The following are for tuning of products */
3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621
#ifdef ENABLE_TUNING_CONTROLS

static unsigned int voice_focus_vals_lookup[] = {
0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
};

static unsigned int mic_svm_vals_lookup[] = {
0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
};

static unsigned int equalizer_vals_lookup[] = {
0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
0x41C00000
};

static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
			  unsigned int *lookup, int idx)
{
	int i = 0;

	for (i = 0; i < TUNING_CTLS_COUNT; i++)
		if (nid == ca0132_tuning_ctls[i].nid)
			break;

	snd_hda_power_up(codec);
3622
	dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747
			ca0132_tuning_ctls[i].req,
			&(lookup[idx]), sizeof(unsigned int));
	snd_hda_power_down(codec);

	return 1;
}

static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
			  struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	long *valp = ucontrol->value.integer.value;
	int idx = nid - TUNING_CTL_START_NID;

	*valp = spec->cur_ctl_vals[idx];
	return 0;
}

static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
			      struct snd_ctl_elem_info *uinfo)
{
	int chs = get_amp_channels(kcontrol);
	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = chs == 3 ? 2 : 1;
	uinfo->value.integer.min = 20;
	uinfo->value.integer.max = 180;
	uinfo->value.integer.step = 1;

	return 0;
}

static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	long *valp = ucontrol->value.integer.value;
	int idx;

	idx = nid - TUNING_CTL_START_NID;
	/* any change? */
	if (spec->cur_ctl_vals[idx] == *valp)
		return 0;

	spec->cur_ctl_vals[idx] = *valp;

	idx = *valp - 20;
	tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);

	return 1;
}

static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
			      struct snd_ctl_elem_info *uinfo)
{
	int chs = get_amp_channels(kcontrol);
	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = chs == 3 ? 2 : 1;
	uinfo->value.integer.min = 0;
	uinfo->value.integer.max = 100;
	uinfo->value.integer.step = 1;

	return 0;
}

static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	long *valp = ucontrol->value.integer.value;
	int idx;

	idx = nid - TUNING_CTL_START_NID;
	/* any change? */
	if (spec->cur_ctl_vals[idx] == *valp)
		return 0;

	spec->cur_ctl_vals[idx] = *valp;

	idx = *valp;
	tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);

	return 0;
}

static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
			      struct snd_ctl_elem_info *uinfo)
{
	int chs = get_amp_channels(kcontrol);
	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = chs == 3 ? 2 : 1;
	uinfo->value.integer.min = 0;
	uinfo->value.integer.max = 48;
	uinfo->value.integer.step = 1;

	return 0;
}

static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	long *valp = ucontrol->value.integer.value;
	int idx;

	idx = nid - TUNING_CTL_START_NID;
	/* any change? */
	if (spec->cur_ctl_vals[idx] == *valp)
		return 0;

	spec->cur_ctl_vals[idx] = *valp;

	idx = *valp;
	tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);

	return 1;
}

3748 3749
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3750 3751 3752 3753 3754

static int add_tuning_control(struct hda_codec *codec,
				hda_nid_t pnid, hda_nid_t nid,
				const char *name, int dir)
{
3755
	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824
	int type = dir ? HDA_INPUT : HDA_OUTPUT;
	struct snd_kcontrol_new knew =
		HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);

	knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
			SNDRV_CTL_ELEM_ACCESS_TLV_READ;
	knew.tlv.c = 0;
	knew.tlv.p = 0;
	switch (pnid) {
	case VOICE_FOCUS:
		knew.info = voice_focus_ctl_info;
		knew.get = tuning_ctl_get;
		knew.put = voice_focus_ctl_put;
		knew.tlv.p = voice_focus_db_scale;
		break;
	case MIC_SVM:
		knew.info = mic_svm_ctl_info;
		knew.get = tuning_ctl_get;
		knew.put = mic_svm_ctl_put;
		break;
	case EQUALIZER:
		knew.info = equalizer_ctl_info;
		knew.get = tuning_ctl_get;
		knew.put = equalizer_ctl_put;
		knew.tlv.p = eq_db_scale;
		break;
	default:
		return 0;
	}
	knew.private_value =
		HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
	sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
}

static int add_tuning_ctls(struct hda_codec *codec)
{
	int i;
	int err;

	for (i = 0; i < TUNING_CTLS_COUNT; i++) {
		err = add_tuning_control(codec,
					ca0132_tuning_ctls[i].parent_nid,
					ca0132_tuning_ctls[i].nid,
					ca0132_tuning_ctls[i].name,
					ca0132_tuning_ctls[i].direct);
		if (err < 0)
			return err;
	}

	return 0;
}

static void ca0132_init_tuning_defaults(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	int i;

	/* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
	spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
	/* SVM level defaults to 0.74. */
	spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;

	/* EQ defaults to 0dB. */
	for (i = 2; i < TUNING_CTLS_COUNT; i++)
		spec->cur_ctl_vals[i] = 24;
}
#endif /*ENABLE_TUNING_CONTROLS*/

3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839
/*
 * Select the active output.
 * If autodetect is enabled, output will be selected based on jack detection.
 * If jack inserted, headphone will be selected, else built-in speakers
 * If autodetect is disabled, output will be selected based on selection.
 */
static int ca0132_select_out(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int pin_ctl;
	int jack_present;
	int auto_jack;
	unsigned int tmp;
	int err;

3840
	codec_dbg(codec, "ca0132_select_out\n");
3841

3842
	snd_hda_power_up_pm(codec);
3843 3844 3845 3846

	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];

	if (auto_jack)
3847
		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3848 3849 3850 3851 3852 3853 3854 3855 3856 3857
	else
		jack_present =
			spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];

	if (jack_present)
		spec->cur_out_type = HEADPHONE_OUT;
	else
		spec->cur_out_type = SPEAKER_OUT;

	if (spec->cur_out_type == SPEAKER_OUT) {
3858
		codec_dbg(codec, "ca0132_select_out speaker\n");
3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882
		/*speaker out config*/
		tmp = FLOAT_ONE;
		err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
		if (err < 0)
			goto exit;
		/*enable speaker EQ*/
		tmp = FLOAT_ONE;
		err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
		if (err < 0)
			goto exit;

		/* Setup EAPD */
		snd_hda_codec_write(codec, spec->out_pins[1], 0,
				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
				    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
				    AC_VERB_SET_EAPD_BTLENABLE, 0x02);

		/* disable headphone node */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3883 3884
		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
				    pin_ctl & ~PIN_HP);
3885 3886
		/* enable speaker node */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3887
				AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3888 3889
		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
				    pin_ctl | PIN_OUT);
3890
	} else {
3891
		codec_dbg(codec, "ca0132_select_out hp\n");
3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915
		/*headphone out config*/
		tmp = FLOAT_ZERO;
		err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
		if (err < 0)
			goto exit;
		/*disable speaker EQ*/
		tmp = FLOAT_ZERO;
		err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
		if (err < 0)
			goto exit;

		/* Setup EAPD */
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
				    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
		snd_hda_codec_write(codec, spec->out_pins[1], 0,
				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
				    AC_VERB_SET_EAPD_BTLENABLE, 0x02);

		/* disable speaker*/
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3916 3917
		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
				    pin_ctl & ~PIN_HP);
3918 3919 3920
		/* enable headphone*/
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3921 3922
		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
				    pin_ctl | PIN_HP);
3923 3924 3925
	}

exit:
3926
	snd_hda_power_down_pm(codec);
3927 3928 3929 3930

	return err < 0 ? err : 0;
}

3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986
/*
 * This function behaves similarly to the ca0132_select_out funciton above,
 * except with a few differences. It adds the ability to select the current
 * output with an enumerated control "output source" if the auto detect
 * mute switch is set to off. If the auto detect mute switch is enabled, it
 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
 * It also adds the ability to auto-detect the front headphone port. The only
 * way to select surround is to disable auto detect, and set Surround with the
 * enumerated control.
 */
static int ca0132_alt_select_out(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int pin_ctl;
	int jack_present;
	int auto_jack;
	unsigned int i;
	unsigned int tmp;
	int err;
	/* Default Headphone is rear headphone */
	hda_nid_t headphone_nid = spec->out_pins[1];

	codec_dbg(codec, "%s\n", __func__);

	snd_hda_power_up_pm(codec);

	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];

	/*
	 * If headphone rear or front is plugged in, set to headphone.
	 * If neither is plugged in, set to rear line out. Only if
	 * hp/speaker auto detect is enabled.
	 */
	if (auto_jack) {
		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
			   snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);

		if (jack_present)
			spec->cur_out_type = HEADPHONE_OUT;
		else
			spec->cur_out_type = SPEAKER_OUT;
	} else
		spec->cur_out_type = spec->out_enum_val;

	/* Begin DSP output switch */
	tmp = FLOAT_ONE;
	err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
	if (err < 0)
		goto exit;

	switch (spec->cur_out_type) {
	case SPEAKER_OUT:
		codec_dbg(codec, "%s speaker\n", __func__);
		/*speaker out config*/
		switch (spec->quirk) {
		case QUIRK_SBZ:
3987 3988 3989
			ca0132_mmio_gpio_set(codec, 7, false);
			ca0132_mmio_gpio_set(codec, 4, true);
			ca0132_mmio_gpio_set(codec, 1, true);
3990 3991 3992 3993 3994 3995
			chipio_set_control_param(codec, 0x0D, 0x18);
			break;
		case QUIRK_R3DI:
			chipio_set_control_param(codec, 0x0D, 0x24);
			r3di_gpio_out_set(codec, R3DI_LINE_OUT);
			break;
3996 3997 3998 3999
		case QUIRK_R3D:
			chipio_set_control_param(codec, 0x0D, 0x24);
			ca0132_mmio_gpio_set(codec, 1, true);
			break;
4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026
		}

		/* disable headphone node */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
				    pin_ctl & ~PIN_HP);
		/* enable line-out node */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
				AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
				    pin_ctl | PIN_OUT);
		/* Enable EAPD */
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
			AC_VERB_SET_EAPD_BTLENABLE, 0x01);

		/* If PlayEnhancement is enabled, set different source */
		if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
		else
			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
		break;
	case HEADPHONE_OUT:
		codec_dbg(codec, "%s hp\n", __func__);
		/* Headphone out config*/
		switch (spec->quirk) {
		case QUIRK_SBZ:
4027 4028 4029
			ca0132_mmio_gpio_set(codec, 7, true);
			ca0132_mmio_gpio_set(codec, 4, true);
			ca0132_mmio_gpio_set(codec, 1, false);
4030 4031 4032 4033 4034 4035
			chipio_set_control_param(codec, 0x0D, 0x12);
			break;
		case QUIRK_R3DI:
			chipio_set_control_param(codec, 0x0D, 0x21);
			r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
			break;
4036 4037 4038 4039
		case QUIRK_R3D:
			chipio_set_control_param(codec, 0x0D, 0x21);
			ca0132_mmio_gpio_set(codec, 0x1, false);
			break;
4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072
		}

		snd_hda_codec_write(codec, spec->out_pins[0], 0,
			AC_VERB_SET_EAPD_BTLENABLE, 0x00);

		/* disable speaker*/
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
				pin_ctl & ~PIN_HP);

		/* enable headphone, either front or rear */

		if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
			headphone_nid = spec->out_pins[2];
		else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
			headphone_nid = spec->out_pins[1];

		pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, headphone_nid,
				    pin_ctl | PIN_HP);

		if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
		else
			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
		break;
	case SURROUND_OUT:
		codec_dbg(codec, "%s surround\n", __func__);
		/* Surround out config*/
		switch (spec->quirk) {
		case QUIRK_SBZ:
4073 4074 4075
			ca0132_mmio_gpio_set(codec, 7, false);
			ca0132_mmio_gpio_set(codec, 4, true);
			ca0132_mmio_gpio_set(codec, 1, true);
4076 4077 4078 4079 4080 4081
			chipio_set_control_param(codec, 0x0D, 0x18);
			break;
		case QUIRK_R3DI:
			chipio_set_control_param(codec, 0x0D, 0x24);
			r3di_gpio_out_set(codec, R3DI_LINE_OUT);
			break;
4082 4083 4084 4085
		case QUIRK_R3D:
			ca0132_mmio_gpio_set(codec, 1, true);
			chipio_set_control_param(codec, 0x0D, 0x24);
			break;
4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134
		}
		/* enable line out node */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
				AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
						pin_ctl | PIN_OUT);
		/* Disable headphone out */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
				    pin_ctl & ~PIN_HP);
		/* Enable EAPD on line out */
		snd_hda_codec_write(codec, spec->out_pins[0], 0,
			AC_VERB_SET_EAPD_BTLENABLE, 0x01);
		/* enable center/lfe out node */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, spec->out_pins[2],
				    pin_ctl | PIN_OUT);
		/* Now set rear surround node as out. */
		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
		snd_hda_set_pin_ctl(codec, spec->out_pins[3],
				    pin_ctl | PIN_OUT);

		if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
		else
			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
		break;
	}

	/* run through the output dsp commands for line-out */
	for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
		err = dspio_set_uint_param(codec,
		alt_out_presets[spec->cur_out_type].mids[i],
		alt_out_presets[spec->cur_out_type].reqs[i],
		alt_out_presets[spec->cur_out_type].vals[i]);

		if (err < 0)
			goto exit;
	}

exit:
	snd_hda_power_down_pm(codec);

	return err < 0 ? err : 0;
}

4135 4136 4137 4138
static void ca0132_unsol_hp_delayed(struct work_struct *work)
{
	struct ca0132_spec *spec = container_of(
		to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4139 4140
	struct hda_jack_tbl *jack;

4141 4142 4143 4144 4145
	if (spec->use_alt_functions)
		ca0132_alt_select_out(spec->codec);
	else
		ca0132_select_out(spec->codec);

4146
	jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4147 4148 4149 4150
	if (jack) {
		jack->block_report = 0;
		snd_hda_jack_report_sync(spec->codec);
	}
4151 4152
}

4153 4154 4155
static void ca0132_set_dmic(struct hda_codec *codec, int enable);
static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4156 4157 4158
static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
static int stop_mic1(struct hda_codec *codec);
static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4159
static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4160 4161 4162 4163 4164 4165 4166 4167 4168

/*
 * Select the active VIP source
 */
static int ca0132_set_vipsource(struct hda_codec *codec, int val)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int tmp;

4169
	if (spec->dsp_state != DSP_DOWNLOADED)
4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201
		return 0;

	/* if CrystalVoice if off, vipsource should be 0 */
	if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
	    (val == 0)) {
		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
		if (spec->cur_mic_type == DIGITAL_MIC)
			tmp = FLOAT_TWO;
		else
			tmp = FLOAT_ONE;
		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
		tmp = FLOAT_ZERO;
		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
	} else {
		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
		if (spec->cur_mic_type == DIGITAL_MIC)
			tmp = FLOAT_TWO;
		else
			tmp = FLOAT_ONE;
		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
		tmp = FLOAT_ONE;
		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
		msleep(20);
		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
	}

	return 1;
}

4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266
static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int tmp;

	if (spec->dsp_state != DSP_DOWNLOADED)
		return 0;

	codec_dbg(codec, "%s\n", __func__);

	chipio_set_stream_control(codec, 0x03, 0);
	chipio_set_stream_control(codec, 0x04, 0);

	/* if CrystalVoice is off, vipsource should be 0 */
	if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
	    (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
		codec_dbg(codec, "%s: off.", __func__);
		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);

		tmp = FLOAT_ZERO;
		dspio_set_uint_param(codec, 0x80, 0x05, tmp);

		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
		if (spec->quirk == QUIRK_R3DI)
			chipio_set_conn_rate(codec, 0x0F, SR_96_000);


		if (spec->in_enum_val == REAR_LINE_IN)
			tmp = FLOAT_ZERO;
		else {
			if (spec->quirk == QUIRK_SBZ)
				tmp = FLOAT_THREE;
			else
				tmp = FLOAT_ONE;
		}

		dspio_set_uint_param(codec, 0x80, 0x00, tmp);

	} else {
		codec_dbg(codec, "%s: on.", __func__);
		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
		if (spec->quirk == QUIRK_R3DI)
			chipio_set_conn_rate(codec, 0x0F, SR_16_000);

		if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
			tmp = FLOAT_TWO;
		else
			tmp = FLOAT_ONE;
		dspio_set_uint_param(codec, 0x80, 0x00, tmp);

		tmp = FLOAT_ONE;
		dspio_set_uint_param(codec, 0x80, 0x05, tmp);

		msleep(20);
		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
	}

	chipio_set_stream_control(codec, 0x03, 1);
	chipio_set_stream_control(codec, 0x04, 1);

	return 1;
}

4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278
/*
 * Select the active microphone.
 * If autodetect is enabled, mic will be selected based on jack detection.
 * If jack inserted, ext.mic will be selected, else built-in mic
 * If autodetect is disabled, mic will be selected based on selection.
 */
static int ca0132_select_mic(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	int jack_present;
	int auto_jack;

4279
	codec_dbg(codec, "ca0132_select_mic\n");
4280

4281
	snd_hda_power_up_pm(codec);
4282 4283 4284 4285

	auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];

	if (auto_jack)
4286
		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313
	else
		jack_present =
			spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];

	if (jack_present)
		spec->cur_mic_type = LINE_MIC_IN;
	else
		spec->cur_mic_type = DIGITAL_MIC;

	if (spec->cur_mic_type == DIGITAL_MIC) {
		/* enable digital Mic */
		chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
		ca0132_set_dmic(codec, 1);
		ca0132_mic_boost_set(codec, 0);
		/* set voice focus */
		ca0132_effects_set(codec, VOICE_FOCUS,
				   spec->effects_switch
				   [VOICE_FOCUS - EFFECT_START_NID]);
	} else {
		/* disable digital Mic */
		chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
		ca0132_set_dmic(codec, 0);
		ca0132_mic_boost_set(codec, spec->cur_mic_boost);
		/* disable voice focus */
		ca0132_effects_set(codec, VOICE_FOCUS, 0);
	}

4314
	snd_hda_power_down_pm(codec);
4315 4316 4317 4318

	return 0;
}

4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342
/*
 * Select the active input.
 * Mic detection isn't used, because it's kind of pointless on the SBZ.
 * The front mic has no jack-detection, so the only way to switch to it
 * is to do it manually in alsamixer.
 */
static int ca0132_alt_select_in(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int tmp;

	codec_dbg(codec, "%s\n", __func__);

	snd_hda_power_up_pm(codec);

	chipio_set_stream_control(codec, 0x03, 0);
	chipio_set_stream_control(codec, 0x04, 0);

	spec->cur_mic_type = spec->in_enum_val;

	switch (spec->cur_mic_type) {
	case REAR_MIC:
		switch (spec->quirk) {
		case QUIRK_SBZ:
4343
		case QUIRK_R3D:
4344
			ca0132_mmio_gpio_set(codec, 0, false);
4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369
			tmp = FLOAT_THREE;
			break;
		case QUIRK_R3DI:
			r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
			tmp = FLOAT_ONE;
			break;
		default:
			tmp = FLOAT_ONE;
			break;
		}

		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
		if (spec->quirk == QUIRK_R3DI)
			chipio_set_conn_rate(codec, 0x0F, SR_96_000);

		dspio_set_uint_param(codec, 0x80, 0x00, tmp);

		chipio_set_stream_control(codec, 0x03, 1);
		chipio_set_stream_control(codec, 0x04, 1);

		if (spec->quirk == QUIRK_SBZ) {
			chipio_write(codec, 0x18B098, 0x0000000C);
			chipio_write(codec, 0x18B09C, 0x0000000C);
		}
4370
		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4371 4372 4373 4374 4375
		break;
	case REAR_LINE_IN:
		ca0132_mic_boost_set(codec, 0);
		switch (spec->quirk) {
		case QUIRK_SBZ:
4376
		case QUIRK_R3D:
4377
			ca0132_mmio_gpio_set(codec, 0, false);
4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402
			break;
		case QUIRK_R3DI:
			r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
			break;
		}

		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
		if (spec->quirk == QUIRK_R3DI)
			chipio_set_conn_rate(codec, 0x0F, SR_96_000);

		tmp = FLOAT_ZERO;
		dspio_set_uint_param(codec, 0x80, 0x00, tmp);

		if (spec->quirk == QUIRK_SBZ) {
			chipio_write(codec, 0x18B098, 0x00000000);
			chipio_write(codec, 0x18B09C, 0x00000000);
		}

		chipio_set_stream_control(codec, 0x03, 1);
		chipio_set_stream_control(codec, 0x04, 1);
		break;
	case FRONT_MIC:
		switch (spec->quirk) {
		case QUIRK_SBZ:
4403
		case QUIRK_R3D:
4404 4405
			ca0132_mmio_gpio_set(codec, 0, true);
			ca0132_mmio_gpio_set(codec, 5, false);
4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430
			tmp = FLOAT_THREE;
			break;
		case QUIRK_R3DI:
			r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
			tmp = FLOAT_ONE;
			break;
		default:
			tmp = FLOAT_ONE;
			break;
		}

		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
		if (spec->quirk == QUIRK_R3DI)
			chipio_set_conn_rate(codec, 0x0F, SR_96_000);

		dspio_set_uint_param(codec, 0x80, 0x00, tmp);

		chipio_set_stream_control(codec, 0x03, 1);
		chipio_set_stream_control(codec, 0x04, 1);

		if (spec->quirk == QUIRK_SBZ) {
			chipio_write(codec, 0x18B098, 0x0000000C);
			chipio_write(codec, 0x18B09C, 0x000000CC);
		}
4431
		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4432 4433
		break;
	}
4434
	ca0132_cvoice_switch_set(codec);
4435 4436 4437 4438 4439 4440

	snd_hda_power_down_pm(codec);
	return 0;

}

4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458
/*
 * Check if VNODE settings take effect immediately.
 */
static bool ca0132_is_vnode_effective(struct hda_codec *codec,
				     hda_nid_t vnid,
				     hda_nid_t *shared_nid)
{
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid;

	switch (vnid) {
	case VNID_SPK:
		nid = spec->shared_out_nid;
		break;
	case VNID_MIC:
		nid = spec->shared_mic_nid;
		break;
	default:
4459
		return false;
4460 4461
	}

4462
	if (shared_nid)
4463 4464
		*shared_nid = nid;

4465
	return true;
4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490
}

/*
* The following functions are control change helpers.
* They return 0 if no changed.  Return 1 if changed.
*/
static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int tmp;

	/* based on CrystalVoice state to enable VoiceFX. */
	if (enable) {
		tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
			FLOAT_ONE : FLOAT_ZERO;
	} else {
		tmp = FLOAT_ZERO;
	}

	dspio_set_uint_param(codec, ca0132_voicefx.mid,
			     ca0132_voicefx.reqs[0], tmp);

	return 1;
}

4491 4492 4493 4494 4495 4496
/*
 * Set the effects parameters
 */
static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
{
	struct ca0132_spec *spec = codec->spec;
4497
	unsigned int on, tmp;
4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520
	int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
	int err = 0;
	int idx = nid - EFFECT_START_NID;

	if ((idx < 0) || (idx >= num_fx))
		return 0; /* no changed */

	/* for out effect, qualify with PE */
	if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
		/* if PE if off, turn off out effects. */
		if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
			val = 0;
	}

	/* for in effect, qualify with CrystalVoice */
	if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
		/* if CrystalVoice if off, turn off in effects. */
		if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
			val = 0;

		/* Voice Focus applies to 2-ch Mic, Digital Mic */
		if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
			val = 0;
4521 4522

		/* If Voice Focus on SBZ, set to two channel. */
4523 4524
		if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
				&& (spec->cur_mic_type != REAR_LINE_IN)) {
4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541
			if (spec->effects_switch[CRYSTAL_VOICE -
						 EFFECT_START_NID]) {

				if (spec->effects_switch[VOICE_FOCUS -
							 EFFECT_START_NID]) {
					tmp = FLOAT_TWO;
					val = 1;
				} else
					tmp = FLOAT_ONE;

				dspio_set_uint_param(codec, 0x80, 0x00, tmp);
			}
		}
		/*
		 * For SBZ noise reduction, there's an extra command
		 * to module ID 0x47. No clue why.
		 */
4542 4543
		if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
				&& (spec->cur_mic_type != REAR_LINE_IN)) {
4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555
			if (spec->effects_switch[CRYSTAL_VOICE -
						 EFFECT_START_NID]) {
				if (spec->effects_switch[NOISE_REDUCTION -
							 EFFECT_START_NID])
					tmp = FLOAT_ONE;
				else
					tmp = FLOAT_ZERO;
			} else
				tmp = FLOAT_ZERO;

			dspio_set_uint_param(codec, 0x47, 0x00, tmp);
		}
4556 4557 4558 4559 4560

		/* If rear line in disable effects. */
		if (spec->use_alt_functions &&
				spec->in_enum_val == REAR_LINE_IN)
			val = 0;
4561 4562
	}

4563
	codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575
		    nid, val);

	on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
	err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
				   ca0132_effects[idx].reqs[0], on);

	if (err < 0)
		return 0; /* no changed */

	return 1;
}

4576 4577 4578 4579 4580 4581 4582 4583 4584
/*
 * Turn on/off Playback Enhancements
 */
static int ca0132_pe_switch_set(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid;
	int i, ret = 0;

4585
	codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4586 4587
		    spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);

4588 4589 4590
	if (spec->use_alt_functions)
		ca0132_alt_select_out(codec);

4591 4592 4593 4594 4595 4596 4597 4598 4599
	i = OUT_EFFECT_START_NID - EFFECT_START_NID;
	nid = OUT_EFFECT_START_NID;
	/* PE affects all out effects */
	for (; nid < OUT_EFFECT_END_NID; nid++, i++)
		ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);

	return ret;
}

4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624
/* Check if Mic1 is streaming, if so, stop streaming */
static int stop_mic1(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
						 AC_VERB_GET_CONV, 0);
	if (oldval != 0)
		snd_hda_codec_write(codec, spec->adcs[0], 0,
				    AC_VERB_SET_CHANNEL_STREAMID,
				    0);
	return oldval;
}

/* Resume Mic1 streaming if it was stopped. */
static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
{
	struct ca0132_spec *spec = codec->spec;
	/* Restore the previous stream and channel */
	if (oldval != 0)
		snd_hda_codec_write(codec, spec->adcs[0], 0,
				    AC_VERB_SET_CHANNEL_STREAMID,
				    oldval);
}

/*
4625
 * Turn on/off CrystalVoice
4626
 */
4627 4628 4629 4630 4631 4632 4633
static int ca0132_cvoice_switch_set(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid;
	int i, ret = 0;
	unsigned int oldval;

4634
	codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647
		    spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);

	i = IN_EFFECT_START_NID - EFFECT_START_NID;
	nid = IN_EFFECT_START_NID;
	/* CrystalVoice affects all in effects */
	for (; nid < IN_EFFECT_END_NID; nid++, i++)
		ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);

	/* including VoiceFX */
	ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));

	/* set correct vipsource */
	oldval = stop_mic1(codec);
4648 4649 4650 4651
	if (spec->use_alt_functions)
		ret |= ca0132_alt_set_vipsource(codec, 1);
	else
		ret |= ca0132_set_vipsource(codec, 1);
4652 4653 4654 4655
	resume_mic1(codec, oldval);
	return ret;
}

4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670
static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
{
	struct ca0132_spec *spec = codec->spec;
	int ret = 0;

	if (val) /* on */
		ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
					HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
	else /* off */
		ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
					HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);

	return ret;
}

4671 4672 4673 4674 4675 4676 4677 4678 4679 4680
static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
{
	struct ca0132_spec *spec = codec->spec;
	int ret = 0;

	ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
				HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
	return ret;
}

4681 4682
static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
4683
{
4684 4685 4686 4687 4688
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	hda_nid_t nid = get_amp_nid(kcontrol);
	hda_nid_t shared_nid = 0;
	bool effective;
	int ret = 0;
4689
	struct ca0132_spec *spec = codec->spec;
4690
	int auto_jack;
4691

4692 4693 4694
	if (nid == VNID_HP_SEL) {
		auto_jack =
			spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4695 4696 4697 4698 4699 4700
		if (!auto_jack) {
			if (spec->use_alt_functions)
				ca0132_alt_select_out(codec);
			else
				ca0132_select_out(codec);
		}
4701 4702
		return 1;
	}
4703

4704 4705 4706 4707 4708 4709 4710
	if (nid == VNID_AMIC1_SEL) {
		auto_jack =
			spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
		if (!auto_jack)
			ca0132_select_mic(codec);
		return 1;
	}
4711

4712
	if (nid == VNID_HP_ASEL) {
4713 4714 4715 4716
		if (spec->use_alt_functions)
			ca0132_alt_select_out(codec);
		else
			ca0132_select_out(codec);
4717 4718
		return 1;
	}
4719

4720 4721 4722
	if (nid == VNID_AMIC1_ASEL) {
		ca0132_select_mic(codec);
		return 1;
4723
	}
4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738

	/* if effective conditions, then update hw immediately. */
	effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
	if (effective) {
		int dir = get_amp_direction(kcontrol);
		int ch = get_amp_channels(kcontrol);
		unsigned long pval;

		mutex_lock(&codec->control_mutex);
		pval = kcontrol->private_value;
		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
								0, dir);
		ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
		kcontrol->private_value = pval;
		mutex_unlock(&codec->control_mutex);
4739 4740
	}

4741
	return ret;
4742
}
4743
/* End of control change helpers. */
4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944
/*
 * Below I've added controls to mess with the effect levels, I've only enabled
 * them on the Sound Blaster Z, but they would probably also work on the
 * Chromebook. I figured they were probably tuned specifically for it, and left
 * out for a reason.
 */

/* Sets DSP effect level from the sliders above the controls */
static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
			  const unsigned int *lookup, int idx)
{
	int i = 0;
	unsigned int y;
	/*
	 * For X_BASS, req 2 is actually crossover freq instead of
	 * effect level
	 */
	if (nid == X_BASS)
		y = 2;
	else
		y = 1;

	snd_hda_power_up(codec);
	if (nid == XBASS_XOVER) {
		for (i = 0; i < OUT_EFFECTS_COUNT; i++)
			if (ca0132_effects[i].nid == X_BASS)
				break;

		dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
				ca0132_effects[i].reqs[1],
				&(lookup[idx - 1]), sizeof(unsigned int));
	} else {
		/* Find the actual effect structure */
		for (i = 0; i < OUT_EFFECTS_COUNT; i++)
			if (nid == ca0132_effects[i].nid)
				break;

		dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
				ca0132_effects[i].reqs[y],
				&(lookup[idx]), sizeof(unsigned int));
	}

	snd_hda_power_down(codec);

	return 0;
}

static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
			  struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	long *valp = ucontrol->value.integer.value;

	*valp = spec->xbass_xover_freq;
	return 0;
}

static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
			  struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	long *valp = ucontrol->value.integer.value;
	int idx = nid - OUT_EFFECT_START_NID;

	*valp = spec->fx_ctl_val[idx];
	return 0;
}

/*
 * The X-bass crossover starts at 10hz, so the min is 1. The
 * frequency is set in multiples of 10.
 */
static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
		struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = 1;
	uinfo->value.integer.min = 1;
	uinfo->value.integer.max = 100;
	uinfo->value.integer.step = 1;

	return 0;
}

static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
		struct snd_ctl_elem_info *uinfo)
{
	int chs = get_amp_channels(kcontrol);

	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	uinfo->count = chs == 3 ? 2 : 1;
	uinfo->value.integer.min = 0;
	uinfo->value.integer.max = 100;
	uinfo->value.integer.step = 1;

	return 0;
}

static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	long *valp = ucontrol->value.integer.value;
	int idx;

	/* any change? */
	if (spec->xbass_xover_freq == *valp)
		return 0;

	spec->xbass_xover_freq = *valp;

	idx = *valp;
	ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);

	return 0;
}

static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	long *valp = ucontrol->value.integer.value;
	int idx;

	idx = nid - EFFECT_START_NID;
	/* any change? */
	if (spec->fx_ctl_val[idx] == *valp)
		return 0;

	spec->fx_ctl_val[idx] = *valp;

	idx = *valp;
	ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);

	return 0;
}


/*
 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
 * only has off or full 30 dB, and didn't like making a volume slider that has
 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
 */
#define MIC_BOOST_NUM_OF_STEPS 4
#define MIC_BOOST_ENUM_MAX_STRLEN 10

static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_info *uinfo)
{
	char *sfx = "dB";
	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];

	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	uinfo->count = 1;
	uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
	if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
		uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
	sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
	strcpy(uinfo->value.enumerated.name, namestr);
	return 0;
}

static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;

	ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
	return 0;
}

static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	int sel = ucontrol->value.enumerated.item[0];
	unsigned int items = MIC_BOOST_NUM_OF_STEPS;

	if (sel >= items)
		return 0;

	codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
		    sel);

	spec->mic_boost_enum_val = sel;

	if (spec->in_enum_val != REAR_LINE_IN)
		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);

	return 1;
}

4945

4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043
/*
 * Input Select Control for alternative ca0132 codecs. This exists because
 * front microphone has no auto-detect, and we need a way to set the rear
 * as line-in
 */
static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	uinfo->count = 1;
	uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
	if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
		uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
	strcpy(uinfo->value.enumerated.name,
			in_src_str[uinfo->value.enumerated.item]);
	return 0;
}

static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;

	ucontrol->value.enumerated.item[0] = spec->in_enum_val;
	return 0;
}

static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	int sel = ucontrol->value.enumerated.item[0];
	unsigned int items = IN_SRC_NUM_OF_INPUTS;

	if (sel >= items)
		return 0;

	codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
		    sel, in_src_str[sel]);

	spec->in_enum_val = sel;

	ca0132_alt_select_in(codec);

	return 1;
}

/* Sound Blaster Z Output Select Control */
static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	uinfo->count = 1;
	uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
	if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
		uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
	strcpy(uinfo->value.enumerated.name,
			alt_out_presets[uinfo->value.enumerated.item].name);
	return 0;
}

static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;

	ucontrol->value.enumerated.item[0] = spec->out_enum_val;
	return 0;
}

static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	int sel = ucontrol->value.enumerated.item[0];
	unsigned int items = NUM_OF_OUTPUTS;
	unsigned int auto_jack;

	if (sel >= items)
		return 0;

	codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
		    sel, alt_out_presets[sel].name);

	spec->out_enum_val = sel;

	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];

	if (!auto_jack)
		ca0132_alt_select_out(codec);

	return 1;
}

5044 5045 5046 5047 5048 5049
/*
 * Smart Volume output setting control. Three different settings, Normal,
 * which takes the value from the smart volume slider. The two others, loud
 * and night, disregard the slider value and have uneditable values.
 */
#define NUM_OF_SVM_SETTINGS 3
5050
static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116

static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_info *uinfo)
{
	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	uinfo->count = 1;
	uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
	if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
		uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
	strcpy(uinfo->value.enumerated.name,
			out_svm_set_enum_str[uinfo->value.enumerated.item]);
	return 0;
}

static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;

	ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
	return 0;
}

static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	int sel = ucontrol->value.enumerated.item[0];
	unsigned int items = NUM_OF_SVM_SETTINGS;
	unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
	unsigned int tmp;

	if (sel >= items)
		return 0;

	codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
		    sel, out_svm_set_enum_str[sel]);

	spec->smart_volume_setting = sel;

	switch (sel) {
	case 0:
		tmp = FLOAT_ZERO;
		break;
	case 1:
		tmp = FLOAT_ONE;
		break;
	case 2:
		tmp = FLOAT_TWO;
		break;
	default:
		tmp = FLOAT_ZERO;
		break;
	}
	/* Req 2 is the Smart Volume Setting req. */
	dspio_set_uint_param(codec, ca0132_effects[idx].mid,
			ca0132_effects[idx].reqs[2], tmp);
	return 1;
}

/* Sound Blaster Z EQ preset controls */
static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_info *uinfo)
{
5117
	unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145

	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	uinfo->count = 1;
	uinfo->value.enumerated.items = items;
	if (uinfo->value.enumerated.item >= items)
		uinfo->value.enumerated.item = items - 1;
	strcpy(uinfo->value.enumerated.name,
		ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
	return 0;
}

static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;

	ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
	return 0;
}

static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	int i, err = 0;
	int sel = ucontrol->value.enumerated.item[0];
5146
	unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170

	if (sel >= items)
		return 0;

	codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
			ca0132_alt_eq_presets[sel].name);
	/*
	 * Idx 0 is default.
	 * Default needs to qualify with CrystalVoice state.
	 */
	for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
		err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
				ca0132_alt_eq_enum.reqs[i],
				ca0132_alt_eq_presets[sel].vals[i]);
		if (err < 0)
			break;
	}

	if (err >= 0)
		spec->eq_preset_val = sel;

	return 1;
}

5171 5172 5173
static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_info *uinfo)
{
5174
	unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5175 5176 5177 5178 5179 5180 5181 5182 5183 5184

	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	uinfo->count = 1;
	uinfo->value.enumerated.items = items;
	if (uinfo->value.enumerated.item >= items)
		uinfo->value.enumerated.item = items - 1;
	strcpy(uinfo->value.enumerated.name,
	       ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
	return 0;
}
5185

5186
static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5187 5188 5189 5190 5191
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;

5192
	ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5193 5194 5195
	return 0;
}

5196
static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5197 5198 5199 5200
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
5201 5202
	int i, err = 0;
	int sel = ucontrol->value.enumerated.item[0];
5203

5204
	if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5205 5206
		return 0;

5207
	codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5208
		    sel, ca0132_voicefx_presets[sel].name);
5209

5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220
	/*
	 * Idx 0 is default.
	 * Default needs to qualify with CrystalVoice state.
	 */
	for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
		err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
				ca0132_voicefx.reqs[i],
				ca0132_voicefx_presets[sel].vals[i]);
		if (err < 0)
			break;
	}
5221

5222 5223 5224 5225 5226
	if (err >= 0) {
		spec->voicefx_val = sel;
		/* enable voice fx */
		ca0132_voicefx_set(codec, (sel ? 1 : 0));
	}
5227

5228
	return 1;
5229 5230
}

5231 5232
static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
5233 5234 5235
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
5236 5237
	hda_nid_t nid = get_amp_nid(kcontrol);
	int ch = get_amp_channels(kcontrol);
5238 5239
	long *valp = ucontrol->value.integer.value;

5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264
	/* vnode */
	if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
		if (ch & 1) {
			*valp = spec->vnode_lswitch[nid - VNODE_START_NID];
			valp++;
		}
		if (ch & 2) {
			*valp = spec->vnode_rswitch[nid - VNODE_START_NID];
			valp++;
		}
		return 0;
	}

	/* effects, include PE and CrystalVoice */
	if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
		*valp = spec->effects_switch[nid - EFFECT_START_NID];
		return 0;
	}

	/* mic boost */
	if (nid == spec->input_pins[0]) {
		*valp = spec->cur_mic_boost;
		return 0;
	}

5265 5266 5267
	return 0;
}

5268 5269
static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
			     struct snd_ctl_elem_value *ucontrol)
5270 5271 5272
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
5273 5274
	hda_nid_t nid = get_amp_nid(kcontrol);
	int ch = get_amp_channels(kcontrol);
5275
	long *valp = ucontrol->value.integer.value;
5276
	int changed = 1;
5277

5278
	codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5279
		    nid, *valp);
5280 5281

	snd_hda_power_up(codec);
5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294
	/* vnode */
	if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
		if (ch & 1) {
			spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
			valp++;
		}
		if (ch & 2) {
			spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
			valp++;
		}
		changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
		goto exit;
	}
5295

5296 5297 5298 5299
	/* PE */
	if (nid == PLAY_ENHANCEMENT) {
		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
		changed = ca0132_pe_switch_set(codec);
5300
		goto exit;
5301
	}
5302

5303 5304 5305 5306
	/* CrystalVoice */
	if (nid == CRYSTAL_VOICE) {
		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
		changed = ca0132_cvoice_switch_set(codec);
5307
		goto exit;
5308
	}
5309

5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320
	/* out and in effects */
	if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
	    ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
		changed = ca0132_effects_set(codec, nid, *valp);
		goto exit;
	}

	/* mic boost */
	if (nid == spec->input_pins[0]) {
		spec->cur_mic_boost = *valp;
5321 5322 5323 5324 5325 5326 5327 5328
		if (spec->use_alt_functions) {
			if (spec->in_enum_val != REAR_LINE_IN)
				changed = ca0132_mic_boost_set(codec, *valp);
		} else {
			/* Mic boost does not apply to Digital Mic */
			if (spec->cur_mic_type != DIGITAL_MIC)
				changed = ca0132_mic_boost_set(codec, *valp);
		}
5329 5330 5331

		goto exit;
	}
5332

5333
exit:
5334
	snd_hda_power_down(codec);
5335
	return changed;
5336 5337
}

5338 5339 5340
/*
 * Volume related
 */
5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375
/*
 * Sets the internal DSP decibel level to match the DAC for output, and the
 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
 * all alternative codecs set DSP playback volume.
 */
static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int dsp_dir;
	unsigned int lookup_val;

	if (nid == VNID_SPK)
		dsp_dir = DSP_VOL_OUT;
	else
		dsp_dir = DSP_VOL_IN;

	lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];

	dspio_set_uint_param(codec,
		ca0132_alt_vol_ctls[dsp_dir].mid,
		ca0132_alt_vol_ctls[dsp_dir].reqs[0],
		float_vol_db_lookup[lookup_val]);

	lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];

	dspio_set_uint_param(codec,
		ca0132_alt_vol_ctls[dsp_dir].mid,
		ca0132_alt_vol_ctls[dsp_dir].reqs[1],
		float_vol_db_lookup[lookup_val]);

	dspio_set_uint_param(codec,
		ca0132_alt_vol_ctls[dsp_dir].mid,
		ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
}

5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414
static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
			      struct snd_ctl_elem_info *uinfo)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	int ch = get_amp_channels(kcontrol);
	int dir = get_amp_direction(kcontrol);
	unsigned long pval;
	int err;

	switch (nid) {
	case VNID_SPK:
		/* follow shared_out info */
		nid = spec->shared_out_nid;
		mutex_lock(&codec->control_mutex);
		pval = kcontrol->private_value;
		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
		err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
		kcontrol->private_value = pval;
		mutex_unlock(&codec->control_mutex);
		break;
	case VNID_MIC:
		/* follow shared_mic info */
		nid = spec->shared_mic_nid;
		mutex_lock(&codec->control_mutex);
		pval = kcontrol->private_value;
		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
		err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
		kcontrol->private_value = pval;
		mutex_unlock(&codec->control_mutex);
		break;
	default:
		err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
	}
	return err;
}

static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5415 5416 5417 5418
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
5419 5420
	hda_nid_t nid = get_amp_nid(kcontrol);
	int ch = get_amp_channels(kcontrol);
5421 5422
	long *valp = ucontrol->value.integer.value;

5423 5424 5425 5426 5427 5428 5429 5430 5431
	/* store the left and right volume */
	if (ch & 1) {
		*valp = spec->vnode_lvol[nid - VNODE_START_NID];
		valp++;
	}
	if (ch & 2) {
		*valp = spec->vnode_rvol[nid - VNODE_START_NID];
		valp++;
	}
5432 5433 5434
	return 0;
}

5435
static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5436 5437 5438 5439
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
5440 5441
	hda_nid_t nid = get_amp_nid(kcontrol);
	int ch = get_amp_channels(kcontrol);
5442
	long *valp = ucontrol->value.integer.value;
5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455
	hda_nid_t shared_nid = 0;
	bool effective;
	int changed = 1;

	/* store the left and right volume */
	if (ch & 1) {
		spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
		valp++;
	}
	if (ch & 2) {
		spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
		valp++;
	}
5456

5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472
	/* if effective conditions, then update hw immediately. */
	effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
	if (effective) {
		int dir = get_amp_direction(kcontrol);
		unsigned long pval;

		snd_hda_power_up(codec);
		mutex_lock(&codec->control_mutex);
		pval = kcontrol->private_value;
		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
								0, dir);
		changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
		kcontrol->private_value = pval;
		mutex_unlock(&codec->control_mutex);
		snd_hda_power_down(codec);
	}
5473

5474
	return changed;
5475 5476
}

5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521
/*
 * This function is the same as the one above, because using an if statement
 * inside of the above volume control for the DSP volume would cause too much
 * lag. This is a lot more smooth.
 */
static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	int ch = get_amp_channels(kcontrol);
	long *valp = ucontrol->value.integer.value;
	hda_nid_t vnid = 0;
	int changed = 1;

	switch (nid) {
	case 0x02:
		vnid = VNID_SPK;
		break;
	case 0x07:
		vnid = VNID_MIC;
		break;
	}

	/* store the left and right volume */
	if (ch & 1) {
		spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
		valp++;
	}
	if (ch & 2) {
		spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
		valp++;
	}

	snd_hda_power_up(codec);
	ca0132_alt_dsp_volume_put(codec, vnid);
	mutex_lock(&codec->control_mutex);
	changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
	mutex_unlock(&codec->control_mutex);
	snd_hda_power_down(codec);

	return changed;
}

5522 5523
static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
			     unsigned int size, unsigned int __user *tlv)
5524
{
5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	struct ca0132_spec *spec = codec->spec;
	hda_nid_t nid = get_amp_nid(kcontrol);
	int ch = get_amp_channels(kcontrol);
	int dir = get_amp_direction(kcontrol);
	unsigned long pval;
	int err;

	switch (nid) {
	case VNID_SPK:
		/* follow shared_out tlv */
		nid = spec->shared_out_nid;
		mutex_lock(&codec->control_mutex);
		pval = kcontrol->private_value;
		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
		err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
		kcontrol->private_value = pval;
		mutex_unlock(&codec->control_mutex);
		break;
	case VNID_MIC:
		/* follow shared_mic tlv */
		nid = spec->shared_mic_nid;
		mutex_lock(&codec->control_mutex);
		pval = kcontrol->private_value;
		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
		err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
		kcontrol->private_value = pval;
		mutex_unlock(&codec->control_mutex);
		break;
	default:
		err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
	}
	return err;
5558 5559
}

5560 5561 5562 5563 5564 5565 5566 5567 5568
/* Add volume slider control for effect level */
static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
					const char *pfx, int dir)
{
	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
	int type = dir ? HDA_INPUT : HDA_OUTPUT;
	struct snd_kcontrol_new knew =
		HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);

5569
	sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
5570

5571
	knew.tlv.c = NULL;
5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595

	switch (nid) {
	case XBASS_XOVER:
		knew.info = ca0132_alt_xbass_xover_slider_info;
		knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
		knew.put = ca0132_alt_xbass_xover_slider_put;
		break;
	default:
		knew.info = ca0132_alt_effect_slider_info;
		knew.get = ca0132_alt_slider_ctl_get;
		knew.put = ca0132_alt_effect_slider_put;
		knew.private_value =
			HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
		break;
	}

	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
}

/*
 * Added FX: prefix for the alternative codecs, because otherwise the surround
 * effect would conflict with the Surround sound volume control. Also seems more
 * clear as to what the switches do. Left alone for others.
 */
5596 5597
static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
			 const char *pfx, int dir)
5598
{
5599
	struct ca0132_spec *spec = codec->spec;
5600
	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5601
	int type = dir ? HDA_INPUT : HDA_OUTPUT;
5602
	struct snd_kcontrol_new knew =
5603
		CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
5604 5605 5606 5607
	/* If using alt_controls, add FX: prefix. But, don't add FX:
	 * prefix to OutFX or InFX enable controls.
	 */
	if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5608
		sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5609 5610 5611
	else
		sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);

5612 5613 5614
	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
}

5615
static int add_voicefx(struct hda_codec *codec)
5616 5617
{
	struct snd_kcontrol_new knew =
5618 5619 5620 5621 5622 5623
		HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
				    VOICEFX, 1, 0, HDA_INPUT);
	knew.info = ca0132_voicefx_info;
	knew.get = ca0132_voicefx_get;
	knew.put = ca0132_voicefx_put;
	return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5624 5625
}

5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656
/* Create the EQ Preset control */
static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
{
	struct snd_kcontrol_new knew =
		HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
				    EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
	knew.info = ca0132_alt_eq_preset_info;
	knew.get = ca0132_alt_eq_preset_get;
	knew.put = ca0132_alt_eq_preset_put;
	return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
				snd_ctl_new1(&knew, codec));
}

/*
 * Add enumerated control for the three different settings of the smart volume
 * output effect. Normal just uses the slider value, and loud and night are
 * their own things that ignore that value.
 */
static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
{
	struct snd_kcontrol_new knew =
		HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
				    SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
	knew.info = ca0132_alt_svm_setting_info;
	knew.get = ca0132_alt_svm_setting_get;
	knew.put = ca0132_alt_svm_setting_put;
	return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
				snd_ctl_new1(&knew, codec));

}

5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689
/*
 * Create an Output Select enumerated control for codecs with surround
 * out capabilities.
 */
static int ca0132_alt_add_output_enum(struct hda_codec *codec)
{
	struct snd_kcontrol_new knew =
		HDA_CODEC_MUTE_MONO("Output Select",
				    OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
	knew.info = ca0132_alt_output_select_get_info;
	knew.get = ca0132_alt_output_select_get;
	knew.put = ca0132_alt_output_select_put;
	return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
				snd_ctl_new1(&knew, codec));
}

/*
 * Create an Input Source enumerated control for the alternate ca0132 codecs
 * because the front microphone has no auto-detect, and Line-in has to be set
 * somehow.
 */
static int ca0132_alt_add_input_enum(struct hda_codec *codec)
{
	struct snd_kcontrol_new knew =
		HDA_CODEC_MUTE_MONO("Input Source",
				    INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
	knew.info = ca0132_alt_input_source_info;
	knew.get = ca0132_alt_input_source_get;
	knew.put = ca0132_alt_input_source_put;
	return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
				snd_ctl_new1(&knew, codec));
}

5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719
/*
 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
 * more control than the original mic boost, which is either full 30dB or off.
 */
static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
{
	struct snd_kcontrol_new knew =
		HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
				    MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
	knew.info = ca0132_alt_mic_boost_info;
	knew.get = ca0132_alt_mic_boost_get;
	knew.put = ca0132_alt_mic_boost_put;
	return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
				snd_ctl_new1(&knew, codec));

}

/*
 * Need to create slave controls for the alternate codecs that have surround
 * capabilities.
 */
static const char * const ca0132_alt_slave_pfxs[] = {
	"Front", "Surround", "Center", "LFE", NULL,
};

/*
 * Also need special channel map, because the default one is incorrect.
 * I think this has to do with the pin for rear surround being 0x11,
 * and the center/lfe being 0x10. Usually the pin order is the opposite.
 */
5720
static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755
	{ .channels = 2,
	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
	{ .channels = 4,
	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
		   SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
	{ .channels = 6,
	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
		   SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
		   SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
	{ }
};

/* Add the correct chmap for streams with 6 channels. */
static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
{
	int err = 0;
	struct hda_pcm *pcm;

	list_for_each_entry(pcm, &codec->pcm_list_head, list) {
		struct hda_pcm_stream *hinfo =
			&pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
		struct snd_pcm_chmap *chmap;
		const struct snd_pcm_chmap_elem *elem;

		elem = ca0132_alt_chmaps;
		if (hinfo->channels_max == 6) {
			err = snd_pcm_add_chmap_ctls(pcm->pcm,
					SNDRV_PCM_STREAM_PLAYBACK,
					elem, hinfo->channels_max, 0, &chmap);
			if (err < 0)
				codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
		}
	}
}

5756 5757 5758 5759
/*
 * When changing Node IDs for Mixer Controls below, make sure to update
 * Node IDs in ca0132_config() as well.
 */
5760
static const struct snd_kcontrol_new ca0132_mixer[] = {
5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781
	CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
	CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
	CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
	HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
	HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
	CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
			       0x12, 1, HDA_INPUT),
	CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
			       VNID_HP_SEL, 1, HDA_OUTPUT),
	CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
			       VNID_AMIC1_SEL, 1, HDA_INPUT),
	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
			       VNID_HP_ASEL, 1, HDA_OUTPUT),
	CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
			       VNID_AMIC1_ASEL, 1, HDA_INPUT),
	{ } /* end */
};

5782
/*
5783 5784 5785
 * Desktop specific control mixer. Removes auto-detect for mic, and adds
 * surround controls. Also sets both the Front Playback and Capture Volume
 * controls to alt so they set the DSP's decibel level.
5786
 */
5787
static const struct snd_kcontrol_new desktop_mixer[] = {
5788 5789
	CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
	CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5790 5791 5792 5793 5794 5795
	HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
	HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
	HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
	HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
	HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
	HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808
	CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
				VNID_HP_ASEL, 1, HDA_OUTPUT),
	{ } /* end */
};

/*
 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
 * because it doesn't set decibel levels for the DSP for capture.
 */
5809
static const struct snd_kcontrol_new r3di_mixer[] = {
5810 5811
	CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
	CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5812 5813 5814 5815 5816 5817
	HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
	HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
	HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
	HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
	HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
	HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5818 5819 5820 5821 5822 5823 5824 5825 5826
	CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
				VNID_HP_ASEL, 1, HDA_OUTPUT),
	{ } /* end */
};

5827 5828 5829
static int ca0132_build_controls(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
5830
	int i, num_fx, num_sliders;
5831 5832 5833 5834 5835 5836 5837 5838
	int err = 0;

	/* Add Mixer controls */
	for (i = 0; i < spec->num_mixers; i++) {
		err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
		if (err < 0)
			return err;
	}
5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851
	/* Setup vmaster with surround slaves for desktop ca0132 devices */
	if (spec->use_alt_functions) {
		snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
					spec->tlv);
		snd_hda_add_vmaster(codec, "Master Playback Volume",
					spec->tlv, ca0132_alt_slave_pfxs,
					"Playback Volume");
		err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
					    NULL, ca0132_alt_slave_pfxs,
					    "Playback Switch",
					    true, &spec->vmaster_mute.sw_kctl);

	}
5852 5853 5854 5855 5856 5857

	/* Add in and out effects controls.
	 * VoiceFX, PE and CrystalVoice are added separately.
	 */
	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
	for (i = 0; i < num_fx; i++) {
5858 5859
		/* SBZ and R3D break if Echo Cancellation is used. */
		if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
5860 5861 5862 5863 5864
			if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
						OUT_EFFECTS_COUNT))
				continue;
		}

5865 5866 5867 5868 5869 5870
		err = add_fx_switch(codec, ca0132_effects[i].nid,
				    ca0132_effects[i].name,
				    ca0132_effects[i].direct);
		if (err < 0)
			return err;
	}
5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882
	/*
	 * If codec has use_alt_controls set to true, add effect level sliders,
	 * EQ presets, and Smart Volume presets. Also, change names to add FX
	 * prefix, and change PlayEnhancement and CrystalVoice to match.
	 */
	if (spec->use_alt_controls) {
		ca0132_alt_add_svm_enum(codec);
		add_ca0132_alt_eq_presets(codec);
		err = add_fx_switch(codec, PLAY_ENHANCEMENT,
					"Enable OutFX", 0);
		if (err < 0)
			return err;
5883

5884 5885 5886 5887
		err = add_fx_switch(codec, CRYSTAL_VOICE,
					"Enable InFX", 1);
		if (err < 0)
			return err;
5888

5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908
		num_sliders = OUT_EFFECTS_COUNT - 1;
		for (i = 0; i < num_sliders; i++) {
			err = ca0132_alt_add_effect_slider(codec,
					    ca0132_effects[i].nid,
					    ca0132_effects[i].name,
					    ca0132_effects[i].direct);
			if (err < 0)
				return err;
		}

		err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
					"X-Bass Crossover", EFX_DIR_OUT);

		if (err < 0)
			return err;
	} else {
		err = add_fx_switch(codec, PLAY_ENHANCEMENT,
					"PlayEnhancement", 0);
		if (err < 0)
			return err;
5909

5910 5911 5912 5913 5914
		err = add_fx_switch(codec, CRYSTAL_VOICE,
					"CrystalVoice", 1);
		if (err < 0)
			return err;
	}
5915 5916
	add_voicefx(codec);

5917 5918 5919 5920 5921 5922 5923 5924
	/*
	 * If the codec uses alt_functions, you need the enumerated controls
	 * to select the new outputs and inputs, plus add the new mic boost
	 * setting control.
	 */
	if (spec->use_alt_functions) {
		ca0132_alt_add_output_enum(codec);
		ca0132_alt_add_input_enum(codec);
5925
		ca0132_alt_add_mic_boost_enum(codec);
5926
	}
5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950
#ifdef ENABLE_TUNING_CONTROLS
	add_tuning_ctls(codec);
#endif

	err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
	if (err < 0)
		return err;

	if (spec->dig_out) {
		err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
						    spec->dig_out);
		if (err < 0)
			return err;
		err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
		if (err < 0)
			return err;
		/* spec->multiout.share_spdif = 1; */
	}

	if (spec->dig_in) {
		err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
		if (err < 0)
			return err;
	}
5951 5952 5953 5954

	if (spec->use_alt_functions)
		ca0132_alt_add_chmap_ctls(codec);

5955 5956 5957
	return 0;
}

5958
/*
5959
 * PCM
5960
 */
5961
static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
5962 5963
	.substreams = 1,
	.channels_min = 2,
5964
	.channels_max = 6,
5965 5966
	.ops = {
		.prepare = ca0132_playback_pcm_prepare,
5967 5968
		.cleanup = ca0132_playback_pcm_cleanup,
		.get_delay = ca0132_playback_pcm_delay,
5969 5970 5971
	},
};

5972
static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
5973 5974 5975
	.substreams = 1,
	.channels_min = 2,
	.channels_max = 2,
5976 5977
	.ops = {
		.prepare = ca0132_capture_pcm_prepare,
5978 5979
		.cleanup = ca0132_capture_pcm_cleanup,
		.get_delay = ca0132_capture_pcm_delay,
5980
	},
5981 5982
};

5983
static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994
	.substreams = 1,
	.channels_min = 2,
	.channels_max = 2,
	.ops = {
		.open = ca0132_dig_playback_pcm_open,
		.close = ca0132_dig_playback_pcm_close,
		.prepare = ca0132_dig_playback_pcm_prepare,
		.cleanup = ca0132_dig_playback_pcm_cleanup
	},
};

5995
static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
5996 5997 5998 5999 6000 6001
	.substreams = 1,
	.channels_min = 2,
	.channels_max = 2,
};

static int ca0132_build_pcms(struct hda_codec *codec)
6002 6003
{
	struct ca0132_spec *spec = codec->spec;
6004
	struct hda_pcm *info;
6005

6006 6007 6008
	info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
	if (!info)
		return -ENOMEM;
6009 6010 6011 6012 6013
	if (spec->use_alt_functions) {
		info->own_chmap = true;
		info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
			= ca0132_alt_chmaps;
	}
6014 6015 6016 6017 6018
	info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
	info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
	info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
		spec->multiout.max_channels;
	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6019
	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6020 6021
	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];

6022
	/* With the DSP enabled, desktops don't use this ADC. */
6023
	if (!spec->use_alt_functions) {
6024 6025 6026 6027 6028 6029 6030 6031
		info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
		if (!info)
			return -ENOMEM;
		info->stream[SNDRV_PCM_STREAM_CAPTURE] =
			ca0132_pcm_analog_capture;
		info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
		info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
	}
6032

6033 6034 6035
	info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
	if (!info)
		return -ENOMEM;
6036 6037 6038 6039
	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];

6040 6041 6042
	if (!spec->dig_out && !spec->dig_in)
		return 0;

6043 6044 6045
	info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
	if (!info)
		return -ENOMEM;
6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056
	info->pcm_type = HDA_PCM_TYPE_SPDIF;
	if (spec->dig_out) {
		info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
			ca0132_pcm_digital_playback;
		info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
	}
	if (spec->dig_in) {
		info->stream[SNDRV_PCM_STREAM_CAPTURE] =
			ca0132_pcm_digital_capture;
		info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
	}
6057

6058
	return 0;
6059 6060
}

6061 6062 6063
static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
{
	if (pin) {
6064
		snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077
		if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
			snd_hda_codec_write(codec, pin, 0,
					    AC_VERB_SET_AMP_GAIN_MUTE,
					    AMP_OUT_UNMUTE);
	}
	if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
		snd_hda_codec_write(codec, dac, 0,
				    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
}

static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
{
	if (pin) {
6078
		snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095
		if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
			snd_hda_codec_write(codec, pin, 0,
					    AC_VERB_SET_AMP_GAIN_MUTE,
					    AMP_IN_UNMUTE(0));
	}
	if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
		snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
				    AMP_IN_UNMUTE(0));

		/* init to 0 dB and unmute. */
		snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
					 HDA_AMP_VOLMASK, 0x5a);
		snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
					 HDA_AMP_MUTE, 0);
	}
}

6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114
static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
{
	unsigned int caps;

	caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
				  AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
	snd_hda_override_amp_caps(codec, nid, dir, caps);
}

/*
 * Switch between Digital built-in mic and analog mic.
 */
static void ca0132_set_dmic(struct hda_codec *codec, int enable)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int tmp;
	u8 val;
	unsigned int oldval;

6115
	codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186

	oldval = stop_mic1(codec);
	ca0132_set_vipsource(codec, 0);
	if (enable) {
		/* set DMic input as 2-ch */
		tmp = FLOAT_TWO;
		dspio_set_uint_param(codec, 0x80, 0x00, tmp);

		val = spec->dmic_ctl;
		val |= 0x80;
		snd_hda_codec_write(codec, spec->input_pins[0], 0,
				    VENDOR_CHIPIO_DMIC_CTL_SET, val);

		if (!(spec->dmic_ctl & 0x20))
			chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
	} else {
		/* set AMic input as mono */
		tmp = FLOAT_ONE;
		dspio_set_uint_param(codec, 0x80, 0x00, tmp);

		val = spec->dmic_ctl;
		/* clear bit7 and bit5 to disable dmic */
		val &= 0x5f;
		snd_hda_codec_write(codec, spec->input_pins[0], 0,
				    VENDOR_CHIPIO_DMIC_CTL_SET, val);

		if (!(spec->dmic_ctl & 0x20))
			chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
	}
	ca0132_set_vipsource(codec, 1);
	resume_mic1(codec, oldval);
}

/*
 * Initialization for Digital Mic.
 */
static void ca0132_init_dmic(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	u8 val;

	/* Setup Digital Mic here, but don't enable.
	 * Enable based on jack detect.
	 */

	/* MCLK uses MPIO1, set to enable.
	 * Bit 2-0: MPIO select
	 * Bit   3: set to disable
	 * Bit 7-4: reserved
	 */
	val = 0x01;
	snd_hda_codec_write(codec, spec->input_pins[0], 0,
			    VENDOR_CHIPIO_DMIC_MCLK_SET, val);

	/* Data1 uses MPIO3. Data2 not use
	 * Bit 2-0: Data1 MPIO select
	 * Bit   3: set disable Data1
	 * Bit 6-4: Data2 MPIO select
	 * Bit   7: set disable Data2
	 */
	val = 0x83;
	snd_hda_codec_write(codec, spec->input_pins[0], 0,
			    VENDOR_CHIPIO_DMIC_PIN_SET, val);

	/* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
	 * Bit 3-0: Channel mask
	 * Bit   4: set for 48KHz, clear for 32KHz
	 * Bit   5: mode
	 * Bit   6: set to select Data2, clear for Data1
	 * Bit   7: set to enable DMic, clear for AMic
	 */
6187 6188 6189 6190
	if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
		val = 0x33;
	else
		val = 0x23;
6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224
	/* keep a copy of dmic ctl val for enable/disable dmic purpuse */
	spec->dmic_ctl = val;
	snd_hda_codec_write(codec, spec->input_pins[0], 0,
			    VENDOR_CHIPIO_DMIC_CTL_SET, val);
}

/*
 * Initialization for Analog Mic 2
 */
static void ca0132_init_analog_mic2(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	mutex_lock(&spec->chipio_mutex);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
	mutex_unlock(&spec->chipio_mutex);
}

static void ca0132_refresh_widget_caps(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	int i;

6225
	codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6226
	snd_hda_codec_update_widgets(codec);
6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239

	for (i = 0; i < spec->multiout.num_dacs; i++)
		refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);

	for (i = 0; i < spec->num_outputs; i++)
		refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);

	for (i = 0; i < spec->num_inputs; i++) {
		refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
		refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
	}
}

6240
/*
6241
 * Recon3D r3d_setup_defaults sub functions.
6242 6243
 */

6244
static void r3d_dsp_scp_startup(struct hda_codec *codec)
6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256 6257 6258 6259 6260 6261 6262 6263 6264
{
	unsigned int tmp;

	tmp = 0x00000000;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);

	tmp = 0x00000001;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);

	tmp = 0x00000004;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);

	tmp = 0x00000005;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);

	tmp = 0x00000000;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);

}

6265
static void r3d_dsp_initial_mic_setup(struct hda_codec *codec)
6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284
{
	unsigned int tmp;

	/* Mic 1 Setup */
	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
	/* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
	tmp = FLOAT_ONE;
	dspio_set_uint_param(codec, 0x80, 0x00, tmp);

	/* Mic 2 Setup, even though it isn't connected on SBZ */
	chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
	tmp = FLOAT_ZERO;
	dspio_set_uint_param(codec, 0x80, 0x01, tmp);
}

6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381
/*
 * Initialize Sound Blaster Z analog microphones.
 */
static void sbz_init_analog_mics(struct hda_codec *codec)
{
	unsigned int tmp;

	/* Mic 1 Setup */
	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
	tmp = FLOAT_THREE;
	dspio_set_uint_param(codec, 0x80, 0x00, tmp);

	/* Mic 2 Setup, even though it isn't connected on SBZ */
	chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
	tmp = FLOAT_ZERO;
	dspio_set_uint_param(codec, 0x80, 0x01, tmp);

}

/*
 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
 * having an updated DAC, which changes the destination to that DAC.
 */
static void sbz_connect_streams(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	mutex_lock(&spec->chipio_mutex);

	codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");

	chipio_set_stream_channels(codec, 0x0C, 6);
	chipio_set_stream_control(codec, 0x0C, 1);

	/* This value is 0x43 for 96khz, and 0x83 for 192khz. */
	chipio_write_no_mutex(codec, 0x18a020, 0x00000043);

	/* Setup stream 0x14 with it's source and destination points */
	chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
	chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
	chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
	chipio_set_stream_channels(codec, 0x14, 2);
	chipio_set_stream_control(codec, 0x14, 1);

	codec_dbg(codec, "Connect Streams exited, mutex released.\n");

	mutex_unlock(&spec->chipio_mutex);

}

/*
 * Write data through ChipIO to setup proper stream destinations.
 * Not sure how it exactly works, but it seems to direct data
 * to different destinations. Example is f8 to c0, e0 to c0.
 * All I know is, if you don't set these, you get no sound.
 */
static void sbz_chipio_startup_data(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	mutex_lock(&spec->chipio_mutex);
	codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");

	/* These control audio output */
	chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
	chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
	chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
	chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
	/* Signal to update I think */
	chipio_write_no_mutex(codec, 0x19042c, 0x00000001);

	chipio_set_stream_channels(codec, 0x0C, 6);
	chipio_set_stream_control(codec, 0x0C, 1);
	/* No clue what these control */
	chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
	chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
	chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
	chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
	chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
	chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
	chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
	chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
	chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
	chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
	chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
	chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);

	chipio_write_no_mutex(codec, 0x19042c, 0x00000001);

	codec_dbg(codec, "Startup Data exited, mutex released.\n");
	mutex_unlock(&spec->chipio_mutex);
}

6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409
/*
 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
 * without a 0x20 source like normal.
 */
static void sbz_dsp_scp_startup(struct hda_codec *codec)
{
	unsigned int tmp;

	tmp = 0x00000003;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);

	tmp = 0x00000000;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);

	tmp = 0x00000001;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);

	tmp = 0x00000004;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);

	tmp = 0x00000005;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);

	tmp = 0x00000000;
	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);

}

6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429
static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
{
	unsigned int tmp;

	chipio_set_stream_control(codec, 0x03, 0);
	chipio_set_stream_control(codec, 0x04, 0);

	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);

	tmp = FLOAT_THREE;
	dspio_set_uint_param(codec, 0x80, 0x00, tmp);

	chipio_set_stream_control(codec, 0x03, 1);
	chipio_set_stream_control(codec, 0x04, 1);

	chipio_write(codec, 0x18b098, 0x0000000c);
	chipio_write(codec, 0x18b09C, 0x0000000c);
}

6430 6431 6432 6433 6434
/*
 * Setup default parameters for DSP
 */
static void ca0132_setup_defaults(struct hda_codec *codec)
{
6435
	struct ca0132_spec *spec = codec->spec;
6436 6437 6438 6439
	unsigned int tmp;
	int num_fx;
	int idx, i;

6440
	if (spec->dsp_state != DSP_DOWNLOADED)
6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473
		return;

	/* out, in effects + voicefx */
	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
	for (idx = 0; idx < num_fx; idx++) {
		for (i = 0; i <= ca0132_effects[idx].params; i++) {
			dspio_set_uint_param(codec, ca0132_effects[idx].mid,
					     ca0132_effects[idx].reqs[i],
					     ca0132_effects[idx].def_vals[i]);
		}
	}

	/*remove DSP headroom*/
	tmp = FLOAT_ZERO;
	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);

	/*set speaker EQ bypass attenuation*/
	dspio_set_uint_param(codec, 0x8f, 0x01, tmp);

	/* set AMic1 and AMic2 as mono mic */
	tmp = FLOAT_ONE;
	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
	dspio_set_uint_param(codec, 0x80, 0x01, tmp);

	/* set AMic1 as CrystalVoice input */
	tmp = FLOAT_ONE;
	dspio_set_uint_param(codec, 0x80, 0x05, tmp);

	/* set WUH source */
	tmp = FLOAT_TWO;
	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
}

6474
/*
6475
 * Setup default parameters for Recon3D/Recon3Di DSP.
6476 6477
 */

6478
static void r3d_setup_defaults(struct hda_codec *codec)
6479 6480 6481 6482 6483 6484 6485 6486 6487
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int tmp;
	int num_fx;
	int idx, i;

	if (spec->dsp_state != DSP_DOWNLOADED)
		return;

6488
	r3d_dsp_scp_startup(codec);
6489

6490
	r3d_dsp_initial_mic_setup(codec);
6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503

	/*remove DSP headroom*/
	tmp = FLOAT_ZERO;
	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);

	/* set WUH source */
	tmp = FLOAT_TWO;
	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);

	/* Set speaker source? */
	dspio_set_uint_param(codec, 0x32, 0x00, tmp);

6504 6505
	if (spec->quirk == QUIRK_R3DI)
		r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518

	/* Setup effect defaults */
	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
	for (idx = 0; idx < num_fx; idx++) {
		for (i = 0; i <= ca0132_effects[idx].params; i++) {
			dspio_set_uint_param(codec,
					ca0132_effects[idx].mid,
					ca0132_effects[idx].reqs[i],
					ca0132_effects[idx].def_vals[i]);
		}
	}
}

6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532
/*
 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
 * than the Chromebook setup.
 */
static void sbz_setup_defaults(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int tmp, stream_format;
	int num_fx;
	int idx, i;

	if (spec->dsp_state != DSP_DOWNLOADED)
		return;

6533
	sbz_dsp_scp_startup(codec);
6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596

	sbz_init_analog_mics(codec);

	sbz_connect_streams(codec);

	sbz_chipio_startup_data(codec);

	chipio_set_stream_control(codec, 0x03, 1);
	chipio_set_stream_control(codec, 0x04, 1);

	/*
	 * Sets internal input loopback to off, used to have a switch to
	 * enable input loopback, but turned out to be way too buggy.
	 */
	tmp = FLOAT_ONE;
	dspio_set_uint_param(codec, 0x37, 0x08, tmp);
	dspio_set_uint_param(codec, 0x37, 0x10, tmp);

	/*remove DSP headroom*/
	tmp = FLOAT_ZERO;
	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);

	/* set WUH source */
	tmp = FLOAT_TWO;
	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);

	/* Set speaker source? */
	dspio_set_uint_param(codec, 0x32, 0x00, tmp);

	sbz_dsp_initial_mic_setup(codec);


	/* out, in effects + voicefx */
	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
	for (idx = 0; idx < num_fx; idx++) {
		for (i = 0; i <= ca0132_effects[idx].params; i++) {
			dspio_set_uint_param(codec,
					ca0132_effects[idx].mid,
					ca0132_effects[idx].reqs[i],
					ca0132_effects[idx].def_vals[i]);
		}
	}

	/*
	 * Have to make a stream to bind the sound output to, otherwise
	 * you'll get dead audio. Before I did this, it would bind to an
	 * audio input, and would never work
	 */
	stream_format = snd_hdac_calc_stream_format(48000, 2,
			SNDRV_PCM_FORMAT_S32_LE, 32, 0);

	snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
					0, stream_format);

	snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);

	snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
					0, stream_format);

	snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
}

6597 6598 6599 6600 6601
/*
 * Initialization of flags in chip
 */
static void ca0132_init_flags(struct hda_codec *codec)
{
6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627
	struct ca0132_spec *spec = codec->spec;

	if (spec->use_alt_functions) {
		chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
		chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
		chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
		chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
		chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
		chipio_set_control_flag(codec,
				CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
		chipio_set_control_flag(codec,
				CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
	} else {
		chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
		chipio_set_control_flag(codec,
				CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
		chipio_set_control_flag(codec,
				CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
		chipio_set_control_flag(codec,
				CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
		chipio_set_control_flag(codec,
				CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
	}
6628 6629 6630 6631 6632 6633 6634
}

/*
 * Initialization of parameters in chip
 */
static void ca0132_init_params(struct hda_codec *codec)
{
6635 6636 6637 6638 6639 6640 6641 6642 6643 6644
	struct ca0132_spec *spec = codec->spec;

	if (spec->use_alt_functions) {
		chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
		chipio_set_conn_rate(codec, 0x0B, SR_48_000);
		chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
		chipio_set_control_param(codec, 0, 0);
		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
	}

6645 6646 6647
	chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
	chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
}
6648

6649 6650 6651 6652 6653 6654 6655 6656 6657
static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
{
	chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
	chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
	chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
	chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
	chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
	chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);

6658 6659
	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6660 6661 6662 6663 6664 6665
	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
}

static bool ca0132_download_dsp_images(struct hda_codec *codec)
{
	bool dsp_loaded = false;
6666
	struct ca0132_spec *spec = codec->spec;
6667
	const struct dsp_image_seg *dsp_os_image;
6668
	const struct firmware *fw_entry;
6669 6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708
	/*
	 * Alternate firmwares for different variants. The Recon3Di apparently
	 * can use the default firmware, but I'll leave the option in case
	 * it needs it again.
	 */
	switch (spec->quirk) {
	case QUIRK_SBZ:
		if (request_firmware(&fw_entry, SBZ_EFX_FILE,
					codec->card->dev) != 0) {
			codec_dbg(codec, "SBZ alt firmware not detected. ");
			spec->alt_firmware_present = false;
		} else {
			codec_dbg(codec, "Sound Blaster Z firmware selected.");
			spec->alt_firmware_present = true;
		}
		break;
	case QUIRK_R3DI:
		if (request_firmware(&fw_entry, R3DI_EFX_FILE,
					codec->card->dev) != 0) {
			codec_dbg(codec, "Recon3Di alt firmware not detected.");
			spec->alt_firmware_present = false;
		} else {
			codec_dbg(codec, "Recon3Di firmware selected.");
			spec->alt_firmware_present = true;
		}
		break;
	default:
		spec->alt_firmware_present = false;
		break;
	}
	/*
	 * Use default ctefx.bin if no alt firmware is detected, or if none
	 * exists for your particular codec.
	 */
	if (!spec->alt_firmware_present) {
		codec_dbg(codec, "Default firmware selected.");
		if (request_firmware(&fw_entry, EFX_FILE,
					codec->card->dev) != 0)
			return false;
	}
6709

6710
	dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
6711
	if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
6712
		codec_err(codec, "ca0132 DSP load image failed\n");
6713 6714 6715
		goto exit_download;
	}

6716 6717
	dsp_loaded = dspload_wait_loaded(codec);

6718
exit_download:
6719 6720
	release_firmware(fw_entry);

6721 6722 6723 6724 6725 6726 6727
	return dsp_loaded;
}

static void ca0132_download_dsp(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

6728 6729 6730
#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
	return; /* NOP */
#endif
6731

6732 6733 6734
	if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
		return; /* don't retry failures */

6735
	chipio_enable_clocks(codec);
6736 6737 6738 6739 6740 6741 6742 6743
	if (spec->dsp_state != DSP_DOWNLOADED) {
		spec->dsp_state = DSP_DOWNLOADING;

		if (!ca0132_download_dsp_images(codec))
			spec->dsp_state = DSP_DOWNLOAD_FAILED;
		else
			spec->dsp_state = DSP_DOWNLOADED;
	}
6744

6745 6746
	/* For codecs using alt functions, this is already done earlier */
	if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
6747 6748 6749
		ca0132_set_dsp_msr(codec, true);
}

6750 6751
static void ca0132_process_dsp_response(struct hda_codec *codec,
					struct hda_jack_callback *callback)
6752 6753 6754
{
	struct ca0132_spec *spec = codec->spec;

6755
	codec_dbg(codec, "ca0132_process_dsp_response\n");
6756 6757 6758 6759 6760 6761 6762 6763
	if (spec->wait_scp) {
		if (dspio_get_response_data(codec) >= 0)
			spec->wait_scp = 0;
	}

	dspio_clear_response_queue(codec);
}

6764
static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6765
{
6766
	struct ca0132_spec *spec = codec->spec;
6767
	struct hda_jack_tbl *tbl;
6768

6769 6770 6771 6772
	/* Delay enabling the HP amp, to let the mic-detection
	 * state machine run.
	 */
	cancel_delayed_work_sync(&spec->unsol_hp_work);
6773
	schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
6774 6775 6776
	tbl = snd_hda_jack_tbl_get(codec, cb->nid);
	if (tbl)
		tbl->block_report = 1;
6777 6778 6779 6780
}

static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
{
6781 6782 6783 6784 6785 6786
	struct ca0132_spec *spec = codec->spec;

	if (spec->use_alt_functions)
		ca0132_alt_select_in(codec);
	else
		ca0132_select_mic(codec);
6787 6788 6789 6790
}

static void ca0132_init_unsol(struct hda_codec *codec)
{
6791 6792 6793
	struct ca0132_spec *spec = codec->spec;
	snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
	snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
6794 6795 6796
					    amic_callback);
	snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
					    ca0132_process_dsp_response);
6797
	/* Front headphone jack detection */
6798
	if (spec->use_alt_functions)
6799 6800
		snd_hda_jack_detect_enable_callback(codec,
			spec->unsol_tag_front_hp, hp_callback);
6801 6802
}

6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819 6820 6821 6822
/*
 * Verbs tables.
 */

/* Sends before DSP download. */
static struct hda_verb ca0132_base_init_verbs[] = {
	/*enable ct extension*/
	{0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
	{}
};

/* Send at exit. */
static struct hda_verb ca0132_base_exit_verbs[] = {
	/*set afg to D3*/
	{0x01, AC_VERB_SET_POWER_STATE, 0x03},
	/*disable ct extension*/
	{0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
	{}
};

6823
/* Other verbs tables. Sends after DSP download. */
6824

6825 6826 6827 6828 6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841 6842 6843 6844 6845 6846 6847 6848 6849 6850 6851 6852 6853
static struct hda_verb ca0132_init_verbs0[] = {
	/* chip init verbs */
	{0x15, 0x70D, 0xF0},
	{0x15, 0x70E, 0xFE},
	{0x15, 0x707, 0x75},
	{0x15, 0x707, 0xD3},
	{0x15, 0x707, 0x09},
	{0x15, 0x707, 0x53},
	{0x15, 0x707, 0xD4},
	{0x15, 0x707, 0xEF},
	{0x15, 0x707, 0x75},
	{0x15, 0x707, 0xD3},
	{0x15, 0x707, 0x09},
	{0x15, 0x707, 0x02},
	{0x15, 0x707, 0x37},
	{0x15, 0x707, 0x78},
	{0x15, 0x53C, 0xCE},
	{0x15, 0x575, 0xC9},
	{0x15, 0x53D, 0xCE},
	{0x15, 0x5B7, 0xC9},
	{0x15, 0x70D, 0xE8},
	{0x15, 0x70E, 0xFE},
	{0x15, 0x707, 0x02},
	{0x15, 0x707, 0x68},
	{0x15, 0x707, 0x62},
	{0x15, 0x53A, 0xCE},
	{0x15, 0x546, 0xC9},
	{0x15, 0x53B, 0xCE},
	{0x15, 0x5E8, 0xC9},
6854 6855 6856
	{}
};

6857 6858
/* Extra init verbs for desktop cards. */
static struct hda_verb ca0132_init_verbs1[] = {
6859 6860 6861 6862 6863 6864 6865 6866 6867 6868 6869 6870 6871 6872 6873 6874
	{0x15, 0x70D, 0x20},
	{0x15, 0x70E, 0x19},
	{0x15, 0x707, 0x00},
	{0x15, 0x539, 0xCE},
	{0x15, 0x546, 0xC9},
	{0x15, 0x70D, 0xB7},
	{0x15, 0x70E, 0x09},
	{0x15, 0x707, 0x10},
	{0x15, 0x70D, 0xAF},
	{0x15, 0x70E, 0x09},
	{0x15, 0x707, 0x01},
	{0x15, 0x707, 0x05},
	{0x15, 0x70D, 0x73},
	{0x15, 0x70E, 0x09},
	{0x15, 0x707, 0x14},
	{0x15, 0x6FF, 0xC4},
6875 6876 6877
	{}
};

6878 6879 6880
static void ca0132_init_chip(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
6881 6882 6883
	int num_fx;
	int i;
	unsigned int on;
6884 6885

	mutex_init(&spec->chipio_mutex);
6886 6887

	spec->cur_out_type = SPEAKER_OUT;
6888 6889 6890 6891 6892
	if (!spec->use_alt_functions)
		spec->cur_mic_type = DIGITAL_MIC;
	else
		spec->cur_mic_type = REAR_MIC;

6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906 6907 6908 6909
	spec->cur_mic_boost = 0;

	for (i = 0; i < VNODES_COUNT; i++) {
		spec->vnode_lvol[i] = 0x5a;
		spec->vnode_rvol[i] = 0x5a;
		spec->vnode_lswitch[i] = 0;
		spec->vnode_rswitch[i] = 0;
	}

	/*
	 * Default states for effects are in ca0132_effects[].
	 */
	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
	for (i = 0; i < num_fx; i++) {
		on = (unsigned int)ca0132_effects[i].reqs[0];
		spec->effects_switch[i] = on ? 1 : 0;
	}
6910 6911 6912 6913 6914 6915 6916 6917 6918
	/*
	 * Sets defaults for the effect slider controls, only for alternative
	 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
	 */
	if (spec->use_alt_controls) {
		spec->xbass_xover_freq = 8;
		for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
			spec->fx_ctl_val[i] = effect_slider_defaults[i];
	}
6919 6920 6921 6922 6923

	spec->voicefx_val = 0;
	spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
	spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;

6924 6925 6926
#ifdef ENABLE_TUNING_CONTROLS
	ca0132_init_tuning_defaults(codec);
#endif
6927 6928
}

6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949
/*
 * Recon3Di exit specific commands.
 */
/* prevents popping noise on shutdown */
static void r3di_gpio_shutdown(struct hda_codec *codec)
{
	snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
}

/*
 * Sound Blaster Z exit specific commands.
 */
static void sbz_region2_exit(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int i;

	for (i = 0; i < 4; i++)
		writeb(0x0, spec->mem_base + 0x100);
	for (i = 0; i < 8; i++)
		writeb(0xb3, spec->mem_base + 0x304);
6950 6951 6952 6953 6954 6955

	ca0132_mmio_gpio_set(codec, 0, false);
	ca0132_mmio_gpio_set(codec, 1, false);
	ca0132_mmio_gpio_set(codec, 4, true);
	ca0132_mmio_gpio_set(codec, 5, false);
	ca0132_mmio_gpio_set(codec, 7, false);
6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970
}

static void sbz_set_pin_ctl_default(struct hda_codec *codec)
{
	hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
	unsigned int i;

	snd_hda_codec_write(codec, 0x11, 0,
			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);

	for (i = 0; i < 5; i++)
		snd_hda_codec_write(codec, pins[i], 0,
				AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
}

6971
static void ca0132_clear_unsolicited(struct hda_codec *codec)
6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984 6985 6986 6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997 6998 6999
{
	hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
	unsigned int i;

	for (i = 0; i < 7; i++) {
		snd_hda_codec_write(codec, pins[i], 0,
				AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
	}
}

/* On shutdown, sends commands in sets of three */
static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
							int mask, int data)
{
	if (dir >= 0)
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_DIRECTION, dir);
	if (mask >= 0)
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_MASK, mask);

	if (data >= 0)
		snd_hda_codec_write(codec, 0x01, 0,
				AC_VERB_SET_GPIO_DATA, data);
}

static void sbz_exit_chip(struct hda_codec *codec)
{
7000 7001
	chipio_set_stream_control(codec, 0x03, 0);
	chipio_set_stream_control(codec, 0x04, 0);
7002 7003 7004 7005 7006 7007

	/* Mess with GPIO */
	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);

7008 7009
	chipio_set_stream_control(codec, 0x14, 0);
	chipio_set_stream_control(codec, 0x0C, 0);
7010 7011 7012 7013 7014 7015 7016 7017 7018 7019

	chipio_set_conn_rate(codec, 0x41, SR_192_000);
	chipio_set_conn_rate(codec, 0x91, SR_192_000);

	chipio_write(codec, 0x18a020, 0x00000083);

	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);

7020
	chipio_set_stream_control(codec, 0x0C, 0);
7021 7022 7023

	chipio_set_control_param(codec, 0x0D, 0x24);

7024
	ca0132_clear_unsolicited(codec);
7025 7026 7027 7028 7029 7030 7031 7032
	sbz_set_pin_ctl_default(codec);

	snd_hda_codec_write(codec, 0x0B, 0,
		AC_VERB_SET_EAPD_BTLENABLE, 0x00);

	sbz_region2_exit(codec);
}

7033 7034 7035 7036 7037 7038 7039
static void r3d_exit_chip(struct hda_codec *codec)
{
	ca0132_clear_unsolicited(codec);
	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
}

7040 7041 7042
static void ca0132_exit_chip(struct hda_codec *codec)
{
	/* put any chip cleanup stuffs here. */
7043 7044 7045

	if (dspload_is_loaded(codec))
		dsp_reset(codec);
7046 7047
}

7048 7049 7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070 7071 7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083 7084 7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112
/*
 * This fixes a problem that was hard to reproduce. Very rarely, I would
 * boot up, and there would be no sound, but the DSP indicated it had loaded
 * properly. I did a few memory dumps to see if anything was different, and
 * there were a few areas of memory uninitialized with a1a2a3a4. This function
 * checks if those areas are uninitialized, and if they are, it'll attempt to
 * reload the card 3 times. Usually it fixes by the second.
 */
static void sbz_dsp_startup_check(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	unsigned int dsp_data_check[4];
	unsigned int cur_address = 0x390;
	unsigned int i;
	unsigned int failure = 0;
	unsigned int reload = 3;

	if (spec->startup_check_entered)
		return;

	spec->startup_check_entered = true;

	for (i = 0; i < 4; i++) {
		chipio_read(codec, cur_address, &dsp_data_check[i]);
		cur_address += 0x4;
	}
	for (i = 0; i < 4; i++) {
		if (dsp_data_check[i] == 0xa1a2a3a4)
			failure = 1;
	}

	codec_dbg(codec, "Startup Check: %d ", failure);
	if (failure)
		codec_info(codec, "DSP not initialized properly. Attempting to fix.");
	/*
	 * While the failure condition is true, and we haven't reached our
	 * three reload limit, continue trying to reload the driver and
	 * fix the issue.
	 */
	while (failure && (reload != 0)) {
		codec_info(codec, "Reloading... Tries left: %d", reload);
		sbz_exit_chip(codec);
		spec->dsp_state = DSP_DOWNLOAD_INIT;
		codec->patch_ops.init(codec);
		failure = 0;
		for (i = 0; i < 4; i++) {
			chipio_read(codec, cur_address, &dsp_data_check[i]);
			cur_address += 0x4;
		}
		for (i = 0; i < 4; i++) {
			if (dsp_data_check[i] == 0xa1a2a3a4)
				failure = 1;
		}
		reload--;
	}

	if (!failure && reload < 3)
		codec_info(codec, "DSP fixed.");

	if (!failure)
		return;

	codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
}

7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153
/*
 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
 * extra precision for decibel values. If you had the dB value in floating point
 * you would take the value after the decimal point, multiply by 64, and divide
 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
 * implement fixed point or floating point dB volumes. For now, I'll set them
 * to 0 just incase a value has lingered from a boot into Windows.
 */
static void ca0132_alt_vol_setup(struct hda_codec *codec)
{
	snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
	snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
	snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
	snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
	snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
	snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
	snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
	snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
}

/*
 * Extra commands that don't really fit anywhere else.
 */
static void sbz_pre_dsp_setup(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	writel(0x00820680, spec->mem_base + 0x01C);
	writel(0x00820680, spec->mem_base + 0x01C);

	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);

	chipio_write(codec, 0x18b0a4, 0x000000c2);

	snd_hda_codec_write(codec, 0x11, 0,
			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
}

7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174
static void r3d_pre_dsp_setup(struct hda_codec *codec)
{

	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);

	chipio_write(codec, 0x18b0a4, 0x000000c2);

	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);

	snd_hda_codec_write(codec, 0x11, 0,
			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
}

7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203
static void r3di_pre_dsp_setup(struct hda_codec *codec)
{
	chipio_write(codec, 0x18b0a4, 0x000000c2);

	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);

	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);

	snd_hda_codec_write(codec, 0x11, 0,
			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
}

/*
 * These are sent before the DSP is downloaded. Not sure
 * what they do, or if they're necessary. Could possibly
 * be removed. Figure they're better to leave in.
 */
7204
static void ca0132_mmio_init(struct hda_codec *codec)
7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215 7216 7217 7218 7219 7220 7221 7222 7223 7224 7225 7226 7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243
{
	struct ca0132_spec *spec = codec->spec;

	writel(0x00000000, spec->mem_base + 0x400);
	writel(0x00000000, spec->mem_base + 0x408);
	writel(0x00000000, spec->mem_base + 0x40C);
	writel(0x00880680, spec->mem_base + 0x01C);
	writel(0x00000083, spec->mem_base + 0xC0C);
	writel(0x00000030, spec->mem_base + 0xC00);
	writel(0x00000000, spec->mem_base + 0xC04);
	writel(0x00000003, spec->mem_base + 0xC0C);
	writel(0x00000003, spec->mem_base + 0xC0C);
	writel(0x00000003, spec->mem_base + 0xC0C);
	writel(0x00000003, spec->mem_base + 0xC0C);
	writel(0x000000C1, spec->mem_base + 0xC08);
	writel(0x000000F1, spec->mem_base + 0xC08);
	writel(0x00000001, spec->mem_base + 0xC08);
	writel(0x000000C7, spec->mem_base + 0xC08);
	writel(0x000000C1, spec->mem_base + 0xC08);
	writel(0x00000080, spec->mem_base + 0xC04);
}

/*
 * Extra init functions for alternative ca0132 codecs. Done
 * here so they don't clutter up the main ca0132_init function
 * anymore than they have to.
 */
static void ca0132_alt_init(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	ca0132_alt_vol_setup(codec);

	switch (spec->quirk) {
	case QUIRK_SBZ:
		codec_dbg(codec, "SBZ alt_init");
		ca0132_gpio_init(codec);
		sbz_pre_dsp_setup(codec);
		snd_hda_sequence_write(codec, spec->chip_init_verbs);
7244
		snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7245 7246 7247 7248 7249
		break;
	case QUIRK_R3DI:
		codec_dbg(codec, "R3DI alt_init");
		ca0132_gpio_init(codec);
		ca0132_gpio_setup(codec);
7250
		r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
7251 7252 7253 7254
		r3di_pre_dsp_setup(codec);
		snd_hda_sequence_write(codec, spec->chip_init_verbs);
		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
		break;
7255 7256 7257 7258 7259
	case QUIRK_R3D:
		r3d_pre_dsp_setup(codec);
		snd_hda_sequence_write(codec, spec->chip_init_verbs);
		snd_hda_sequence_write(codec, spec->desktop_init_verbs);
		break;
7260 7261 7262
	}
}

7263 7264 7265 7266 7267
static int ca0132_init(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;
	struct auto_pin_cfg *cfg = &spec->autocfg;
	int i;
7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283 7284
	bool dsp_loaded;

	/*
	 * If the DSP is already downloaded, and init has been entered again,
	 * there's only two reasons for it. One, the codec has awaken from a
	 * suspended state, and in that case dspload_is_loaded will return
	 * false, and the init will be ran again. The other reason it gets
	 * re entered is on startup for some reason it triggers a suspend and
	 * resume state. In this case, it will check if the DSP is downloaded,
	 * and not run the init function again. For codecs using alt_functions,
	 * it will check if the DSP is loaded properly.
	 */
	if (spec->dsp_state == DSP_DOWNLOADED) {
		dsp_loaded = dspload_is_loaded(codec);
		if (!dsp_loaded) {
			spec->dsp_reload = true;
			spec->dsp_state = DSP_DOWNLOAD_INIT;
7285 7286 7287
		} else {
			if (spec->quirk == QUIRK_SBZ)
				sbz_dsp_startup_check(codec);
7288
			return 0;
7289
		}
7290
	}
7291

7292 7293
	if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
		spec->dsp_state = DSP_DOWNLOAD_INIT;
7294
	spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7295

7296 7297
	if (spec->use_pci_mmio)
		ca0132_mmio_init(codec);
7298

7299
	snd_hda_power_up_pm(codec);
7300

7301
	ca0132_init_unsol(codec);
7302 7303
	ca0132_init_params(codec);
	ca0132_init_flags(codec);
7304

7305
	snd_hda_sequence_write(codec, spec->base_init_verbs);
7306

7307
	if (spec->use_alt_functions)
7308 7309
		ca0132_alt_init(codec);

7310
	ca0132_download_dsp(codec);
7311

7312
	ca0132_refresh_widget_caps(codec);
7313

7314 7315
	switch (spec->quirk) {
	case QUIRK_R3DI:
7316 7317
	case QUIRK_R3D:
		r3d_setup_defaults(codec);
7318
		break;
7319
	case QUIRK_SBZ:
7320
		sbz_setup_defaults(codec);
7321 7322
		break;
	default:
7323 7324 7325
		ca0132_setup_defaults(codec);
		ca0132_init_analog_mic2(codec);
		ca0132_init_dmic(codec);
7326
		break;
7327
	}
7328 7329 7330

	for (i = 0; i < spec->num_outputs; i++)
		init_output(codec, spec->out_pins[i], spec->dacs[0]);
7331

7332 7333 7334 7335 7336 7337 7338
	init_output(codec, cfg->dig_out_pins[0], spec->dig_out);

	for (i = 0; i < spec->num_inputs; i++)
		init_input(codec, spec->input_pins[i], spec->adcs[i]);

	init_input(codec, cfg->dig_in_pin, spec->dig_in);

7339
	if (!spec->use_alt_functions) {
7340 7341 7342 7343 7344 7345 7346
		snd_hda_sequence_write(codec, spec->chip_init_verbs);
		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
			    VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
	}

7347
	if (spec->quirk == QUIRK_SBZ)
7348 7349
		ca0132_gpio_setup(codec);

7350
	snd_hda_sequence_write(codec, spec->spec_init_verbs);
7351
	if (spec->use_alt_functions) {
7352 7353
		ca0132_alt_select_out(codec);
		ca0132_alt_select_in(codec);
7354
	} else {
7355 7356 7357
		ca0132_select_out(codec);
		ca0132_select_mic(codec);
	}
7358

7359 7360
	snd_hda_jack_report_sync(codec);

7361 7362 7363 7364 7365 7366 7367 7368 7369
	/*
	 * Re set the PlayEnhancement switch on a resume event, because the
	 * controls will not be reloaded.
	 */
	if (spec->dsp_reload) {
		spec->dsp_reload = false;
		ca0132_pe_switch_set(codec);
	}

7370
	snd_hda_power_down_pm(codec);
7371 7372 7373 7374 7375 7376

	return 0;
}

static void ca0132_free(struct hda_codec *codec)
{
7377 7378
	struct ca0132_spec *spec = codec->spec;

7379
	cancel_delayed_work_sync(&spec->unsol_hp_work);
7380
	snd_hda_power_up(codec);
7381 7382 7383 7384
	switch (spec->quirk) {
	case QUIRK_SBZ:
		sbz_exit_chip(codec);
		break;
7385 7386 7387
	case QUIRK_R3D:
		r3d_exit_chip(codec);
		break;
7388 7389 7390 7391
	case QUIRK_R3DI:
		r3di_gpio_shutdown(codec);
		break;
	}
7392 7393 7394 7395

	snd_hda_sequence_write(codec, spec->base_exit_verbs);
	ca0132_exit_chip(codec);

7396
	snd_hda_power_down(codec);
7397
	if (spec->mem_base)
7398
		pci_iounmap(codec->bus->pci, spec->mem_base);
7399
	kfree(spec->spec_init_verbs);
7400 7401 7402
	kfree(codec->spec);
}

7403 7404 7405 7406 7407
static void ca0132_reboot_notify(struct hda_codec *codec)
{
	codec->patch_ops.free(codec);
}

7408
static const struct hda_codec_ops ca0132_patch_ops = {
7409 7410 7411 7412
	.build_controls = ca0132_build_controls,
	.build_pcms = ca0132_build_pcms,
	.init = ca0132_init,
	.free = ca0132_free,
7413
	.unsol_event = snd_hda_jack_unsol_event,
7414
	.reboot_notify = ca0132_reboot_notify,
7415 7416
};

7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427
static void ca0132_config(struct hda_codec *codec)
{
	struct ca0132_spec *spec = codec->spec;

	spec->dacs[0] = 0x2;
	spec->dacs[1] = 0x3;
	spec->dacs[2] = 0x4;

	spec->multiout.dac_nids = spec->dacs;
	spec->multiout.num_dacs = 3;

7428
	if (!spec->use_alt_functions)
7429 7430 7431 7432 7433 7434
		spec->multiout.max_channels = 2;
	else
		spec->multiout.max_channels = 6;

	switch (spec->quirk) {
	case QUIRK_ALIENWARE:
7435
		codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
7436 7437 7438 7439
		snd_hda_apply_pincfgs(codec, alienware_pincfgs);

		spec->num_outputs = 2;
		spec->out_pins[0] = 0x0b; /* speaker out */
7440
		spec->out_pins[1] = 0x0f;
7441 7442 7443 7444 7445 7446 7447 7448 7449 7450 7451 7452 7453
		spec->shared_out_nid = 0x2;
		spec->unsol_tag_hp = 0x0f;

		spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
		spec->adcs[1] = 0x8; /* analog mic2 */
		spec->adcs[2] = 0xa; /* what u hear */

		spec->num_inputs = 3;
		spec->input_pins[0] = 0x12;
		spec->input_pins[1] = 0x11;
		spec->input_pins[2] = 0x13;
		spec->shared_mic_nid = 0x7;
		spec->unsol_tag_amic1 = 0x11;
7454 7455
		break;
	case QUIRK_SBZ:
7456 7457 7458 7459 7460 7461 7462 7463 7464
	case QUIRK_R3D:
		if (spec->quirk == QUIRK_SBZ) {
			codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
			snd_hda_apply_pincfgs(codec, sbz_pincfgs);
		}
		if (spec->quirk == QUIRK_R3D) {
			codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
			snd_hda_apply_pincfgs(codec, r3d_pincfgs);
		}
7465 7466 7467 7468 7469 7470 7471 7472 7473 7474 7475 7476 7477 7478 7479 7480 7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505 7506 7507 7508 7509 7510 7511 7512 7513 7514 7515 7516 7517

		spec->num_outputs = 2;
		spec->out_pins[0] = 0x0B; /* Line out */
		spec->out_pins[1] = 0x0F; /* Rear headphone out */
		spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
		spec->out_pins[3] = 0x11; /* Rear surround */
		spec->shared_out_nid = 0x2;
		spec->unsol_tag_hp = spec->out_pins[1];
		spec->unsol_tag_front_hp = spec->out_pins[2];

		spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
		spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
		spec->adcs[2] = 0xa; /* what u hear */

		spec->num_inputs = 2;
		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
		spec->input_pins[1] = 0x13; /* What U Hear */
		spec->shared_mic_nid = 0x7;
		spec->unsol_tag_amic1 = spec->input_pins[0];

		/* SPDIF I/O */
		spec->dig_out = 0x05;
		spec->multiout.dig_out_nid = spec->dig_out;
		spec->dig_in = 0x09;
		break;
	case QUIRK_R3DI:
		codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
		snd_hda_apply_pincfgs(codec, r3di_pincfgs);

		spec->num_outputs = 2;
		spec->out_pins[0] = 0x0B; /* Line out */
		spec->out_pins[1] = 0x0F; /* Rear headphone out */
		spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
		spec->out_pins[3] = 0x11; /* Rear surround */
		spec->shared_out_nid = 0x2;
		spec->unsol_tag_hp = spec->out_pins[1];
		spec->unsol_tag_front_hp = spec->out_pins[2];

		spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
		spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
		spec->adcs[2] = 0x0a; /* what u hear */

		spec->num_inputs = 2;
		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
		spec->input_pins[1] = 0x13; /* What U Hear */
		spec->shared_mic_nid = 0x7;
		spec->unsol_tag_amic1 = spec->input_pins[0];

		/* SPDIF I/O */
		spec->dig_out = 0x05;
		spec->multiout.dig_out_nid = spec->dig_out;
		break;
	default:
7518 7519
		spec->num_outputs = 2;
		spec->out_pins[0] = 0x0b; /* speaker out */
7520
		spec->out_pins[1] = 0x10; /* headphone out */
7521 7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532 7533 7534 7535 7536 7537 7538
		spec->shared_out_nid = 0x2;
		spec->unsol_tag_hp = spec->out_pins[1];

		spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
		spec->adcs[1] = 0x8; /* analog mic2 */
		spec->adcs[2] = 0xa; /* what u hear */

		spec->num_inputs = 3;
		spec->input_pins[0] = 0x12;
		spec->input_pins[1] = 0x11;
		spec->input_pins[2] = 0x13;
		spec->shared_mic_nid = 0x7;
		spec->unsol_tag_amic1 = spec->input_pins[0];

		/* SPDIF I/O */
		spec->dig_out = 0x05;
		spec->multiout.dig_out_nid = spec->dig_out;
		spec->dig_in = 0x09;
7539
		break;
7540
	}
7541 7542
}

7543 7544 7545
static int ca0132_prepare_verbs(struct hda_codec *codec)
{
/* Verbs + terminator (an empty element) */
7546
#define NUM_SPEC_VERBS 2
7547 7548 7549
	struct ca0132_spec *spec = codec->spec;

	spec->chip_init_verbs = ca0132_init_verbs0;
7550 7551
	if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D)
		spec->desktop_init_verbs = ca0132_init_verbs1;
K
Kees Cook 已提交
7552 7553 7554
	spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
					sizeof(struct hda_verb),
					GFP_KERNEL);
7555 7556 7557 7558
	if (!spec->spec_init_verbs)
		return -ENOMEM;

	/* config EAPD */
7559 7560 7561
	spec->spec_init_verbs[0].nid = 0x0b;
	spec->spec_init_verbs[0].param = 0x78D;
	spec->spec_init_verbs[0].verb = 0x00;
7562 7563 7564

	/* Previously commented configuration */
	/*
7565 7566 7567 7568 7569 7570
	spec->spec_init_verbs[2].nid = 0x0b;
	spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
	spec->spec_init_verbs[2].verb = 0x02;

	spec->spec_init_verbs[3].nid = 0x10;
	spec->spec_init_verbs[3].param = 0x78D;
7571 7572 7573
	spec->spec_init_verbs[3].verb = 0x02;

	spec->spec_init_verbs[4].nid = 0x10;
7574
	spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
7575 7576 7577 7578 7579 7580 7581
	spec->spec_init_verbs[4].verb = 0x02;
	*/

	/* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
	return 0;
}

7582 7583 7584
static int patch_ca0132(struct hda_codec *codec)
{
	struct ca0132_spec *spec;
7585
	int err;
7586
	const struct snd_pci_quirk *quirk;
7587

7588
	codec_dbg(codec, "patch_ca0132\n");
7589 7590 7591 7592 7593

	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
	if (!spec)
		return -ENOMEM;
	codec->spec = spec;
7594
	spec->codec = codec;
7595

7596 7597 7598 7599
	codec->patch_ops = ca0132_patch_ops;
	codec->pcm_format_first = 1;
	codec->no_sticky_stream = 1;

7600 7601 7602 7603 7604 7605 7606
	/* Detect codec quirk */
	quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
	if (quirk)
		spec->quirk = quirk->value;
	else
		spec->quirk = QUIRK_NONE;

7607
	spec->dsp_state = DSP_DOWNLOAD_INIT;
7608
	spec->num_mixers = 1;
7609 7610 7611 7612

	/* Set which mixers each quirk uses. */
	switch (spec->quirk) {
	case QUIRK_SBZ:
7613
		spec->mixers[0] = desktop_mixer;
7614 7615
		snd_hda_codec_set_name(codec, "Sound Blaster Z");
		break;
7616 7617 7618 7619
	case QUIRK_R3D:
		spec->mixers[0] = desktop_mixer;
		snd_hda_codec_set_name(codec, "Recon3D");
		break;
7620 7621 7622 7623 7624 7625 7626 7627
	case QUIRK_R3DI:
		spec->mixers[0] = r3di_mixer;
		snd_hda_codec_set_name(codec, "Recon3Di");
		break;
	default:
		spec->mixers[0] = ca0132_mixer;
		break;
	}
7628

7629
	/* Setup whether or not to use alt functions/controls/pci_mmio */
7630 7631
	switch (spec->quirk) {
	case QUIRK_SBZ:
7632
	case QUIRK_R3D:
7633 7634 7635 7636
		spec->use_alt_controls = true;
		spec->use_alt_functions = true;
		spec->use_pci_mmio = true;
		break;
7637
	case QUIRK_R3DI:
7638
		spec->use_alt_controls = true;
7639
		spec->use_alt_functions = true;
7640
		spec->use_pci_mmio = false;
7641 7642
		break;
	default:
7643
		spec->use_alt_controls = false;
7644
		spec->use_alt_functions = false;
7645
		spec->use_pci_mmio = false;
7646 7647 7648
		break;
	}

7649 7650 7651 7652 7653 7654 7655 7656
	if (spec->use_pci_mmio) {
		spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
		if (spec->mem_base == NULL) {
			codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
			spec->quirk = QUIRK_NONE;
		}
	}

7657 7658 7659
	spec->base_init_verbs = ca0132_base_init_verbs;
	spec->base_exit_verbs = ca0132_base_exit_verbs;

7660 7661
	INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);

7662 7663 7664 7665
	ca0132_init_chip(codec);

	ca0132_config(codec);

7666 7667
	err = ca0132_prepare_verbs(codec);
	if (err < 0)
7668
		goto error;
7669

7670 7671
	err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
	if (err < 0)
7672
		goto error;
7673

7674
	return 0;
7675 7676 7677 7678

 error:
	ca0132_free(codec);
	return err;
7679 7680 7681 7682 7683
}

/*
 * patch entries
 */
7684 7685
static struct hda_device_id snd_hda_id_ca0132[] = {
	HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
7686 7687
	{} /* terminator */
};
7688
MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
7689 7690

MODULE_LICENSE("GPL");
7691
MODULE_DESCRIPTION("Creative Sound Core3D codec");
7692

7693
static struct hda_codec_driver ca0132_driver = {
7694
	.id = snd_hda_id_ca0132,
7695 7696
};

7697
module_hda_codec_driver(ca0132_driver);