Makefile.rules

# ===========================================================================
# arch/um: Generic definitions
# ===========================================================================

USER_SINGLE_OBJS := \
	$(foreach f,$(patsubst %.o,%,$(obj-y) $(obj-m)),$($(f)-objs))
USER_OBJS += $(filter %_user.o,$(obj-y) $(obj-m)  $(USER_SINGLE_OBJS))
USER_OBJS := $(foreach file,$(USER_OBJS),$(obj)/$(file))

$(USER_OBJS) : c_flags = -Wp,-MD,$(depfile) $(USER_CFLAGS) \
	$(CFLAGS_$(notdir $@))
$(USER_OBJS): cmd_checksrc =
$(USER_OBJS): quiet_cmd_checksrc =
$(USER_OBJS): cmd_force_checksrc =
$(USER_OBJS): quiet_cmd_force_checksrc =


# The stubs and unmap.o can't try to call mcount or update basic block data
define unprofile
	$(patsubst -pg,,$(patsubst -fprofile-arcs -ftest-coverage,,$(1)))
endef


# The stubs and unmap.o can't try to call mcount or update basic block data
define unprofile
	$(patsubst -pg,,$(patsubst -fprofile-arcs -ftest-coverage,,$(1)))
endef

quiet_cmd_make_link = SYMLINK $@
cmd_make_link       = ln -sf $(srctree)/arch/$(SUBARCH)/$($(notdir $@)-dir)/$(notdir $@) $@

# this needs to be before the foreach, because targets does not accept
# complete paths like $(obj)/$(f). To make sure this works, use a := assignment
# or we will get $(obj)/$(f) in the "targets" value.
# Also, this forces you to use the := syntax when assigning to targets.
# Otherwise the line below will cause an infinite loop (if you don't know why,
# just do it).

targets := $(targets) $(SYMLINKS)

SYMLINKS := $(foreach f,$(SYMLINKS),$(obj)/$(f))

$(SYMLINKS): FORCE
	$(call if_changed,make_link)