irqinit.c 7.1 KB
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#include <linux/linkage.h>
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#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/random.h>
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#include <linux/kprobes.h>
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#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/bitops.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
#include <linux/delay.h>
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#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/timer.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
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#include <asm/setup.h>
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#include <asm/i8259.h>
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#include <asm/traps.h>
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/*
 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
 * (these are usually mapped to vectors 0x30-0x3f)
 */

/*
 * The IO-APIC gives us many more interrupt sources. Most of these
 * are unused but an SMP system is supposed to have enough memory ...
 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
 * across the spectrum, so we really want to be prepared to get all
 * of these. Plus, more powerful systems might have more than 64
 * IO-APIC registers.
 *
 * (these are usually mapped into the 0x30-0xff vector range)
 */
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#ifdef CONFIG_X86_32
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/*
 * Note that on a 486, we don't want to do a SIGFPE on an irq13
 * as the irq is unreliable, and exception 16 works correctly
 * (ie as explained in the intel literature). On a 386, you
 * can't use exception 16 due to bad IBM design, so we have to
 * rely on the less exact irq13.
 *
 * Careful.. Not only is IRQ13 unreliable, but it is also
 * leads to races. IBM designers who came up with it should
 * be shot.
 */

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static irqreturn_t math_error_irq(int cpl, void *dev_id)
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{
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	outb(0, 0xF0);
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	if (ignore_fpu_irq || !boot_cpu_data.hard_math)
		return IRQ_NONE;
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	math_error(get_irq_regs(), 0, 16);
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	return IRQ_HANDLED;
}

/*
 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
 * so allow interrupt sharing.
 */
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static struct irqaction fpu_irq = {
	.handler = math_error_irq,
	.name = "fpu",
};
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#endif

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/*
 * IRQ2 is cascade interrupt to second interrupt controller
 */
static struct irqaction irq2 = {
	.handler = no_action,
	.name = "cascade",
};

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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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	[0 ... NR_VECTORS - 1] = -1,
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};

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int vector_used_by_percpu_irq(unsigned int vector)
{
	int cpu;

	for_each_online_cpu(cpu) {
		if (per_cpu(vector_irq, cpu)[vector] != -1)
			return 1;
	}

	return 0;
}

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void __init init_ISA_irqs(void)
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{
	int i;

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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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	init_bsp_APIC();
#endif
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	legacy_pic->init(0);
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	/*
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	 * 16 old-style INTA-cycle interrupts:
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	 */
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	for (i = 0; i < legacy_pic->nr_legacy_irqs; i++) {
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		struct irq_desc *desc = irq_to_desc(i);

		desc->status = IRQ_DISABLED;
		desc->action = NULL;
		desc->depth = 1;

		set_irq_chip_and_handler_name(i, &i8259A_chip,
					      handle_level_irq, "XT");
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	}
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}
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void __init init_IRQ(void)
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{
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	int i;

	/*
	 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
	 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
	 * then this configuration will likely be static after the boot. If
	 * these IRQ's are handled by more mordern controllers like IO-APIC,
	 * then this vector space can be freed and re-used dynamically as the
	 * irq's migrate etc.
	 */
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	for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
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		per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;

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	x86_init.irqs.intr_init();
}
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/*
 * Setup the vector to irq mappings.
 */
void setup_vector_irq(int cpu)
{
#ifndef CONFIG_X86_IO_APIC
	int irq;

	/*
	 * On most of the platforms, legacy PIC delivers the interrupts on the
	 * boot cpu. But there are certain platforms where PIC interrupts are
	 * delivered to multiple cpu's. If the legacy IRQ is handled by the
	 * legacy PIC, for the new cpu that is coming online, setup the static
	 * legacy vector to irq mapping:
	 */
	for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)
		per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
#endif

	__setup_vector_irq(cpu);
}

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static void __init smp_intr_init(void)
{
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#ifdef CONFIG_SMP
#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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	/*
	 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
	 * IPI, driven by wakeup.
	 */
	alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);

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	/* IPIs for invalidation */
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
	alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
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	/* IPI for generic function call */
	alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);

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	/* IPI for generic single function call */
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	alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
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			call_function_single_interrupt);
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	/* Low priority IPI to cleanup after moving an irq */
	set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
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	set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
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	/* IPI used for rebooting/stopping */
	alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
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#endif
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#endif /* CONFIG_SMP */
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}

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static void __init apic_intr_init(void)
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{
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	smp_intr_init();
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#ifdef CONFIG_X86_THERMAL_VECTOR
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	alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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	alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
#endif
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#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
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	alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
#endif
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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	/* self generated IPI for local APIC timer */
	alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);

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	/* IPI for X86 platform specific use */
	alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
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	/* IPI vectors for APIC spurious and error interrupts */
	alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
	alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);

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	/* Performance monitoring interrupts: */
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# ifdef CONFIG_PERF_EVENTS
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	alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt);
# endif

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#endif
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}
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void __init native_init_IRQ(void)
{
	int i;

	/* Execute any quirks before the call gates are initialised: */
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	x86_init.irqs.pre_vector_init();
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	apic_intr_init();

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	/*
	 * Cover the whole vector space, no vector can escape
	 * us. (some of these will be overridden and become
	 * 'special' SMP interrupts)
	 */
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	for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
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		/* IA32_SYSCALL_VECTOR could be used in trap_init already. */
		if (!test_bit(i, used_vectors))
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			set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
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	}
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	if (!acpi_ioapic)
		setup_irq(2, &irq2);

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#ifdef CONFIG_X86_32
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	/*
	 * External FPU? Set up irq13 if so, for
	 * original braindamaged IBM FERR coupling.
	 */
	if (boot_cpu_data.hard_math && !cpu_has_fpu)
		setup_irq(FPU_IRQ, &fpu_irq);

	irq_ctx_init(smp_processor_id());
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#endif
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}