io_apic_64.c 57.5 KB
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/*
 *	Intel IO-APIC support for multi-Pentium hosts.
 *
 *	Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
 *
 *	Many thanks to Stig Venaas for trying out countless experimental
 *	patches and reporting/debugging problems patiently!
 *
 *	(c) 1999, Multiple IO-APIC support, developed by
 *	Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
 *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
 *	further tested and cleaned up by Zach Brown <zab@redhat.com>
 *	and Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively
 *	Paul Diefenbaugh	:	Added full ACPI support
 */

#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/mc146818rtc.h>
#include <linux/acpi.h>
#include <linux/sysdev.h>
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#include <linux/msi.h>
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#include <linux/htirq.h>
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#include <linux/dmar.h>
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#include <linux/jiffies.h>
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#ifdef CONFIG_ACPI
#include <acpi/acpi_bus.h>
#endif
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#include <linux/bootmem.h>
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#include <asm/idle.h>
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#include <asm/io.h>
#include <asm/smp.h>
#include <asm/desc.h>
#include <asm/proto.h>
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#include <asm/acpi.h>
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#include <asm/dma.h>
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#include <asm/nmi.h>
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#include <asm/msidef.h>
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#include <asm/hypertransport.h>
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#include <mach_ipi.h>
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#include <mach_apic.h>
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struct irq_cfg {
	cpumask_t domain;
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	cpumask_t old_domain;
	unsigned move_cleanup_count;
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	u8 vector;
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	u8 move_in_progress : 1;
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};

/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
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static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
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	[0]  = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR,  },
	[1]  = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR,  },
	[2]  = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR,  },
	[3]  = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR,  },
	[4]  = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR,  },
	[5]  = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR,  },
	[6]  = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR,  },
	[7]  = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR,  },
	[8]  = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR,  },
	[9]  = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR,  },
	[10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
	[11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
	[12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
	[13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
	[14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
	[15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
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};

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static int assign_irq_vector(int irq, cpumask_t mask);
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int first_system_vector = 0xfe;

char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};

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#define __apicdebuginit  __init

int sis_apic_bug; /* not actually supported, dummy for compile */

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static int no_timer_check;

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static int disable_timer_pin_1 __initdata;

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int timer_through_8259 __initdata;
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/* Where if anywhere is the i8259 connect in external int mode */
static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };

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static DEFINE_SPINLOCK(ioapic_lock);
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DEFINE_SPINLOCK(vector_lock);
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/*
 * # of IRQ routing registers
 */
int nr_ioapic_registers[MAX_IO_APICS];

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/* I/O APIC entries */
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struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
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int nr_ioapics;

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/* MP IRQ source entries */
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struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* # of MP IRQ source entries */
int mp_irq_entries;

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DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);

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/*
 * Rough estimation of how many shared IRQs there are, can
 * be changed anytime.
 */
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#define MAX_PLUS_SHARED_IRQS NR_IRQS
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#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)

/*
 * This is performance-critical, we want to do it O(1)
 *
 * the indexing order of this array favors 1:1 mappings
 * between pins and IRQs.
 */

static struct irq_pin_list {
	short apic, pin, next;
} irq_2_pin[PIN_MAP_SIZE];

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struct io_apic {
	unsigned int index;
	unsigned int unused[3];
	unsigned int data;
};

static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
{
	return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
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		+ (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
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}

static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	writel(reg, &io_apic->index);
	return readl(&io_apic->data);
}

static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	writel(reg, &io_apic->index);
	writel(value, &io_apic->data);
}

/*
 * Re-write a value: to be used for read-modify-write
 * cycles where the read already set up the index register.
 */
static inline void io_apic_modify(unsigned int apic, unsigned int value)
{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	writel(value, &io_apic->data);
}

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static bool io_apic_level_ack_pending(unsigned int irq)
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{
	struct irq_pin_list *entry;
	unsigned long flags;

	spin_lock_irqsave(&ioapic_lock, flags);
	entry = irq_2_pin + irq;
	for (;;) {
		unsigned int reg;
		int pin;

		pin = entry->pin;
		if (pin == -1)
			break;
		reg = io_apic_read(entry->apic, 0x10 + pin*2);
		/* Is the remote IRR bit set? */
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		if (reg & IO_APIC_REDIR_REMOTE_IRR) {
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			spin_unlock_irqrestore(&ioapic_lock, flags);
			return true;
		}
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		if (!entry->next)
			break;
		entry = irq_2_pin + entry->next;
	}
	spin_unlock_irqrestore(&ioapic_lock, flags);
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	return false;
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}

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/*
 * Synchronize the IO-APIC and the CPU by doing
 * a dummy read from the IO-APIC
 */
static inline void io_apic_sync(unsigned int apic)
{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	readl(&io_apic->data);
}

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#define __DO_ACTION(R, ACTION, FINAL)					\
									\
{									\
	int pin;							\
	struct irq_pin_list *entry = irq_2_pin + irq;			\
									\
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	BUG_ON(irq >= NR_IRQS);						\
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	for (;;) {							\
		unsigned int reg;					\
		pin = entry->pin;					\
		if (pin == -1)						\
			break;						\
		reg = io_apic_read(entry->apic, 0x10 + R + pin*2);	\
		reg ACTION;						\
		io_apic_modify(entry->apic, reg);			\
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		FINAL;							\
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		if (!entry->next)					\
			break;						\
		entry = irq_2_pin + entry->next;			\
	}								\
}

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union entry_union {
	struct { u32 w1, w2; };
	struct IO_APIC_route_entry entry;
};

static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
{
	union entry_union eu;
	unsigned long flags;
	spin_lock_irqsave(&ioapic_lock, flags);
	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
	spin_unlock_irqrestore(&ioapic_lock, flags);
	return eu.entry;
}

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/*
 * When we write a new IO APIC routing entry, we need to write the high
 * word first! If the mask bit in the low word is clear, we will enable
 * the interrupt, and we need to make sure the entry is fully populated
 * before that happens.
 */
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static void
__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
	union entry_union eu;
	eu.entry = e;
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	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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}

static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
{
	unsigned long flags;
	spin_lock_irqsave(&ioapic_lock, flags);
	__ioapic_write_entry(apic, pin, e);
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	spin_unlock_irqrestore(&ioapic_lock, flags);
}

/*
 * When we mask an IO APIC routing entry, we need to write the low
 * word first, in order to set the mask bit before we change the
 * high bits!
 */
static void ioapic_mask_entry(int apic, int pin)
{
	unsigned long flags;
	union entry_union eu = { .entry.mask = 1 };

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	spin_lock_irqsave(&ioapic_lock, flags);
	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
	spin_unlock_irqrestore(&ioapic_lock, flags);
}

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#ifdef CONFIG_SMP
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static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
{
	int apic, pin;
	struct irq_pin_list *entry = irq_2_pin + irq;

	BUG_ON(irq >= NR_IRQS);
	for (;;) {
		unsigned int reg;
		apic = entry->apic;
		pin = entry->pin;
		if (pin == -1)
			break;
		io_apic_write(apic, 0x11 + pin*2, dest);
		reg = io_apic_read(apic, 0x10 + pin*2);
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		reg &= ~IO_APIC_REDIR_VECTOR_MASK;
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		reg |= vector;
		io_apic_modify(apic, reg);
		if (!entry->next)
			break;
		entry = irq_2_pin + entry->next;
	}
}

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static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
{
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	struct irq_cfg *cfg = irq_cfg + irq;
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	unsigned long flags;
	unsigned int dest;
	cpumask_t tmp;

	cpus_and(tmp, mask, cpu_online_map);
	if (cpus_empty(tmp))
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		return;
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	if (assign_irq_vector(irq, mask))
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		return;

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	cpus_and(tmp, cfg->domain, mask);
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	dest = cpu_mask_to_apicid(tmp);
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	/*
	 * Only the high 8 bits are valid.
	 */
	dest = SET_APIC_LOGICAL_ID(dest);

	spin_lock_irqsave(&ioapic_lock, flags);
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	__target_IO_APIC_irq(irq, dest, cfg->vector);
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	irq_desc[irq].affinity = mask;
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	spin_unlock_irqrestore(&ioapic_lock, flags);
}
#endif

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/*
 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 * shared ISA-space IRQs, so we have to support them. We are super
 * fast in the common case, and fast for shared ISA-space IRQs.
 */
static void add_pin_to_irq(unsigned int irq, int apic, int pin)
{
	static int first_free_entry = NR_IRQS;
	struct irq_pin_list *entry = irq_2_pin + irq;

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	BUG_ON(irq >= NR_IRQS);
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	while (entry->next)
		entry = irq_2_pin + entry->next;

	if (entry->pin != -1) {
		entry->next = first_free_entry;
		entry = irq_2_pin + entry->next;
		if (++first_free_entry >= PIN_MAP_SIZE)
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			panic("io_apic.c: ran out of irq_2_pin entries!");
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	}
	entry->apic = apic;
	entry->pin = pin;
}

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/*
 * Reroute an IRQ to a different pin.
 */
static void __init replace_pin_at_irq(unsigned int irq,
				      int oldapic, int oldpin,
				      int newapic, int newpin)
{
	struct irq_pin_list *entry = irq_2_pin + irq;

	while (1) {
		if (entry->apic == oldapic && entry->pin == oldpin) {
			entry->apic = newapic;
			entry->pin = newpin;
		}
		if (!entry->next)
			break;
		entry = irq_2_pin + entry->next;
	}
}

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#define DO_ACTION(name,R,ACTION, FINAL)					\
									\
	static void name##_IO_APIC_irq (unsigned int irq)		\
	__DO_ACTION(R, ACTION, FINAL)

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/* mask = 1 */
DO_ACTION(__mask,	0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))

/* mask = 0 */
DO_ACTION(__unmask,	0, &= ~IO_APIC_REDIR_MASKED, )
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static void mask_IO_APIC_irq (unsigned int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&ioapic_lock, flags);
	__mask_IO_APIC_irq(irq);
	spin_unlock_irqrestore(&ioapic_lock, flags);
}

static void unmask_IO_APIC_irq (unsigned int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&ioapic_lock, flags);
	__unmask_IO_APIC_irq(irq);
	spin_unlock_irqrestore(&ioapic_lock, flags);
}

static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
{
	struct IO_APIC_route_entry entry;

	/* Check delivery_mode to be sure we're not clearing an SMI pin */
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	entry = ioapic_read_entry(apic, pin);
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	if (entry.delivery_mode == dest_SMI)
		return;
	/*
	 * Disable it in the IO-APIC irq-routing table:
	 */
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	ioapic_mask_entry(apic, pin);
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}

static void clear_IO_APIC (void)
{
	int apic, pin;

	for (apic = 0; apic < nr_ioapics; apic++)
		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
			clear_IO_APIC_pin(apic, pin);
}

int skip_ioapic_setup;
int ioapic_force;

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static int __init parse_noapic(char *str)
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{
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	disable_ioapic_setup();
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	return 0;
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}
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early_param("noapic", parse_noapic);
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/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
static int __init disable_timer_pin_setup(char *arg)
{
	disable_timer_pin_1 = 1;
	return 1;
}
__setup("disable_timer_pin_1", disable_timer_pin_setup);


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/*
 * Find the IRQ entry number of a certain pin.
 */
static int find_irq_entry(int apic, int pin, int type)
{
	int i;

	for (i = 0; i < mp_irq_entries; i++)
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		if (mp_irqs[i].mp_irqtype == type &&
		    (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
		     mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
		    mp_irqs[i].mp_dstirq == pin)
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			return i;

	return -1;
}

/*
 * Find the pin to which IRQ[irq] (ISA) is connected
 */
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static int __init find_isa_irq_pin(int irq, int type)
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{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
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		int lbus = mp_irqs[i].mp_srcbus;
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		if (test_bit(lbus, mp_bus_not_pci) &&
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		    (mp_irqs[i].mp_irqtype == type) &&
		    (mp_irqs[i].mp_srcbusirq == irq))
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			return mp_irqs[i].mp_dstirq;
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	}
	return -1;
}

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static int __init find_isa_irq_apic(int irq, int type)
{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
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		int lbus = mp_irqs[i].mp_srcbus;
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		if (test_bit(lbus, mp_bus_not_pci) &&
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		    (mp_irqs[i].mp_irqtype == type) &&
		    (mp_irqs[i].mp_srcbusirq == irq))
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			break;
	}
	if (i < mp_irq_entries) {
		int apic;
		for(apic = 0; apic < nr_ioapics; apic++) {
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			if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
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				return apic;
		}
	}

	return -1;
}

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/*
 * Find a specific PCI IRQ entry.
 * Not an __init, possibly needed by modules
 */
static int pin_2_irq(int idx, int apic, int pin);

int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
{
	int apic, i, best_guess = -1;

	apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
		bus, slot, pin);
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	if (test_bit(bus, mp_bus_not_pci)) {
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		apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
		return -1;
	}
	for (i = 0; i < mp_irq_entries; i++) {
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		int lbus = mp_irqs[i].mp_srcbus;
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		for (apic = 0; apic < nr_ioapics; apic++)
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			if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
			    mp_irqs[i].mp_dstapic == MP_APIC_ALL)
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				break;

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		if (!test_bit(lbus, mp_bus_not_pci) &&
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		    !mp_irqs[i].mp_irqtype &&
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		    (bus == lbus) &&
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		    (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
			int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
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			if (!(apic || IO_APIC_IRQ(irq)))
				continue;

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			if (pin == (mp_irqs[i].mp_srcbusirq & 3))
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				return irq;
			/*
			 * Use the first all-but-pin matching entry as a
			 * best-guess fuzzy result for broken mptables.
			 */
			if (best_guess < 0)
				best_guess = irq;
		}
	}
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	BUG_ON(best_guess >= NR_IRQS);
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	return best_guess;
}

/* ISA interrupts are always polarity zero edge triggered,
 * when listed as conforming in the MP table. */

#define default_ISA_trigger(idx)	(0)
#define default_ISA_polarity(idx)	(0)

/* PCI interrupts are always polarity one level triggered,
 * when listed as conforming in the MP table. */

#define default_PCI_trigger(idx)	(1)
#define default_PCI_polarity(idx)	(1)

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static int MPBIOS_polarity(int idx)
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{
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	int bus = mp_irqs[idx].mp_srcbus;
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	int polarity;

	/*
	 * Determine IRQ line polarity (high active or low active):
	 */
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	switch (mp_irqs[idx].mp_irqflag & 3)
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	{
		case 0: /* conforms, ie. bus-type dependent polarity */
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			if (test_bit(bus, mp_bus_not_pci))
				polarity = default_ISA_polarity(idx);
			else
				polarity = default_PCI_polarity(idx);
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			break;
		case 1: /* high active */
		{
			polarity = 0;
			break;
		}
		case 2: /* reserved */
		{
			printk(KERN_WARNING "broken BIOS!!\n");
			polarity = 1;
			break;
		}
		case 3: /* low active */
		{
			polarity = 1;
			break;
		}
		default: /* invalid */
		{
			printk(KERN_WARNING "broken BIOS!!\n");
			polarity = 1;
			break;
		}
	}
	return polarity;
}

static int MPBIOS_trigger(int idx)
{
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	int bus = mp_irqs[idx].mp_srcbus;
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	int trigger;

	/*
	 * Determine IRQ trigger mode (edge or level sensitive):
	 */
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	switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
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	{
		case 0: /* conforms, ie. bus-type dependent */
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			if (test_bit(bus, mp_bus_not_pci))
				trigger = default_ISA_trigger(idx);
			else
				trigger = default_PCI_trigger(idx);
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			break;
		case 1: /* edge */
		{
			trigger = 0;
			break;
		}
		case 2: /* reserved */
		{
			printk(KERN_WARNING "broken BIOS!!\n");
			trigger = 1;
			break;
		}
		case 3: /* level */
		{
			trigger = 1;
			break;
		}
		default: /* invalid */
		{
			printk(KERN_WARNING "broken BIOS!!\n");
			trigger = 0;
			break;
		}
	}
	return trigger;
}

static inline int irq_polarity(int idx)
{
	return MPBIOS_polarity(idx);
}

static inline int irq_trigger(int idx)
{
	return MPBIOS_trigger(idx);
}

static int pin_2_irq(int idx, int apic, int pin)
{
	int irq, i;
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	int bus = mp_irqs[idx].mp_srcbus;
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	/*
	 * Debugging check, we are in big trouble if this message pops up!
	 */
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	if (mp_irqs[idx].mp_dstirq != pin)
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		printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");

684
	if (test_bit(bus, mp_bus_not_pci)) {
685
		irq = mp_irqs[idx].mp_srcbusirq;
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	} else {
		/*
		 * PCI IRQs are mapped in order
		 */
		i = irq = 0;
		while (i < apic)
			irq += nr_ioapic_registers[i++];
		irq += pin;
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	}
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	BUG_ON(irq >= NR_IRQS);
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	return irq;
}

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static int __assign_irq_vector(int irq, cpumask_t mask)
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{
701 702 703 704 705 706 707 708 709 710 711
	/*
	 * NOTE! The local APIC isn't very good at handling
	 * multiple interrupts at the same interrupt level.
	 * As the interrupt level is determined by taking the
	 * vector number and shifting that right by 4, we
	 * want to spread these out a bit so that they don't
	 * all fall in the same interrupt level.
	 *
	 * Also, we've got to be careful not to trash gate
	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
	 */
712
	static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
713
	unsigned int old_vector;
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	int cpu;
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	struct irq_cfg *cfg;
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	BUG_ON((unsigned)irq >= NR_IRQS);
718
	cfg = &irq_cfg[irq];
719

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	/* Only try and allocate irqs on cpus that are present */
	cpus_and(mask, mask, cpu_online_map);

723 724 725
	if ((cfg->move_in_progress) || cfg->move_cleanup_count)
		return -EBUSY;

726 727 728 729 730 731
	old_vector = cfg->vector;
	if (old_vector) {
		cpumask_t tmp;
		cpus_and(tmp, cfg->domain, mask);
		if (!cpus_empty(tmp))
			return 0;
732
	}
733 734

	for_each_cpu_mask(cpu, mask) {
735
		cpumask_t domain, new_mask;
736
		int new_cpu;
737
		int vector, offset;
738 739

		domain = vector_allocation_domain(cpu);
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		cpus_and(new_mask, domain, cpu_online_map);
741

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		vector = current_vector;
		offset = current_offset;
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next:
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		vector += 8;
746
		if (vector >= first_system_vector) {
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			/* If we run out of vectors on large boxen, must share them. */
			offset = (offset + 1) % 8;
			vector = FIRST_DEVICE_VECTOR + offset;
		}
751
		if (unlikely(current_vector == vector))
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			continue;
		if (vector == IA32_SYSCALL_VECTOR)
			goto next;
755
		for_each_cpu_mask(new_cpu, new_mask)
756
			if (per_cpu(vector_irq, new_cpu)[vector] != -1)
757
				goto next;
758
		/* Found one! */
759 760
		current_vector = vector;
		current_offset = offset;
761 762 763 764
		if (old_vector) {
			cfg->move_in_progress = 1;
			cfg->old_domain = cfg->domain;
		}
765
		for_each_cpu_mask(new_cpu, new_mask)
766
			per_cpu(vector_irq, new_cpu)[vector] = irq;
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		cfg->vector = vector;
		cfg->domain = domain;
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		return 0;
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	}
771
	return -ENOSPC;
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}

774
static int assign_irq_vector(int irq, cpumask_t mask)
775
{
776
	int err;
777
	unsigned long flags;
778

779
	spin_lock_irqsave(&vector_lock, flags);
780
	err = __assign_irq_vector(irq, mask);
781
	spin_unlock_irqrestore(&vector_lock, flags);
782
	return err;
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}

785 786
static void __clear_irq_vector(int irq)
{
787
	struct irq_cfg *cfg;
788 789 790
	cpumask_t mask;
	int cpu, vector;

791 792 793
	BUG_ON((unsigned)irq >= NR_IRQS);
	cfg = &irq_cfg[irq];
	BUG_ON(!cfg->vector);
794

795 796
	vector = cfg->vector;
	cpus_and(mask, cfg->domain, cpu_online_map);
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	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = -1;

800
	cfg->vector = 0;
801
	cpus_clear(cfg->domain);
802 803
}

804 805 806 807 808 809 810
void __setup_vector_irq(int cpu)
{
	/* Initialize vector_irq on a new cpu */
	/* This function must be called with vector_lock held */
	int irq, vector;

	/* Mark the inuse vectors */
811
	for (irq = 0; irq < NR_IRQS; ++irq) {
812
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
813
			continue;
814
		vector = irq_cfg[irq].vector;
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		per_cpu(vector_irq, cpu)[vector] = irq;
	}
	/* Mark the free vectors */
	for (vector = 0; vector < NR_VECTORS; ++vector) {
		irq = per_cpu(vector_irq, cpu)[vector];
		if (irq < 0)
			continue;
822
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
823 824 825 826 827
			per_cpu(vector_irq, cpu)[vector] = -1;
	}
}


828
static struct irq_chip ioapic_chip;
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static void ioapic_register_intr(int irq, unsigned long trigger)
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{
832 833
	if (trigger) {
		irq_desc[irq].status |= IRQ_LEVEL;
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		set_irq_chip_and_handler_name(irq, &ioapic_chip,
					      handle_fasteoi_irq, "fasteoi");
836 837
	} else {
		irq_desc[irq].status &= ~IRQ_LEVEL;
838 839
		set_irq_chip_and_handler_name(irq, &ioapic_chip,
					      handle_edge_irq, "edge");
840
	}
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}
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static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
			      int trigger, int polarity)
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{
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	struct irq_cfg *cfg = irq_cfg + irq;
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	struct IO_APIC_route_entry entry;
848
	cpumask_t mask;
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	if (!IO_APIC_IRQ(irq))
		return;

853 854
	mask = TARGET_CPUS;
	if (assign_irq_vector(irq, mask))
855 856
		return;

857 858
	cpus_and(mask, cfg->domain, mask);

859 860 861
	apic_printk(APIC_VERBOSE,KERN_DEBUG
		    "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
		    "IRQ %d Mode:%i Active:%i)\n",
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		    apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
863
		    irq, trigger, polarity);
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865 866 867 868
	/*
	 * add it to the IO-APIC irq-routing table:
	 */
	memset(&entry,0,sizeof(entry));
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	entry.delivery_mode = INT_DELIVERY_MODE;
	entry.dest_mode = INT_DEST_MODE;
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	entry.dest = cpu_mask_to_apicid(mask);
873
	entry.mask = 0;				/* enable IRQ */
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	entry.trigger = trigger;
	entry.polarity = polarity;
876
	entry.vector = cfg->vector;
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	/* Mask level triggered irqs.
	 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
	 */
	if (trigger)
882 883
		entry.mask = 1;

884 885 886
	ioapic_register_intr(irq, trigger);
	if (irq < 16)
		disable_8259A_irq(irq);
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	ioapic_write_entry(apic, pin, entry);
}

static void __init setup_IO_APIC_irqs(void)
{
	int apic, pin, idx, irq, first_notcon = 1;

	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");

	for (apic = 0; apic < nr_ioapics; apic++) {
	for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
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		idx = find_irq_entry(apic,pin,mp_INT);
		if (idx == -1) {
			if (first_notcon) {
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				apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
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				first_notcon = 0;
			} else
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				apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
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			continue;
		}
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		if (!first_notcon) {
			apic_printk(APIC_VERBOSE, " not connected.\n");
			first_notcon = 1;
		}
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		irq = pin_2_irq(idx, apic, pin);
		add_pin_to_irq(irq, apic, pin);

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		setup_IO_APIC_irq(apic, pin, irq,
				  irq_trigger(idx), irq_polarity(idx));
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	}
	}

	if (!first_notcon)
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		apic_printk(APIC_VERBOSE, " not connected.\n");
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}

/*
927
 * Set up the timer pin, possibly with the 8259A-master behind.
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 */
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static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
					int vector)
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{
	struct IO_APIC_route_entry entry;

934
	memset(&entry, 0, sizeof(entry));
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	/*
	 * We use logical delivery to get the timer IRQ
	 * to the first CPU.
	 */
	entry.dest_mode = INT_DEST_MODE;
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	entry.mask = 1;					/* mask IRQ now */
942
	entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
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	entry.delivery_mode = INT_DELIVERY_MODE;
	entry.polarity = 0;
	entry.trigger = 0;
	entry.vector = vector;

	/*
	 * The timer IRQ doesn't have to know that behind the
950
	 * scene we may have a 8259A-master in AEOI mode ...
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	 */
952
	set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
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	/*
	 * Add it to the IO-APIC irq-routing table:
	 */
957
	ioapic_write_entry(apic, pin, entry);
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}

void __apicdebuginit print_IO_APIC(void)
{
	int apic, i;
	union IO_APIC_reg_00 reg_00;
	union IO_APIC_reg_01 reg_01;
	union IO_APIC_reg_02 reg_02;
	unsigned long flags;

	if (apic_verbosity == APIC_QUIET)
		return;

	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
	for (i = 0; i < nr_ioapics; i++)
		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
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		       mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
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	/*
	 * We are a bit conservative about what we expect.  We have to
	 * know about every hardware change ASAP.
	 */
	printk(KERN_INFO "testing the IO APIC.......................\n");

	for (apic = 0; apic < nr_ioapics; apic++) {

	spin_lock_irqsave(&ioapic_lock, flags);
	reg_00.raw = io_apic_read(apic, 0);
	reg_01.raw = io_apic_read(apic, 1);
	if (reg_01.bits.version >= 0x10)
		reg_02.raw = io_apic_read(apic, 2);
	spin_unlock_irqrestore(&ioapic_lock, flags);

	printk("\n");
992
	printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
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	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);

	printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
	printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);

	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
	printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);

	if (reg_01.bits.version >= 0x10) {
		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
	}

	printk(KERN_DEBUG ".... IRQ redirection table:\n");

1009 1010
	printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
			  " Stat Dmod Deli Vect:   \n");
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	for (i = 0; i <= reg_01.bits.entries; i++) {
		struct IO_APIC_route_entry entry;

1015
		entry = ioapic_read_entry(apic, i);
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		printk(KERN_DEBUG " %02x %03X ",
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			i,
1019
			entry.dest
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		);

		printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
			entry.mask,
			entry.trigger,
			entry.irr,
			entry.polarity,
			entry.delivery_status,
			entry.dest_mode,
			entry.delivery_mode,
			entry.vector
		);
	}
	}
	printk(KERN_DEBUG "IRQ to pin mappings:\n");
	for (i = 0; i < NR_IRQS; i++) {
		struct irq_pin_list *entry = irq_2_pin + i;
		if (entry->pin < 0)
			continue;
1039
		printk(KERN_DEBUG "IRQ%d ", i);
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		for (;;) {
			printk("-> %d:%d", entry->apic, entry->pin);
			if (!entry->next)
				break;
			entry = irq_2_pin + entry->next;
		}
		printk("\n");
	}

	printk(KERN_INFO ".................................... done.\n");

	return;
}

#if 0

static __apicdebuginit void print_APIC_bitfield (int base)
{
	unsigned int v;
	int i, j;

	if (apic_verbosity == APIC_QUIET)
		return;

	printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
	for (i = 0; i < 8; i++) {
		v = apic_read(base + i*0x10);
		for (j = 0; j < 32; j++) {
			if (v & (1<<j))
				printk("1");
			else
				printk("0");
		}
		printk("\n");
	}
}

void __apicdebuginit print_local_APIC(void * dummy)
{
	unsigned int v, ver, maxlvt;

	if (apic_verbosity == APIC_QUIET)
		return;

	printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
		smp_processor_id(), hard_smp_processor_id());
1086
	v = apic_read(APIC_ID);
1087
	printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
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	v = apic_read(APIC_LVR);
	printk(KERN_INFO "... APIC VERSION: %08x\n", v);
	ver = GET_APIC_VERSION(v);
1091
	maxlvt = lapic_get_maxlvt();
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	v = apic_read(APIC_TASKPRI);
	printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);

1096 1097 1098 1099 1100
	v = apic_read(APIC_ARBPRI);
	printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
		v & APIC_ARBPRI_MASK);
	v = apic_read(APIC_PROCPRI);
	printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
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	v = apic_read(APIC_EOI);
	printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
	v = apic_read(APIC_RRR);
	printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
	v = apic_read(APIC_LDR);
	printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
	v = apic_read(APIC_DFR);
	printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
	v = apic_read(APIC_SPIV);
	printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);

	printk(KERN_DEBUG "... APIC ISR field:\n");
	print_APIC_bitfield(APIC_ISR);
	printk(KERN_DEBUG "... APIC TMR field:\n");
	print_APIC_bitfield(APIC_TMR);
	printk(KERN_DEBUG "... APIC IRR field:\n");
	print_APIC_bitfield(APIC_IRR);

1120 1121
	v = apic_read(APIC_ESR);
	printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
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	v = apic_read(APIC_ICR);
	printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
	v = apic_read(APIC_ICR2);
	printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);

	v = apic_read(APIC_LVTT);
	printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);

	if (maxlvt > 3) {                       /* PC is LVT#4. */
		v = apic_read(APIC_LVTPC);
		printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
	}
	v = apic_read(APIC_LVT0);
	printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
	v = apic_read(APIC_LVT1);
	printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);

	if (maxlvt > 2) {			/* ERR is LVT#3. */
		v = apic_read(APIC_LVTERR);
		printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
	}

	v = apic_read(APIC_TMICT);
	printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
	v = apic_read(APIC_TMCCT);
	printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
	v = apic_read(APIC_TDCR);
	printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
	printk("\n");
}

void print_all_local_APICs (void)
{
	on_each_cpu(print_local_APIC, NULL, 1, 1);
}

void __apicdebuginit print_PIC(void)
{
	unsigned int v;
	unsigned long flags;

	if (apic_verbosity == APIC_QUIET)
		return;

	printk(KERN_DEBUG "\nprinting PIC contents\n");

	spin_lock_irqsave(&i8259A_lock, flags);

	v = inb(0xa1) << 8 | inb(0x21);
	printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);

	v = inb(0xa0) << 8 | inb(0x20);
	printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);

	outb(0x0b,0xa0);
	outb(0x0b,0x20);
	v = inb(0xa0) << 8 | inb(0x20);
	outb(0x0a,0xa0);
	outb(0x0a,0x20);

	spin_unlock_irqrestore(&i8259A_lock, flags);

	printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);

	v = inb(0x4d1) << 8 | inb(0x4d0);
	printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
}

#endif  /*  0  */

1193
void __init enable_IO_APIC(void)
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{
	union IO_APIC_reg_01 reg_01;
1196 1197
	int i8259_apic, i8259_pin;
	int i, apic;
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	unsigned long flags;

	for (i = 0; i < PIN_MAP_SIZE; i++) {
		irq_2_pin[i].pin = -1;
		irq_2_pin[i].next = 0;
	}

	/*
	 * The number of IO-APIC IRQ registers (== #pins):
	 */
1208
	for (apic = 0; apic < nr_ioapics; apic++) {
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		spin_lock_irqsave(&ioapic_lock, flags);
1210
		reg_01.raw = io_apic_read(apic, 1);
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		spin_unlock_irqrestore(&ioapic_lock, flags);
1212 1213 1214 1215 1216 1217 1218
		nr_ioapic_registers[apic] = reg_01.bits.entries+1;
	}
	for(apic = 0; apic < nr_ioapics; apic++) {
		int pin;
		/* See if any of the pins is in ExtINT mode */
		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
			struct IO_APIC_route_entry entry;
1219
			entry = ioapic_read_entry(apic, pin);
1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245

			/* If the interrupt line is enabled and in ExtInt mode
			 * I have found the pin where the i8259 is connected.
			 */
			if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
				ioapic_i8259.apic = apic;
				ioapic_i8259.pin  = pin;
				goto found_i8259;
			}
		}
	}
 found_i8259:
	/* Look to see what if the MP table has reported the ExtINT */
	i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
	i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
	/* Trust the MP table if nothing is setup in the hardware */
	if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
		printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
		ioapic_i8259.pin  = i8259_pin;
		ioapic_i8259.apic = i8259_apic;
	}
	/* Complain if the MP table and the hardware disagree */
	if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
		(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
	{
		printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
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	}

	/*
	 * Do not trust the IO-APIC being empty at bootup
	 */
	clear_IO_APIC();
}

/*
 * Not an __init, needed by the reboot code
 */
void disable_IO_APIC(void)
{
	/*
	 * Clear the IO-APIC before rebooting:
	 */
	clear_IO_APIC();

1264
	/*
1265
	 * If the i8259 is routed through an IOAPIC
1266
	 * Put that IOAPIC in virtual wire mode
1267
	 * so legacy interrupts can be delivered.
1268
	 */
1269
	if (ioapic_i8259.pin != -1) {
1270 1271 1272 1273 1274 1275 1276 1277 1278
		struct IO_APIC_route_entry entry;

		memset(&entry, 0, sizeof(entry));
		entry.mask            = 0; /* Enabled */
		entry.trigger         = 0; /* Edge */
		entry.irr             = 0;
		entry.polarity        = 0; /* High */
		entry.delivery_status = 0;
		entry.dest_mode       = 0; /* Physical */
1279
		entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1280
		entry.vector          = 0;
1281
		entry.dest          = GET_APIC_ID(read_apic_id());
1282 1283 1284 1285

		/*
		 * Add it to the IO-APIC irq-routing table:
		 */
1286
		ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1287 1288
	}

1289
	disconnect_bsp_APIC(ioapic_i8259.pin != -1);
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}

/*
 * There is a nasty bug in some older SMP boards, their mptable lies
 * about the timer IRQ. We do the following to work around the situation:
 *
 *	- timer IRQ defaults to IO-APIC IRQ
 *	- if this function detects that timer IRQs are defunct, then we fall
 *	  back to ISA timer IRQs
 */
static int __init timer_irq_works(void)
{
	unsigned long t1 = jiffies;
1303
	unsigned long flags;
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1304

1305
	local_save_flags(flags);
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	local_irq_enable();
	/* Let ten ticks pass... */
	mdelay((10 * 1000) / HZ);
1309
	local_irq_restore(flags);
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	/*
	 * Expect a few ticks at least, to be sure some possible
	 * glue logic does not lock up after one or two first
	 * ticks in a non-ExtINT mode.  Also the local APIC
	 * might have cached one ExtINT interrupt.  Finally, at
	 * least one tick may be lost due to delays.
	 */

	/* jiffies wrap? */
1320
	if (time_after(jiffies, t1 + 4))
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		return 1;
	return 0;
}

/*
 * In the SMP+IOAPIC case it might happen that there are an unspecified
 * number of pending IRQ events unhandled. These cases are very rare,
 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
 * better to do it this way as thus we do not have to be aware of
 * 'pending' interrupts in the IRQ path, except at this point.
 */
/*
 * Edge triggered needs to resend any interrupt
 * that was delayed but this is now handled in the device
 * independent code.
 */

/*
 * Starting up a edge-triggered IO-APIC interrupt is
 * nasty - we need to make sure that we get the edge.
 * If it is already asserted for some reason, we need
 * return 1 to indicate that is was pending.
 *
 * This is not complete - we should be able to fake
 * an edge even if it isn't on the 8259A...
 */

1348
static unsigned int startup_ioapic_irq(unsigned int irq)
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{
	int was_pending = 0;
	unsigned long flags;

	spin_lock_irqsave(&ioapic_lock, flags);
	if (irq < 16) {
		disable_8259A_irq(irq);
		if (i8259A_irq_pending(irq))
			was_pending = 1;
	}
	__unmask_IO_APIC_irq(irq);
	spin_unlock_irqrestore(&ioapic_lock, flags);

	return was_pending;
}

1365
static int ioapic_retrigger_irq(unsigned int irq)
1366
{
1367
	struct irq_cfg *cfg = &irq_cfg[irq];
1368
	cpumask_t mask;
1369
	unsigned long flags;
1370

1371
	spin_lock_irqsave(&vector_lock, flags);
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Akinobu Mita 已提交
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	mask = cpumask_of_cpu(first_cpu(cfg->domain));
1373
	send_IPI_mask(mask, cfg->vector);
1374
	spin_unlock_irqrestore(&vector_lock, flags);
1375 1376 1377 1378

	return 1;
}

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/*
 * Level and edge triggered IO-APIC interrupts need different handling,
 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
 * handled with the level-triggered descriptor, but that one has slightly
 * more overhead. Level-triggered interrupts cannot be handled with the
 * edge-triggered handler, without risking IRQ storms and other ugly
 * races.
 */

1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430
#ifdef CONFIG_SMP
asmlinkage void smp_irq_move_cleanup_interrupt(void)
{
	unsigned vector, me;
	ack_APIC_irq();
	exit_idle();
	irq_enter();

	me = smp_processor_id();
	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
		unsigned int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __get_cpu_var(vector_irq)[vector];
		if (irq >= NR_IRQS)
			continue;

		desc = irq_desc + irq;
		cfg = irq_cfg + irq;
		spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
			goto unlock;

		__get_cpu_var(vector_irq)[vector] = -1;
		cfg->move_cleanup_count--;
unlock:
		spin_unlock(&desc->lock);
	}

	irq_exit();
}

static void irq_complete_move(unsigned int irq)
{
	struct irq_cfg *cfg = irq_cfg + irq;
	unsigned vector, me;

	if (likely(!cfg->move_in_progress))
		return;

1431
	vector = ~get_irq_regs()->orig_ax;
1432
	me = smp_processor_id();
1433
	if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445
		cpumask_t cleanup_mask;

		cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
		cfg->move_cleanup_count = cpus_weight(cleanup_mask);
		send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
		cfg->move_in_progress = 0;
	}
}
#else
static inline void irq_complete_move(unsigned int irq) {}
#endif

1446 1447
static void ack_apic_edge(unsigned int irq)
{
1448
	irq_complete_move(irq);
1449 1450 1451 1452 1453 1454 1455 1456
	move_native_irq(irq);
	ack_APIC_irq();
}

static void ack_apic_level(unsigned int irq)
{
	int do_unmask_irq = 0;

1457
	irq_complete_move(irq);
1458
#ifdef CONFIG_GENERIC_PENDING_IRQ
1459 1460 1461 1462 1463 1464 1465 1466 1467
	/* If we are moving the irq we need to mask it */
	if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
		do_unmask_irq = 1;
		mask_IO_APIC_irq(irq);
	}
#endif

	/*
	 * We must acknowledge the irq before we move it or the acknowledge will
1468
	 * not propagate properly.
1469 1470 1471 1472
	 */
	ack_APIC_irq();

	/* Now we can move and renable the irq */
1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
	if (unlikely(do_unmask_irq)) {
		/* Only migrate the irq if the ack has been received.
		 *
		 * On rare occasions the broadcast level triggered ack gets
		 * delayed going to ioapics, and if we reprogram the
		 * vector while Remote IRR is still set the irq will never
		 * fire again.
		 *
		 * To prevent this scenario we read the Remote IRR bit
		 * of the ioapic.  This has two effects.
		 * - On any sane system the read of the ioapic will
		 *   flush writes (and acks) going to the ioapic from
		 *   this cpu.
		 * - We get to see if the ACK has actually been delivered.
		 *
		 * Based on failed experiments of reprogramming the
		 * ioapic entry from outside of irq context starting
		 * with masking the ioapic entry and then polling until
		 * Remote IRR was clear before reprogramming the
		 * ioapic I don't trust the Remote IRR bit to be
		 * completey accurate.
		 *
		 * However there appears to be no other way to plug
		 * this race, so if the Remote IRR bit is not
		 * accurate and is causing problems then it is a hardware bug
		 * and you can go talk to the chipset vendor about it.
		 */
		if (!io_apic_level_ack_pending(irq))
			move_masked_irq(irq);
1502
		unmask_IO_APIC_irq(irq);
1503
	}
1504 1505
}

1506 1507
static struct irq_chip ioapic_chip __read_mostly = {
	.name 		= "IO-APIC",
1508 1509 1510
	.startup 	= startup_ioapic_irq,
	.mask	 	= mask_IO_APIC_irq,
	.unmask	 	= unmask_IO_APIC_irq,
1511 1512
	.ack 		= ack_apic_edge,
	.eoi 		= ack_apic_level,
1513
#ifdef CONFIG_SMP
1514
	.set_affinity 	= set_ioapic_affinity_irq,
1515
#endif
1516
	.retrigger	= ioapic_retrigger_irq,
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};

static inline void init_IO_APIC_traps(void)
{
	int irq;

	/*
	 * NOTE! The local APIC isn't very good at handling
	 * multiple interrupts at the same interrupt level.
	 * As the interrupt level is determined by taking the
	 * vector number and shifting that right by 4, we
	 * want to spread these out a bit so that they don't
	 * all fall in the same interrupt level.
	 *
	 * Also, we've got to be careful not to trash gate
	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
	 */
	for (irq = 0; irq < NR_IRQS ; irq++) {
1535
		if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
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			/*
			 * Hmm.. We don't have an entry for this,
			 * so default to an old-fashioned 8259
			 * interrupt if we can..
			 */
			if (irq < 16)
				make_8259A_irq(irq);
			else
				/* Strange. Oh, well.. */
1545
				irq_desc[irq].chip = &no_irq_chip;
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		}
	}
}

static void enable_lapic_irq (unsigned int irq)
{
	unsigned long v;

	v = apic_read(APIC_LVT0);
1555
	apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
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}

static void disable_lapic_irq (unsigned int irq)
{
	unsigned long v;

	v = apic_read(APIC_LVT0);
1563
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
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}

static void ack_lapic_irq (unsigned int irq)
{
	ack_APIC_irq();
}

static void end_lapic_irq (unsigned int i) { /* nothing */ }

1573
static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1574
	.name = "local-APIC",
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	.typename = "local-APIC-edge",
	.startup = NULL, /* startup_irq() not used for IRQ0 */
	.shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
	.enable = enable_lapic_irq,
	.disable = disable_lapic_irq,
	.ack = ack_lapic_irq,
	.end = end_lapic_irq,
};

1584
static void __init setup_nmi(void)
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{
	/*
 	 * Dirty trick to enable the NMI watchdog ...
	 * We put the 8259A master into AEOI mode and
	 * unmask on all local APICs LVT0 as NMI.
	 *
	 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
	 * is from Maciej W. Rozycki - so we do not have to EOI from
	 * the NMI handler or the timer interrupt.
	 */ 
	printk(KERN_INFO "activating NMI Watchdog ...");

1597
	enable_NMI_through_LVT0();
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	printk(" done.\n");
}

/*
 * This looks a bit hackish but it's about the only one way of sending
 * a few INTA cycles to 8259As and any associated glue logic.  ICR does
 * not support the ExtINT mode, unfortunately.  We need to send these
 * cycles as some i82489DX-based boards have glue logic that keeps the
 * 8259A interrupt line asserted until INTA.  --macro
 */
J
Jacek Luczak 已提交
1609
static inline void __init unlock_ExtINT_logic(void)
L
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1610
{
1611
	int apic, pin, i;
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	struct IO_APIC_route_entry entry0, entry1;
	unsigned char save_control, save_freq_select;

1615 1616
	pin  = find_isa_irq_pin(8, mp_INT);
	apic = find_isa_irq_apic(8, mp_INT);
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	if (pin == -1)
		return;

1620 1621
	entry0 = ioapic_read_entry(apic, pin);

1622
	clear_IO_APIC_pin(apic, pin);
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	memset(&entry1, 0, sizeof(entry1));

	entry1.dest_mode = 0;			/* physical delivery */
	entry1.mask = 0;			/* unmask IRQ now */
1628
	entry1.dest = hard_smp_processor_id();
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	entry1.delivery_mode = dest_ExtINT;
	entry1.polarity = entry0.polarity;
	entry1.trigger = 0;
	entry1.vector = 0;

1634
	ioapic_write_entry(apic, pin, entry1);
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	save_control = CMOS_READ(RTC_CONTROL);
	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
		   RTC_FREQ_SELECT);
	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);

	i = 100;
	while (i-- > 0) {
		mdelay(10);
		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
			i -= 10;
	}

	CMOS_WRITE(save_control, RTC_CONTROL);
	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1651
	clear_IO_APIC_pin(apic, pin);
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1652

1653
	ioapic_write_entry(apic, pin, entry0);
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}

/*
 * This code may look a bit paranoid, but it's supposed to cooperate with
 * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
 * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
 * fanatically on his truly buggy board.
1661 1662
 *
 * FIXME: really need to revamp this for modern platforms only.
L
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1663
 */
1664
static inline void __init check_timer(void)
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1665
{
1666
	struct irq_cfg *cfg = irq_cfg + 0;
1667
	int apic1, pin1, apic2, pin2;
1668
	unsigned long flags;
1669
	int no_pin1 = 0;
1670 1671

	local_irq_save(flags);
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	/*
	 * get/set the timer IRQ vector:
	 */
	disable_8259A_irq(0);
1677
	assign_irq_vector(0, TARGET_CPUS);
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	/*
1680 1681
	 * As IRQ0 is to be enabled in the 8259A, the virtual
	 * wire has to be disabled in the local APIC.
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1682
	 */
1683
	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
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1684 1685
	init_8259A(1);

1686 1687 1688 1689
	pin1  = find_isa_irq_pin(0, mp_INT);
	apic1 = find_isa_irq_apic(0, mp_INT);
	pin2  = ioapic_i8259.pin;
	apic2 = ioapic_i8259.apic;
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1691
	apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1692
		cfg->vector, apic1, pin1, apic2, pin2);
1693

1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709
	/*
	 * Some BIOS writers are clueless and report the ExtINTA
	 * I/O APIC input from the cascaded 8259A as the timer
	 * interrupt input.  So just in case, if only one pin
	 * was found above, try it both directly and through the
	 * 8259A.
	 */
	if (pin1 == -1) {
		pin1 = pin2;
		apic1 = apic2;
		no_pin1 = 1;
	} else if (pin2 == -1) {
		pin2 = pin1;
		apic2 = apic1;
	}

1710 1711 1712 1713 1714
	replace_pin_at_irq(0, 0, 0, apic1, pin1);
	apic1 = 0;
	pin1 = 0;
	setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);

1715 1716 1717 1718
	if (pin1 != -1) {
		/*
		 * Ok, does IRQ0 through the IOAPIC work?
		 */
1719 1720
		if (no_pin1) {
			add_pin_to_irq(0, apic1, pin1);
I
Ingo Molnar 已提交
1721
			setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1722
		}
1723 1724 1725 1726 1727 1728 1729 1730 1731
		unmask_IO_APIC_irq(0);
		if (!no_timer_check && timer_irq_works()) {
			nmi_watchdog_default();
			if (nmi_watchdog == NMI_IO_APIC) {
				setup_nmi();
				enable_8259A_irq(0);
			}
			if (disable_timer_pin_1 > 0)
				clear_IO_APIC_pin(0, pin1);
1732
			goto out;
1733 1734
		}
		clear_IO_APIC_pin(apic1, pin1);
1735 1736 1737
		if (!no_pin1)
			apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
				    "8254 timer not connected to IO-APIC\n");
L
Linus Torvalds 已提交
1738

1739 1740 1741
		apic_printk(APIC_VERBOSE,KERN_INFO
			"...trying to set up timer (IRQ0) "
			"through the 8259A ... ");
1742 1743 1744 1745 1746
		apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
			apic2, pin2);
		/*
		 * legacy devices should be connected to IO APIC #0
		 */
1747
		replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1748
		setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1749
		unmask_IO_APIC_irq(0);
1750
		enable_8259A_irq(0);
1751 1752
		if (timer_irq_works()) {
			apic_printk(APIC_VERBOSE," works.\n");
1753
			timer_through_8259 = 1;
1754 1755
			nmi_watchdog_default();
			if (nmi_watchdog == NMI_IO_APIC) {
1756
				disable_8259A_irq(0);
1757
				setup_nmi();
1758
				enable_8259A_irq(0);
1759
			}
1760
			goto out;
1761 1762 1763 1764
		}
		/*
		 * Cleanup, just in case ...
		 */
1765
		disable_8259A_irq(0);
1766
		clear_IO_APIC_pin(apic2, pin2);
1767
		apic_printk(APIC_VERBOSE," failed.\n");
L
Linus Torvalds 已提交
1768 1769
	}

1770
	if (nmi_watchdog == NMI_IO_APIC) {
L
Linus Torvalds 已提交
1771
		printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1772
		nmi_watchdog = NMI_NONE;
L
Linus Torvalds 已提交
1773 1774 1775 1776
	}

	apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");

1777
	irq_desc[0].chip = &lapic_irq_type;
1778
	apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);	/* Fixed mode */
L
Linus Torvalds 已提交
1779 1780 1781
	enable_8259A_irq(0);

	if (timer_irq_works()) {
1782
		apic_printk(APIC_VERBOSE," works.\n");
1783
		goto out;
L
Linus Torvalds 已提交
1784
	}
1785
	disable_8259A_irq(0);
1786
	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
L
Linus Torvalds 已提交
1787 1788 1789 1790 1791 1792
	apic_printk(APIC_VERBOSE," failed.\n");

	apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");

	init_8259A(0);
	make_8259A_irq(0);
1793
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
1794 1795 1796 1797 1798

	unlock_ExtINT_logic();

	if (timer_irq_works()) {
		apic_printk(APIC_VERBOSE," works.\n");
1799
		goto out;
L
Linus Torvalds 已提交
1800 1801 1802
	}
	apic_printk(APIC_VERBOSE," failed :(.\n");
	panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1803 1804
out:
	local_irq_restore(flags);
L
Linus Torvalds 已提交
1805 1806
}

1807 1808 1809 1810 1811 1812 1813
static int __init notimercheck(char *s)
{
	no_timer_check = 1;
	return 1;
}
__setup("no_timer_check", notimercheck);

L
Linus Torvalds 已提交
1814 1815
/*
 *
S
Simon Arlott 已提交
1816
 * IRQs that are handled by the PIC in the MPS IOAPIC case.
L
Linus Torvalds 已提交
1817 1818 1819 1820 1821 1822 1823 1824
 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
 *   Linux doesn't really care, as it's not actually used
 *   for any interrupt handling anyway.
 */
#define PIC_IRQS	(1<<2)

void __init setup_IO_APIC(void)
{
1825 1826 1827 1828

	/*
	 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
	 */
L
Linus Torvalds 已提交
1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850

	if (acpi_ioapic)
		io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
	else
		io_apic_irqs = ~PIC_IRQS;

	apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");

	sync_Arb_IDs();
	setup_IO_APIC_irqs();
	init_IO_APIC_traps();
	check_timer();
	if (!acpi_ioapic)
		print_IO_APIC();
}

struct sysfs_ioapic_data {
	struct sys_device dev;
	struct IO_APIC_route_entry entry[0];
};
static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];

1851
static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
L
Linus Torvalds 已提交
1852 1853 1854 1855 1856 1857 1858
{
	struct IO_APIC_route_entry *entry;
	struct sysfs_ioapic_data *data;
	int i;

	data = container_of(dev, struct sysfs_ioapic_data, dev);
	entry = data->entry;
1859 1860
	for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
		*entry = ioapic_read_entry(dev->id, i);
L
Linus Torvalds 已提交
1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877

	return 0;
}

static int ioapic_resume(struct sys_device *dev)
{
	struct IO_APIC_route_entry *entry;
	struct sysfs_ioapic_data *data;
	unsigned long flags;
	union IO_APIC_reg_00 reg_00;
	int i;

	data = container_of(dev, struct sysfs_ioapic_data, dev);
	entry = data->entry;

	spin_lock_irqsave(&ioapic_lock, flags);
	reg_00.raw = io_apic_read(dev->id, 0);
1878 1879
	if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
		reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
L
Linus Torvalds 已提交
1880 1881 1882
		io_apic_write(dev->id, 0, reg_00.raw);
	}
	spin_unlock_irqrestore(&ioapic_lock, flags);
1883 1884
	for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
		ioapic_write_entry(dev->id, i, entry[i]);
L
Linus Torvalds 已提交
1885 1886 1887 1888 1889

	return 0;
}

static struct sysdev_class ioapic_sysdev_class = {
1890
	.name = "ioapic",
L
Linus Torvalds 已提交
1891 1892 1893 1894 1895 1896 1897
	.suspend = ioapic_suspend,
	.resume = ioapic_resume,
};

static int __init ioapic_init_sysfs(void)
{
	struct sys_device * dev;
1898
	int i, size, error;
L
Linus Torvalds 已提交
1899 1900 1901 1902 1903 1904 1905 1906

	error = sysdev_class_register(&ioapic_sysdev_class);
	if (error)
		return error;

	for (i = 0; i < nr_ioapics; i++ ) {
		size = sizeof(struct sys_device) + nr_ioapic_registers[i]
			* sizeof(struct IO_APIC_route_entry);
1907
		mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
L
Linus Torvalds 已提交
1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928
		if (!mp_ioapic_data[i]) {
			printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
			continue;
		}
		dev = &mp_ioapic_data[i]->dev;
		dev->id = i;
		dev->cls = &ioapic_sysdev_class;
		error = sysdev_register(dev);
		if (error) {
			kfree(mp_ioapic_data[i]);
			mp_ioapic_data[i] = NULL;
			printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
			continue;
		}
	}

	return 0;
}

device_initcall(ioapic_init_sysfs);

1929
/*
1930
 * Dynamic irq allocate and deallocation
1931 1932 1933
 */
int create_irq(void)
{
1934 1935 1936
	/* Allocate an unused irq */
	int irq;
	int new;
1937 1938
	unsigned long flags;

1939 1940 1941 1942 1943
	irq = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for (new = (NR_IRQS - 1); new >= 0; new--) {
		if (platform_legacy_irq(new))
			continue;
1944
		if (irq_cfg[new].vector != 0)
1945
			continue;
1946
		if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1947 1948 1949 1950
			irq = new;
		break;
	}
	spin_unlock_irqrestore(&vector_lock, flags);
1951

1952
	if (irq >= 0) {
1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964
		dynamic_irq_init(irq);
	}
	return irq;
}

void destroy_irq(unsigned int irq)
{
	unsigned long flags;

	dynamic_irq_cleanup(irq);

	spin_lock_irqsave(&vector_lock, flags);
1965
	__clear_irq_vector(irq);
1966 1967 1968
	spin_unlock_irqrestore(&vector_lock, flags);
}

1969
/*
S
Simon Arlott 已提交
1970
 * MSI message composition
1971 1972
 */
#ifdef CONFIG_PCI_MSI
1973
static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1974
{
1975 1976
	struct irq_cfg *cfg = irq_cfg + irq;
	int err;
1977
	unsigned dest;
1978
	cpumask_t tmp;
1979

1980 1981 1982 1983
	tmp = TARGET_CPUS;
	err = assign_irq_vector(irq, tmp);
	if (!err) {
		cpus_and(tmp, cfg->domain, tmp);
1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002
		dest = cpu_mask_to_apicid(tmp);

		msg->address_hi = MSI_ADDR_BASE_HI;
		msg->address_lo =
			MSI_ADDR_BASE_LO |
			((INT_DEST_MODE == 0) ?
				MSI_ADDR_DEST_MODE_PHYSICAL:
				MSI_ADDR_DEST_MODE_LOGICAL) |
			((INT_DELIVERY_MODE != dest_LowestPrio) ?
				MSI_ADDR_REDIRECTION_CPU:
				MSI_ADDR_REDIRECTION_LOWPRI) |
			MSI_ADDR_DEST_ID(dest);

		msg->data =
			MSI_DATA_TRIGGER_EDGE |
			MSI_DATA_LEVEL_ASSERT |
			((INT_DELIVERY_MODE != dest_LowestPrio) ?
				MSI_DATA_DELIVERY_FIXED:
				MSI_DATA_DELIVERY_LOWPRI) |
2003
			MSI_DATA_VECTOR(cfg->vector);
2004
	}
2005
	return err;
2006 2007
}

2008 2009
#ifdef CONFIG_SMP
static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2010
{
2011
	struct irq_cfg *cfg = irq_cfg + irq;
2012 2013 2014 2015 2016 2017
	struct msi_msg msg;
	unsigned int dest;
	cpumask_t tmp;

	cpus_and(tmp, mask, cpu_online_map);
	if (cpus_empty(tmp))
2018
		return;
2019

2020
	if (assign_irq_vector(irq, mask))
2021
		return;
2022

2023
	cpus_and(tmp, cfg->domain, mask);
2024
	dest = cpu_mask_to_apicid(tmp);
2025

2026 2027 2028
	read_msi_msg(irq, &msg);

	msg.data &= ~MSI_DATA_VECTOR_MASK;
2029
	msg.data |= MSI_DATA_VECTOR(cfg->vector);
2030 2031 2032 2033
	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
	msg.address_lo |= MSI_ADDR_DEST_ID(dest);

	write_msi_msg(irq, &msg);
2034
	irq_desc[irq].affinity = mask;
2035
}
2036
#endif /* CONFIG_SMP */
2037

2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050
/*
 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
 * which implement the MSI or MSI-X Capability Structure.
 */
static struct irq_chip msi_chip = {
	.name		= "PCI-MSI",
	.unmask		= unmask_msi_irq,
	.mask		= mask_msi_irq,
	.ack		= ack_apic_edge,
#ifdef CONFIG_SMP
	.set_affinity	= set_msi_irq_affinity,
#endif
	.retrigger	= ioapic_retrigger_irq,
2051 2052
};

2053
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2054 2055
{
	struct msi_msg msg;
2056 2057 2058 2059 2060
	int irq, ret;
	irq = create_irq();
	if (irq < 0)
		return irq;

2061
	ret = msi_compose_msg(dev, irq, &msg);
2062 2063
	if (ret < 0) {
		destroy_irq(irq);
2064
		return ret;
2065
	}
2066

2067
	set_irq_msi(irq, desc);
2068 2069
	write_msi_msg(irq, &msg);

2070
	set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2071

2072
	return 0;
2073 2074 2075 2076
}

void arch_teardown_msi_irq(unsigned int irq)
{
2077
	destroy_irq(irq);
2078 2079
}

2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135
#ifdef CONFIG_DMAR
#ifdef CONFIG_SMP
static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
{
	struct irq_cfg *cfg = irq_cfg + irq;
	struct msi_msg msg;
	unsigned int dest;
	cpumask_t tmp;

	cpus_and(tmp, mask, cpu_online_map);
	if (cpus_empty(tmp))
		return;

	if (assign_irq_vector(irq, mask))
		return;

	cpus_and(tmp, cfg->domain, mask);
	dest = cpu_mask_to_apicid(tmp);

	dmar_msi_read(irq, &msg);

	msg.data &= ~MSI_DATA_VECTOR_MASK;
	msg.data |= MSI_DATA_VECTOR(cfg->vector);
	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
	msg.address_lo |= MSI_ADDR_DEST_ID(dest);

	dmar_msi_write(irq, &msg);
	irq_desc[irq].affinity = mask;
}
#endif /* CONFIG_SMP */

struct irq_chip dmar_msi_type = {
	.name = "DMAR_MSI",
	.unmask = dmar_msi_unmask,
	.mask = dmar_msi_mask,
	.ack = ack_apic_edge,
#ifdef CONFIG_SMP
	.set_affinity = dmar_msi_set_affinity,
#endif
	.retrigger = ioapic_retrigger_irq,
};

int arch_setup_dmar_msi(unsigned int irq)
{
	int ret;
	struct msi_msg msg;

	ret = msi_compose_msg(NULL, irq, &msg);
	if (ret < 0)
		return ret;
	dmar_msi_write(irq, &msg);
	set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
		"edge");
	return 0;
}
#endif
2136

2137
#endif /* CONFIG_PCI_MSI */
2138 2139 2140 2141 2142 2143 2144 2145 2146
/*
 * Hypertransport interrupt support
 */
#ifdef CONFIG_HT_IRQ

#ifdef CONFIG_SMP

static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
{
2147 2148
	struct ht_irq_msg msg;
	fetch_ht_irq_msg(irq, &msg);
2149

2150 2151
	msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
	msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2152

2153 2154
	msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
	msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2155

2156
	write_ht_irq_msg(irq, &msg);
2157 2158 2159 2160
}

static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
{
2161
	struct irq_cfg *cfg = irq_cfg + irq;
2162 2163 2164 2165 2166
	unsigned int dest;
	cpumask_t tmp;

	cpus_and(tmp, mask, cpu_online_map);
	if (cpus_empty(tmp))
2167
		return;
2168

2169
	if (assign_irq_vector(irq, mask))
2170 2171
		return;

2172
	cpus_and(tmp, cfg->domain, mask);
2173 2174
	dest = cpu_mask_to_apicid(tmp);

2175
	target_ht_irq(irq, dest, cfg->vector);
2176
	irq_desc[irq].affinity = mask;
2177 2178 2179
}
#endif

2180
static struct irq_chip ht_irq_chip = {
2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
	.name		= "PCI-HT",
	.mask		= mask_ht_irq,
	.unmask		= unmask_ht_irq,
	.ack		= ack_apic_edge,
#ifdef CONFIG_SMP
	.set_affinity	= set_ht_irq_affinity,
#endif
	.retrigger	= ioapic_retrigger_irq,
};

int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
{
2193 2194
	struct irq_cfg *cfg = irq_cfg + irq;
	int err;
2195
	cpumask_t tmp;
2196

2197 2198 2199
	tmp = TARGET_CPUS;
	err = assign_irq_vector(irq, tmp);
	if (!err) {
2200
		struct ht_irq_msg msg;
2201 2202
		unsigned dest;

2203
		cpus_and(tmp, cfg->domain, tmp);
2204 2205
		dest = cpu_mask_to_apicid(tmp);

2206
		msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2207

2208 2209
		msg.address_lo =
			HT_IRQ_LOW_BASE |
2210
			HT_IRQ_LOW_DEST_ID(dest) |
2211
			HT_IRQ_LOW_VECTOR(cfg->vector) |
2212 2213 2214 2215 2216 2217
			((INT_DEST_MODE == 0) ?
				HT_IRQ_LOW_DM_PHYSICAL :
				HT_IRQ_LOW_DM_LOGICAL) |
			HT_IRQ_LOW_RQEOI_EDGE |
			((INT_DELIVERY_MODE != dest_LowestPrio) ?
				HT_IRQ_LOW_MT_FIXED :
2218 2219
				HT_IRQ_LOW_MT_ARBITRATED) |
			HT_IRQ_LOW_IRQ_MASKED;
2220

2221
		write_ht_irq_msg(irq, &msg);
2222

2223 2224
		set_irq_chip_and_handler_name(irq, &ht_irq_chip,
					      handle_edge_irq, "edge");
2225
	}
2226
	return err;
2227 2228 2229
}
#endif /* CONFIG_HT_IRQ */

L
Linus Torvalds 已提交
2230 2231 2232 2233
/* --------------------------------------------------------------------------
                          ACPI-based IOAPIC Configuration
   -------------------------------------------------------------------------- */

L
Len Brown 已提交
2234
#ifdef CONFIG_ACPI
L
Linus Torvalds 已提交
2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250

#define IO_APIC_MAX_ID		0xFE

int __init io_apic_get_redir_entries (int ioapic)
{
	union IO_APIC_reg_01	reg_01;
	unsigned long flags;

	spin_lock_irqsave(&ioapic_lock, flags);
	reg_01.raw = io_apic_read(ioapic, 1);
	spin_unlock_irqrestore(&ioapic_lock, flags);

	return reg_01.bits.entries;
}


B
Bob Moore 已提交
2251
int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
L
Linus Torvalds 已提交
2252 2253 2254 2255 2256 2257 2258
{
	if (!IO_APIC_IRQ(irq)) {
		apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
			ioapic);
		return -EINVAL;
	}

2259 2260 2261 2262 2263 2264
	/*
	 * IRQs < 16 are already in the irq_2_pin[] map
	 */
	if (irq >= 16)
		add_pin_to_irq(irq, ioapic, pin);

2265
	setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
L
Linus Torvalds 已提交
2266 2267 2268 2269 2270

	return 0;
}


2271 2272 2273 2274 2275 2276 2277 2278
int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
{
	int i;

	if (skip_ioapic_setup)
		return -1;

	for (i = 0; i < mp_irq_entries; i++)
2279 2280
		if (mp_irqs[i].mp_irqtype == mp_INT &&
		    mp_irqs[i].mp_srcbusirq == bus_irq)
2281 2282 2283 2284 2285 2286 2287 2288 2289 2290
			break;
	if (i >= mp_irq_entries)
		return -1;

	*trigger = irq_trigger(i);
	*polarity = irq_polarity(i);
	return 0;
}

#endif /* CONFIG_ACPI */
L
Linus Torvalds 已提交
2291 2292 2293 2294 2295 2296

/*
 * This function currently is only a helper for the i386 smp boot process where
 * we need to reprogram the ioredtbls to cater for the cpus which have come online
 * so mask in all cases should simply be TARGET_CPUS
 */
2297
#ifdef CONFIG_SMP
L
Linus Torvalds 已提交
2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310
void __init setup_ioapic_dest(void)
{
	int pin, ioapic, irq, irq_entry;

	if (skip_ioapic_setup == 1)
		return;

	for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
		for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
			irq_entry = find_irq_entry(ioapic, pin, mp_INT);
			if (irq_entry == -1)
				continue;
			irq = pin_2_irq(irq_entry, ioapic, pin);
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			/* setup_IO_APIC_irqs could fail to get vector for some device
			 * when you have too many devices, because at that time only boot
			 * cpu is online.
			 */
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			if (!irq_cfg[irq].vector)
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				setup_IO_APIC_irq(ioapic, pin, irq,
						  irq_trigger(irq_entry),
						  irq_polarity(irq_entry));
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			else
				set_ioapic_affinity_irq(irq, TARGET_CPUS);
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Linus Torvalds 已提交
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		}

	}
}
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#endif
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#define IOAPIC_RESOURCE_NAME_SIZE 11

static struct resource *ioapic_resources;

static struct resource * __init ioapic_setup_resources(void)
{
	unsigned long n;
	struct resource *res;
	char *mem;
	int i;

	if (nr_ioapics <= 0)
		return NULL;

	n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
	n *= nr_ioapics;

	mem = alloc_bootmem(n);
	res = (void *)mem;

	if (mem != NULL) {
		mem += sizeof(struct resource) * nr_ioapics;

		for (i = 0; i < nr_ioapics; i++) {
			res[i].name = mem;
			res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
			sprintf(mem,  "IOAPIC %u", i);
			mem += IOAPIC_RESOURCE_NAME_SIZE;
		}
	}

	ioapic_resources = res;

	return res;
}

void __init ioapic_init_mappings(void)
{
	unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
	struct resource *ioapic_res;
	int i;

	ioapic_res = ioapic_setup_resources();
	for (i = 0; i < nr_ioapics; i++) {
		if (smp_found_config) {
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			ioapic_phys = mp_ioapics[i].mp_apicaddr;
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		} else {
			ioapic_phys = (unsigned long)
				alloc_bootmem_pages(PAGE_SIZE);
			ioapic_phys = __pa(ioapic_phys);
		}
		set_fixmap_nocache(idx, ioapic_phys);
		apic_printk(APIC_VERBOSE,
			    "mapped IOAPIC to %016lx (%016lx)\n",
			    __fix_to_virt(idx), ioapic_phys);
		idx++;

		if (ioapic_res != NULL) {
			ioapic_res->start = ioapic_phys;
			ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
			ioapic_res++;
		}
	}
}

static int __init ioapic_insert_resources(void)
{
	int i;
	struct resource *r = ioapic_resources;

	if (!r) {
		printk(KERN_ERR
		       "IO APIC resources could be not be allocated.\n");
		return -1;
	}

	for (i = 0; i < nr_ioapics; i++) {
		insert_resource(&iomem_resource, r);
		r++;
	}

	return 0;
}

/* Insert the IO APIC resources after PCI initialization has occured to handle
 * IO APICS that are mapped in on a BAR in PCI space. */
late_initcall(ioapic_insert_resources);