alternative.h 6.7 KB
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#ifndef _ASM_X86_ALTERNATIVE_H
#define _ASM_X86_ALTERNATIVE_H
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#include <linux/types.h>
#include <linux/stddef.h>
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#include <linux/stringify.h>
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#include <asm/asm.h>

/*
 * Alternative inline assembly for SMP.
 *
 * The LOCK_PREFIX macro defined here replaces the LOCK and
 * LOCK_PREFIX macros used everywhere in the source tree.
 *
 * SMP alternatives use the same data structures as the other
 * alternatives and the X86_FEATURE_UP flag to indicate the case of a
 * UP system running a SMP kernel.  The existing apply_alternatives()
 * works fine for patching a SMP kernel for UP.
 *
 * The SMP alternative tables can be kept after boot and contain both
 * UP and SMP versions of the instructions to allow switching back to
 * SMP at runtime, when hotplugging in a new CPU, which is especially
 * useful in virtualized environments.
 *
 * The very common lock prefix is handled as special case in a
 * separate table which is a pure address list without replacement ptr
 * and size information.  That keeps the table sizes small.
 */

#ifdef CONFIG_SMP
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#define LOCK_PREFIX_HERE \
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		".section .smp_locks,\"a\"\n"	\
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		".balign 4\n"			\
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		".long 671f - .\n" /* offset */	\
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		".previous\n"			\
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		"671:"

#define LOCK_PREFIX LOCK_PREFIX_HERE "\n\tlock; "
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#else /* ! CONFIG_SMP */
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#define LOCK_PREFIX_HERE ""
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#define LOCK_PREFIX ""
#endif

struct alt_instr {
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	s32 instr_offset;	/* original instruction */
	s32 repl_offset;	/* offset to replacement instruction */
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	u16 cpuid;		/* cpuid bit set for replacement */
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	u8  instrlen;		/* length of original instruction */
	u8  replacementlen;	/* length of new instruction, <= instrlen */
};

extern void alternative_instructions(void);
extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);

struct module;

#ifdef CONFIG_SMP
extern void alternatives_smp_module_add(struct module *mod, char *name,
					void *locks, void *locks_end,
					void *text, void *text_end);
extern void alternatives_smp_module_del(struct module *mod);
extern void alternatives_smp_switch(int smp);
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extern int alternatives_text_reserved(void *start, void *end);
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extern bool skip_smp_alternatives;
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#else
static inline void alternatives_smp_module_add(struct module *mod, char *name,
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					       void *locks, void *locks_end,
					       void *text, void *text_end) {}
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static inline void alternatives_smp_module_del(struct module *mod) {}
static inline void alternatives_smp_switch(int smp) {}
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static inline int alternatives_text_reserved(void *start, void *end)
{
	return 0;
}
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#endif	/* CONFIG_SMP */

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/* alternative assembly primitive: */
#define ALTERNATIVE(oldinstr, newinstr, feature)			\
									\
      "661:\n\t" oldinstr "\n662:\n"					\
      ".section .altinstructions,\"a\"\n"				\
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      "	 .long 661b - .\n"			/* label           */	\
      "	 .long 663f - .\n"			/* new instruction */	\
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      "	 .word " __stringify(feature) "\n"	/* feature bit     */	\
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      "	 .byte 662b-661b\n"			/* sourcelen       */	\
      "	 .byte 664f-663f\n"			/* replacementlen  */	\
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      ".previous\n"							\
      ".section .discard,\"aw\",@progbits\n"				\
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      "	 .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */	\
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      ".previous\n"							\
      ".section .altinstr_replacement, \"ax\"\n"			\
      "663:\n\t" newinstr "\n664:\n"		/* replacement     */	\
      ".previous"

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/*
 * This must be included *after* the definition of ALTERNATIVE due to
 * <asm/arch_hweight.h>
 */
#include <asm/cpufeature.h>

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/*
 * Alternative instructions for different CPU types or capabilities.
 *
 * This allows to use optimized instructions even on generic binary
 * kernels.
 *
 * length of oldinstr must be longer or equal the length of newinstr
 * It can be padded with nops as needed.
 *
 * For non barrier like inlines please define new variants
 * without volatile and memory clobber.
 */
#define alternative(oldinstr, newinstr, feature)			\
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	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) : : : "memory")
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/*
 * Alternative inline assembly with input.
 *
 * Pecularities:
 * No memory clobber here.
 * Argument numbers start with 1.
 * Best is to use constraints that are fixed size (like (%1) ... "r")
 * If you use variable sized constraints like "m" or "g" in the
 * replacement make sure to pad to the worst case length.
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 * Leaving an unused argument 0 to keep API compatibility.
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 */
#define alternative_input(oldinstr, newinstr, feature, input...)	\
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	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature)		\
		: : "i" (0), ## input)
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/* Like alternative_input, but with a single output argument */
#define alternative_io(oldinstr, newinstr, feature, output, input...)	\
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	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature)		\
		: output : "i" (0), ## input)
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/* Like alternative_io, but for replacing a direct call with another one. */
#define alternative_call(oldfunc, newfunc, feature, output, input...)	\
	asm volatile (ALTERNATIVE("call %P[old]", "call %P[new]", feature) \
		: output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)

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/*
 * use this macro(s) if you need more than one output parameter
 * in alternative_io
 */
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#define ASM_OUTPUT2(a...) a
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/*
 * use this macro if you need clobbers but no inputs in
 * alternative_{input,io,call}()
 */
#define ASM_NO_INPUT_CLOBBER(clbr...) "i" (0) : clbr

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struct paravirt_patch_site;
#ifdef CONFIG_PARAVIRT
void apply_paravirt(struct paravirt_patch_site *start,
		    struct paravirt_patch_site *end);
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#else
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static inline void apply_paravirt(struct paravirt_patch_site *start,
				  struct paravirt_patch_site *end)
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{}
#define __parainstructions	NULL
#define __parainstructions_end	NULL
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#endif
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extern void *text_poke_early(void *addr, const void *opcode, size_t len);

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/*
 * Clear and restore the kernel write-protection flag on the local CPU.
 * Allows the kernel to edit read-only pages.
 * Side-effect: any interrupt handler running between save and restore will have
 * the ability to write to read-only pages.
 *
 * Warning:
 * Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
 * no thread can be preempted in the instructions being modified (no iret to an
 * invalid instruction possible) or if the instructions are changed from a
 * consistent state to another consistent state atomically.
 * More care must be taken when modifying code in the SMP case because of
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 * Intel's errata. text_poke_smp() takes care that errata, but still
 * doesn't support NMI/MCE handler code modifying.
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 * On the local CPU you need to be protected again NMI or MCE handlers seeing an
 * inconsistent instruction while you patch.
 */
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struct text_poke_param {
	void *addr;
	const void *opcode;
	size_t len;
};

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extern void *text_poke(void *addr, const void *opcode, size_t len);
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extern void *text_poke_smp(void *addr, const void *opcode, size_t len);
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extern void text_poke_smp_batch(struct text_poke_param *params, int n);
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#endif /* _ASM_X86_ALTERNATIVE_H */