tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	intc: interrupt-controller@50041000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = < 0x50041000 0x1000 >,
		      < 0x50040100 0x0100 >;
	};

	apbdma: dma@6000a000 {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = < 0 104 0x04
			       0 105 0x04
			       0 106 0x04
			       0 107 0x04
			       0 108 0x04
			       0 109 0x04
			       0 110 0x04
			       0 111 0x04
			       0 112 0x04
			       0 113 0x04
			       0 114 0x04
			       0 115 0x04
			       0 116 0x04
			       0 117 0x04
			       0 118 0x04
			       0 119 0x04 >;
	};

	i2c@7000c000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000C000 0x100>;
		interrupts = < 0 38 0x04 >;
	};

	i2c@7000c400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000C400 0x100>;
		interrupts = < 0 84 0x04 >;
	};

	i2c@7000c500 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000C500 0x100>;
		interrupts = < 0 92 0x04 >;
	};

	i2c@7000d000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000D000 0x200>;
		interrupts = < 0 53 0x04 >;
	};

	i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = < 0 13 0x04 >;
		dma-channel = < 2 >;
	};

	i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = < 0 3 0x04 >;
		dma-channel = < 1 >;
	};

	das@70000c00 {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra20-gpio";
		reg = < 0x6000d000 0x1000 >;
		interrupts = < 0 32 0x04
			       0 33 0x04
			       0 34 0x04
			       0 35 0x04
			       0 55 0x04
			       0 87 0x04
			       0 89 0x04 >;
		#gpio-cells = <2>;
		gpio-controller;
	};

	pinmux: pinmux@70000000 {
		compatible = "nvidia,tegra20-pinmux";
		reg = < 0x70000014 0x10    /* Tri-state registers */
			0x70000080 0x20    /* Mux registers */
			0x700000a0 0x14    /* Pull-up/down registers */
			0x70000868 0xa8 >; /* Pad control registers */
	};

	serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = < 0 36 0x04 >;
	};

	serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = < 0 37 0x04 >;
	};

	serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = < 0 46 0x04 >;
	};

	serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = < 0 90 0x04 >;
	};

	serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = < 0 91 0x04 >;
	};

	emc@7000f400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = < 0 14 0x04 >;
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = < 0 15 0x04 >;
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = < 0 19 0x04 >;
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = < 0 31 0x04 >;
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = < 0 20 0x04 >;
		phy_type = "utmi";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = < 0 21 0x04 >;
		phy_type = "ulpi";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = < 0 97 0x04 >;
		phy_type = "utmi";
	};
};