smpboot.c 36.9 KB
Newer Older
1
 /*
2 3
 *	x86 SMP booting functions
 *
4
 *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
I
Ingo Molnar 已提交
5
 *	(c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
 *	Copyright 2001 Andi Kleen, SuSE Labs.
 *
 *	Much of the core SMP work is based on previous work by Thomas Radke, to
 *	whom a great many thanks are extended.
 *
 *	Thanks to Intel for making available several different Pentium,
 *	Pentium Pro and Pentium-II/Xeon MP machines.
 *	Original development of Linux SMP code supported by Caldera.
 *
 *	This code is released under the GNU General Public License version 2 or
 *	later.
 *
 *	Fixes
 *		Felix Koop	:	NR_CPUS used properly
 *		Jose Renau	:	Handle single CPU case.
 *		Alan Cox	:	By repeated request 8) - Total BogoMIPS report.
 *		Greg Wright	:	Fix for kernel stacks panic.
 *		Erich Boleyn	:	MP v1.4 and additional changes.
 *	Matthias Sattler	:	Changes for 2.1 kernel map.
 *	Michel Lespinasse	:	Changes for 2.1 kernel map.
 *	Michael Chastain	:	Change trampoline.S to gnu as.
 *		Alan Cox	:	Dumb bug: 'B' step PPro's are fine
 *		Ingo Molnar	:	Added APIC timers, based on code
 *					from Jose Renau
 *		Ingo Molnar	:	various cleanups and rewrites
 *		Tigran Aivazian	:	fixed "0.00 in /proc/uptime on SMP" bug.
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs
 *	Andi Kleen		:	Changed for SMP boot into long mode.
 *		Martin J. Bligh	: 	Added support for multi-quad systems
 *		Dave Jones	:	Report invalid combinations of Athlon CPUs.
 *		Rusty Russell	:	Hacked into shape for new "hotplug" boot process.
 *      Andi Kleen              :       Converted to new state machine.
 *	Ashok Raj		: 	CPU hotplug support
 *	Glauber Costa		:	i386 and x86_64 integration
 */

42 43
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

44 45
#include <linux/init.h>
#include <linux/smp.h>
46
#include <linux/module.h>
47
#include <linux/sched.h>
48
#include <linux/percpu.h>
G
Glauber Costa 已提交
49
#include <linux/bootmem.h>
50 51
#include <linux/err.h>
#include <linux/nmi.h>
52
#include <linux/tboot.h>
53
#include <linux/stackprotector.h>
54
#include <linux/gfp.h>
55
#include <linux/cpuidle.h>
56

57
#include <asm/acpi.h>
58
#include <asm/desc.h>
59 60
#include <asm/nmi.h>
#include <asm/irq.h>
61
#include <asm/idle.h>
62
#include <asm/realmode.h>
63 64
#include <asm/cpu.h>
#include <asm/numa.h>
65 66 67
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/mtrr.h>
68
#include <asm/mwait.h>
I
Ingo Molnar 已提交
69
#include <asm/apic.h>
70
#include <asm/io_apic.h>
71 72
#include <asm/i387.h>
#include <asm/fpu-internal.h>
73
#include <asm/setup.h>
T
Tejun Heo 已提交
74
#include <asm/uv/uv.h>
75
#include <linux/mc146818rtc.h>
76
#include <asm/i8259.h>
77
#include <asm/realmode.h>
78
#include <asm/misc.h>
79

80 81 82 83 84
/* Number of siblings per CPU package */
int smp_num_siblings = 1;
EXPORT_SYMBOL(smp_num_siblings);

/* Last level cache ID of each logical CPU */
85
DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
86 87

/* representing HT siblings of each logical CPU */
88
DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
89 90 91
EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);

/* representing HT and core siblings of each logical CPU */
92
DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
93 94
EXPORT_PER_CPU_SYMBOL(cpu_core_map);

95
DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
96

97
/* Per CPU bogomips and other parameters */
98
DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
99
EXPORT_PER_CPU_SYMBOL(cpu_info);
100

101
atomic_t init_deasserted;
102

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
{
	unsigned long flags;

	spin_lock_irqsave(&rtc_lock, flags);
	CMOS_WRITE(0xa, 0xf);
	spin_unlock_irqrestore(&rtc_lock, flags);
	local_flush_tlb();
	pr_debug("1.\n");
	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
							start_eip >> 4;
	pr_debug("2.\n");
	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
							start_eip & 0xf;
	pr_debug("3.\n");
}

static inline void smpboot_restore_warm_reset_vector(void)
{
	unsigned long flags;

	/*
	 * Install writable page 0 entry to set BIOS data area.
	 */
	local_flush_tlb();

	/*
	 * Paranoid:  Set warm reset code and vector here back
	 * to default values.
	 */
	spin_lock_irqsave(&rtc_lock, flags);
	CMOS_WRITE(0, 0xf);
	spin_unlock_irqrestore(&rtc_lock, flags);

	*((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
}

140
/*
141 142
 * Report back to the Boot Processor during boot time or to the caller processor
 * during CPU online.
143
 */
144
static void smp_callin(void)
145 146 147 148 149 150 151 152
{
	int cpuid, phys_id;

	/*
	 * If waken up by an INIT in an 82489DX configuration
	 * we may get here before an INIT-deassert IPI reaches
	 * our local APIC.  We have to wait for the IPI or we'll
	 * lock up on an APIC access.
153 154
	 *
	 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
155
	 */
156
	cpuid = smp_processor_id();
157 158 159
	if (apic->wait_for_init_deassert && cpuid)
		while (!atomic_read(&init_deasserted))
			cpu_relax();
160 161 162 163

	/*
	 * (This works even if the APIC is not enabled.)
	 */
164
	phys_id = read_apic_id();
165 166 167 168 169 170 171

	/*
	 * the boot CPU has finished the init stage and is spinning
	 * on callin_map until we finish. We are free to set up this
	 * CPU, first the APIC. (this is probably redundant on most
	 * boards)
	 */
172
	apic_ap_setup();
173

174 175 176
	/*
	 * Need to setup vector mappings before we enable interrupts.
	 */
177
	setup_vector_irq(smp_processor_id());
178 179 180 181 182 183 184

	/*
	 * Save our processor parameters. Note: this information
	 * is needed for clock calibration.
	 */
	smp_store_cpu_info(cpuid);

185 186
	/*
	 * Get our bogomips.
187 188 189
	 * Update loops_per_jiffy in cpu_data. Previous call to
	 * smp_store_cpu_info() stored a value that is close but not as
	 * accurate as the value just calculated.
190 191
	 */
	calibrate_delay();
192
	cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
193
	pr_debug("Stack at about %p\n", &cpuid);
194

195 196 197 198 199 200 201
	/*
	 * This must be done before setting cpu_online_mask
	 * or calling notify_cpu_starting.
	 */
	set_cpu_sibling_map(raw_smp_processor_id());
	wmb();

202 203
	notify_cpu_starting(cpuid);

204 205 206
	/*
	 * Allow the master to continue.
	 */
207
	cpumask_set_cpu(cpuid, cpu_callin_mask);
208 209
}

210 211
static int cpu0_logical_apicid;
static int enable_start_cpu0;
212 213 214
/*
 * Activate a secondary processor.
 */
215
static void notrace start_secondary(void *unused)
216 217 218 219 220 221
{
	/*
	 * Don't put *anything* before cpu_init(), SMP booting is too
	 * fragile that we want to limit the things done here to the
	 * most necessary things.
	 */
222
	cpu_init();
223
	x86_cpuinit.early_percpu_clock_init();
224 225
	preempt_disable();
	smp_callin();
226

227 228
	enable_start_cpu0 = 0;

229
#ifdef CONFIG_X86_32
230
	/* switch away from the initial page table */
231 232 233 234
	load_cr3(swapper_pg_dir);
	__flush_tlb_all();
#endif

235 236 237 238 239 240 241
	/* otherwise gcc will move up smp_processor_id before the cpu_init */
	barrier();
	/*
	 * Check TSC synchronization with the BP:
	 */
	check_tsc_sync_target();

242 243 244
	/*
	 * Enable the espfix hack for this CPU
	 */
245
#ifdef CONFIG_X86_ESPFIX64
246 247 248
	init_espfix_ap();
#endif

249
	/*
250 251 252
	 * We need to hold vector_lock so there the set of online cpus
	 * does not change while we are assigning vectors to cpus.  Holding
	 * this lock ensures we don't half assign or remove an irq from a cpu.
253
	 */
254
	lock_vector_lock();
255
	set_cpu_online(smp_processor_id(), true);
256
	unlock_vector_lock();
257
	cpu_set_state_online(smp_processor_id());
258
	x86_platform.nmi_init();
259

260 261 262
	/* enable local interrupts */
	local_irq_enable();

263 264
	/* to prevent fake stack check failure in clock setup */
	boot_init_stack_canary();
265

266
	x86_cpuinit.setup_percpu_clockev();
267 268

	wmb();
T
Thomas Gleixner 已提交
269
	cpu_startup_entry(CPUHP_ONLINE);
270 271
}

272 273 274 275 276 277 278 279 280
void __init smp_store_boot_cpu_info(void)
{
	int id = 0; /* CPU 0 */
	struct cpuinfo_x86 *c = &cpu_data(id);

	*c = boot_cpu_data;
	c->cpu_index = id;
}

281 282 283 284
/*
 * The bootstrap kernel entry code has set these up. Save them for
 * a given CPU
 */
285
void smp_store_cpu_info(int id)
286 287 288
{
	struct cpuinfo_x86 *c = &cpu_data(id);

289
	*c = boot_cpu_data;
290
	c->cpu_index = id;
291 292 293 294 295
	/*
	 * During boot time, CPU0 has this setup already. Save the info when
	 * bringing up AP or offlined CPU0.
	 */
	identify_secondary_cpu(c);
296 297
}

298 299 300 301 302 303 304 305
static bool
topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
{
	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;

	return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
}

306
static bool
307
topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
308
{
309 310
	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;

311
	return !WARN_ONCE(!topology_same_node(c, o),
312 313 314 315 316 317 318 319 320 321 322
		"sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
		"[node: %d != %d]. Ignoring dependency.\n",
		cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
}

#define link_mask(_m, c1, c2)						\
do {									\
	cpumask_set_cpu((c1), cpu_##_m##_mask(c2));			\
	cpumask_set_cpu((c2), cpu_##_m##_mask(c1));			\
} while (0)

323
static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
324
{
A
Andreas Herrmann 已提交
325
	if (cpu_has_topoext) {
326 327 328 329 330 331 332 333 334 335 336 337 338 339 340
		int cpu1 = c->cpu_index, cpu2 = o->cpu_index;

		if (c->phys_proc_id == o->phys_proc_id &&
		    per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
		    c->compute_unit_id == o->compute_unit_id)
			return topology_sane(c, o, "smt");

	} else if (c->phys_proc_id == o->phys_proc_id &&
		   c->cpu_core_id == o->cpu_core_id) {
		return topology_sane(c, o, "smt");
	}

	return false;
}

341
static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
342 343 344 345 346 347 348 349
{
	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;

	if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
	    per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
		return topology_sane(c, o, "llc");

	return false;
350 351
}

352 353 354 355 356 357
/*
 * Unlike the other levels, we do not enforce keeping a
 * multicore group inside a NUMA node.  If this happens, we will
 * discard the MC level of the topology later.
 */
static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
358
{
359 360
	if (c->phys_proc_id == o->phys_proc_id)
		return true;
361 362
	return false;
}
363

364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389
static struct sched_domain_topology_level numa_inside_package_topology[] = {
#ifdef CONFIG_SCHED_SMT
	{ cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
#endif
#ifdef CONFIG_SCHED_MC
	{ cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
#endif
	{ NULL, },
};
/*
 * set_sched_topology() sets the topology internal to a CPU.  The
 * NUMA topologies are layered on top of it to build the full
 * system topology.
 *
 * If NUMA nodes are observed to occur within a CPU package, this
 * function should be called.  It forces the sched domain code to
 * only use the SMT level for the CPU portion of the topology.
 * This essentially falls back to relying on NUMA information
 * from the SRAT table to describe the entire system topology
 * (except for hyperthreads).
 */
static void primarily_use_numa_for_topology(void)
{
	set_sched_topology(numa_inside_package_topology);
}

390
void set_cpu_sibling_map(int cpu)
391
{
392
	bool has_smt = smp_num_siblings > 1;
393
	bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
394
	struct cpuinfo_x86 *c = &cpu_data(cpu);
395 396
	struct cpuinfo_x86 *o;
	int i;
397

398
	cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
399

400
	if (!has_mp) {
401
		cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
402 403
		cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
		cpumask_set_cpu(cpu, cpu_core_mask(cpu));
404 405 406 407
		c->booted_cores = 1;
		return;
	}

408
	for_each_cpu(i, cpu_sibling_setup_mask) {
409 410 411 412 413
		o = &cpu_data(i);

		if ((i == cpu) || (has_smt && match_smt(c, o)))
			link_mask(sibling, cpu, i);

414
		if ((i == cpu) || (has_mp && match_llc(c, o)))
415 416
			link_mask(llc_shared, cpu, i);

417 418 419 420 421 422 423 424 425
	}

	/*
	 * This needs a separate iteration over the cpus because we rely on all
	 * cpu_sibling_mask links to be set-up.
	 */
	for_each_cpu(i, cpu_sibling_setup_mask) {
		o = &cpu_data(i);

426
		if ((i == cpu) || (has_mp && match_die(c, o))) {
427 428
			link_mask(core, cpu, i);

429 430 431
			/*
			 *  Does this new cpu bringup a new core?
			 */
432
			if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
433 434 435 436
				/*
				 * for each core in package, increment
				 * the booted_cores for this new cpu
				 */
437
				if (cpumask_first(cpu_sibling_mask(i)) == i)
438 439 440 441 442 443 444 445 446 447
					c->booted_cores++;
				/*
				 * increment the core count for all
				 * the other cpus in this package
				 */
				if (i != cpu)
					cpu_data(i).booted_cores++;
			} else if (i != cpu && !c->booted_cores)
				c->booted_cores = cpu_data(i).booted_cores;
		}
448
		if (match_die(c, o) && !topology_same_node(c, o))
449
			primarily_use_numa_for_topology();
450 451 452
	}
}

453
/* maps the cpu to the sched domain representing multi-core */
R
Rusty Russell 已提交
454
const struct cpumask *cpu_coregroup_mask(int cpu)
455
{
456
	return cpu_llc_shared_mask(cpu);
R
Rusty Russell 已提交
457 458
}

I
Ingo Molnar 已提交
459
static void impress_friends(void)
460 461 462 463 464 465
{
	int cpu;
	unsigned long bogosum = 0;
	/*
	 * Allow the user to impress friends.
	 */
466
	pr_debug("Before bogomips\n");
467
	for_each_possible_cpu(cpu)
468
		if (cpumask_test_cpu(cpu, cpu_callout_mask))
469
			bogosum += cpu_data(cpu).loops_per_jiffy;
470
	pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
471
		num_online_cpus(),
472 473 474
		bogosum/(500000/HZ),
		(bogosum/(5000/HZ))%100);

475
	pr_debug("Before bogocount - setting activated=1\n");
476 477
}

478
void __inquire_remote_apic(int apicid)
479 480
{
	unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
481
	const char * const names[] = { "ID", "VERSION", "SPIV" };
482 483 484
	int timeout;
	u32 status;

485
	pr_info("Inquiring remote APIC 0x%x...\n", apicid);
486 487

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
488
		pr_info("... APIC 0x%x %s: ", apicid, names[i]);
489 490 491 492 493 494

		/*
		 * Wait for idle.
		 */
		status = safe_apic_wait_icr_idle();
		if (status)
495
			pr_cont("a previous APIC delivery may have failed\n");
496

497
		apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
498 499 500 501 502 503 504 505 506 507

		timeout = 0;
		do {
			udelay(100);
			status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
		} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);

		switch (status) {
		case APIC_ICR_RR_VALID:
			status = apic_read(APIC_RRR);
508
			pr_cont("%08x\n", status);
509 510
			break;
		default:
511
			pr_cont("failed\n");
512 513 514 515
		}
	}
}

516 517 518 519 520 521 522 523
/*
 * The Multiprocessor Specification 1.4 (1997) example code suggests
 * that there should be a 10ms delay between the BSP asserting INIT
 * and de-asserting INIT, when starting a remote processor.
 * But that slows boot and resume on modern processors, which include
 * many cores and don't require that delay.
 *
 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
524
 * Modern processor families are quirked to remove the delay entirely.
525 526 527 528 529 530 531 532 533 534 535 536 537
 */
#define UDELAY_10MS_DEFAULT 10000

static unsigned int init_udelay = UDELAY_10MS_DEFAULT;

static int __init cpu_init_udelay(char *str)
{
	get_option(&str, &init_udelay);

	return 0;
}
early_param("cpu_init_udelay", cpu_init_udelay);

538 539 540 541 542 543 544 545 546 547 548 549
static void __init smp_quirk_init_udelay(void)
{
	/* if cmdline changed it from default, leave it alone */
	if (init_udelay != UDELAY_10MS_DEFAULT)
		return;

	/* if modern processor, use no delay */
	if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
	    ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF)))
		init_udelay = 0;
}

550 551 552 553 554
/*
 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
 * won't ... remember to clear down the APIC, etc later.
 */
555
int
556
wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
557 558 559 560 561 562 563
{
	unsigned long send_status, accept_status = 0;
	int maxlvt;

	/* Target chip */
	/* Boot on the stack */
	/* Kick the second */
564
	apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
565

566
	pr_debug("Waiting for send to finish...\n");
567 568 569 570 571 572
	send_status = safe_apic_wait_icr_idle();

	/*
	 * Give the other CPU some time to accept the IPI.
	 */
	udelay(200);
573
	if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
574 575 576 577 578
		maxlvt = lapic_get_maxlvt();
		if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
			apic_write(APIC_ESR, 0);
		accept_status = (apic_read(APIC_ESR) & 0xEF);
	}
579
	pr_debug("NMI sent\n");
580 581

	if (send_status)
582
		pr_err("APIC never delivered???\n");
583
	if (accept_status)
584
		pr_err("APIC delivery error (%lx)\n", accept_status);
585 586 587 588

	return (send_status | accept_status);
}

589
static int
590
wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
591
{
592
	unsigned long send_status = 0, accept_status = 0;
593 594
	int maxlvt, num_starts, j;

595 596
	maxlvt = lapic_get_maxlvt();

597 598 599 600
	/*
	 * Be paranoid about clearing APIC errors.
	 */
	if (APIC_INTEGRATED(apic_version[phys_apicid])) {
601 602
		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
			apic_write(APIC_ESR, 0);
603 604 605
		apic_read(APIC_ESR);
	}

606
	pr_debug("Asserting INIT\n");
607 608 609 610 611 612 613

	/*
	 * Turn INIT on target chip
	 */
	/*
	 * Send IPI
	 */
614 615
	apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
		       phys_apicid);
616

617 618
	pr_debug("Waiting for send to finish...\n");
	send_status = safe_apic_wait_icr_idle();
619

620
	udelay(init_udelay);
621

622
	pr_debug("Deasserting INIT\n");
623

624 625 626
	/* Target chip */
	/* Send IPI */
	apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
627

628 629
	pr_debug("Waiting for send to finish...\n");
	send_status = safe_apic_wait_icr_idle();
630

631 632
	mb();
	atomic_set(&init_deasserted, 1);
633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649

	/*
	 * Should we send STARTUP IPIs ?
	 *
	 * Determine this based on the APIC version.
	 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
	 */
	if (APIC_INTEGRATED(apic_version[phys_apicid]))
		num_starts = 2;
	else
		num_starts = 0;

	/*
	 * Paravirt / VMI wants a startup IPI hook here to set up the
	 * target processor state.
	 */
	startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
650
			 stack_start);
651 652 653 654

	/*
	 * Run STARTUP IPI loop.
	 */
655
	pr_debug("#startup loops: %d\n", num_starts);
656 657

	for (j = 1; j <= num_starts; j++) {
658
		pr_debug("Sending STARTUP #%d\n", j);
659 660
		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
			apic_write(APIC_ESR, 0);
661
		apic_read(APIC_ESR);
662
		pr_debug("After apic_write\n");
663 664 665 666 667 668 669 670

		/*
		 * STARTUP IPI
		 */

		/* Target chip */
		/* Boot on the stack */
		/* Kick the second */
671 672
		apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
			       phys_apicid);
673

674 675 676 677
		/*
		 * Give the other CPU some time to accept the IPI.
		 */
		udelay(300);
678

679
		pr_debug("Startup point 1\n");
680

681 682
		pr_debug("Waiting for send to finish...\n");
		send_status = safe_apic_wait_icr_idle();
683

684 685 686 687
		/*
		 * Give the other CPU some time to accept the IPI.
		 */
		udelay(200);
688

689
		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
690 691 692 693 694
			apic_write(APIC_ESR, 0);
		accept_status = (apic_read(APIC_ESR) & 0xEF);
		if (send_status || accept_status)
			break;
	}
695
	pr_debug("After Startup\n");
696 697

	if (send_status)
698
		pr_err("APIC never delivered???\n");
699
	if (accept_status)
700
		pr_err("APIC delivery error (%lx)\n", accept_status);
701 702 703 704

	return (send_status | accept_status);
}

705 706 707 708 709 710 711 712
void smp_announce(void)
{
	int num_nodes = num_online_nodes();

	printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
	       num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
}

713
/* reduce the number of lines printed when booting a large cpu count system */
714
static void announce_cpu(int cpu, int apicid)
715 716
{
	static int current_node = -1;
717
	int node = early_cpu_to_node(cpu);
718
	static int width, node_width;
719 720 721

	if (!width)
		width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
722

723 724 725 726 727 728
	if (!node_width)
		node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */

	if (cpu == 1)
		printk(KERN_INFO "x86: Booting SMP configuration:\n");

729 730 731
	if (system_state == SYSTEM_BOOTING) {
		if (node != current_node) {
			if (current_node > (-1))
732
				pr_cont("\n");
733
			current_node = node;
734 735 736

			printk(KERN_INFO ".... node %*s#%d, CPUs:  ",
			       node_width - num_digits(node), " ", node);
737
		}
738 739 740 741 742 743 744

		/* Add padding for the BSP */
		if (cpu == 1)
			pr_cont("%*s", width + 1, " ");

		pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);

745 746 747 748 749
	} else
		pr_info("Booting Node %d Processor %d APIC 0x%x\n",
			node, cpu, apicid);
}

750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772
static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
{
	int cpu;

	cpu = smp_processor_id();
	if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
		return NMI_HANDLED;

	return NMI_DONE;
}

/*
 * Wake up AP by INIT, INIT, STARTUP sequence.
 *
 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
 * boot-strap code which is not a desired behavior for waking up BSP. To
 * void the boot-strap code, wake up CPU0 by NMI instead.
 *
 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
 * We'll change this code in the future to wake up hard offlined CPU0 if
 * real platform and request are available.
 */
773
static int
774 775 776 777 778 779
wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
	       int *cpu0_nmi_registered)
{
	int id;
	int boot_error;

780 781
	preempt_disable();

782 783 784
	/*
	 * Wake up AP by INIT, INIT, STARTUP sequence.
	 */
785 786 787 788
	if (cpu) {
		boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
		goto out;
	}
789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806

	/*
	 * Wake up BSP by nmi.
	 *
	 * Register a NMI handler to help wake up CPU0.
	 */
	boot_error = register_nmi_handler(NMI_LOCAL,
					  wakeup_cpu0_nmi, 0, "wake_cpu0");

	if (!boot_error) {
		enable_start_cpu0 = 1;
		*cpu0_nmi_registered = 1;
		if (apic->dest_logical == APIC_DEST_LOGICAL)
			id = cpu0_logical_apicid;
		else
			id = apicid;
		boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
	}
807 808 809

out:
	preempt_enable();
810 811 812 813

	return boot_error;
}

814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831
void common_cpu_up(unsigned int cpu, struct task_struct *idle)
{
	/* Just in case we booted with a single CPU. */
	alternatives_enable_smp();

	per_cpu(current_task, cpu) = idle;

#ifdef CONFIG_X86_32
	/* Stack for startup_32 can be just as for start_secondary onwards */
	irq_ctx_init(cpu);
	per_cpu(cpu_current_top_of_stack, cpu) =
		(unsigned long)task_stack_page(idle) + THREAD_SIZE;
#else
	clear_tsk_thread_flag(idle, TIF_FORK);
	initial_gs = per_cpu_offset(cpu);
#endif
}

832 833 834
/*
 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
835 836
 * Returns zero if CPU booted OK, else error code from
 * ->wakeup_secondary_cpu.
837
 */
838
static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
839
{
840
	volatile u32 *trampoline_status =
841
		(volatile u32 *) __va(real_mode_header->trampoline_status);
842
	/* start_ip had better be page-aligned! */
843
	unsigned long start_ip = real_mode_header->trampoline_start;
844

845
	unsigned long boot_error = 0;
846
	int cpu0_nmi_registered = 0;
847
	unsigned long timeout;
848

849 850
	idle->thread.sp = (unsigned long) (((struct pt_regs *)
			  (THREAD_SIZE +  task_stack_page(idle))) - 1);
851

852
	early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
853
	initial_code = (unsigned long)start_secondary;
854
	stack_start  = idle->thread.sp;
855

856 857
	/* So we see what's up */
	announce_cpu(cpu, apicid);
858 859 860 861 862 863 864 865

	/*
	 * This grunge runs the startup process for
	 * the targeted processor.
	 */

	atomic_set(&init_deasserted, 0);

J
Jack Steiner 已提交
866
	if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
867

868
		pr_debug("Setting warm reset code and vector.\n");
869

J
Jack Steiner 已提交
870 871 872
		smpboot_setup_warm_reset_vector(start_ip);
		/*
		 * Be paranoid about clearing APIC errors.
873 874 875 876 877
		*/
		if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
			apic_write(APIC_ESR, 0);
			apic_read(APIC_ESR);
		}
J
Jack Steiner 已提交
878
	}
879

880 881 882 883 884 885 886 887 888
	/*
	 * AP might wait on cpu_callout_mask in cpu_init() with
	 * cpu_initialized_mask set if previous attempt to online
	 * it timed-out. Clear cpu_initialized_mask so that after
	 * INIT/SIPI it could start with a clean state.
	 */
	cpumask_clear_cpu(cpu, cpu_initialized_mask);
	smp_mb();

889
	/*
890 891 892 893
	 * Wake up a CPU in difference cases:
	 * - Use the method in the APIC driver if it's defined
	 * Otherwise,
	 * - Use an INIT boot APIC message for APs or NMI for BSP.
894
	 */
895 896 897
	if (apic->wakeup_secondary_cpu)
		boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
	else
898 899
		boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
						     &cpu0_nmi_registered);
900 901 902

	if (!boot_error) {
		/*
903
		 * Wait 10s total for a response from AP
904
		 */
905 906 907 908 909 910 911 912 913 914 915 916 917 918 919
		boot_error = -1;
		timeout = jiffies + 10*HZ;
		while (time_before(jiffies, timeout)) {
			if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
				/*
				 * Tell AP to proceed with initialization
				 */
				cpumask_set_cpu(cpu, cpu_callout_mask);
				boot_error = 0;
				break;
			}
			udelay(100);
			schedule();
		}
	}
920

921
	if (!boot_error) {
922
		/*
923
		 * Wait till AP completes initial initialization
924
		 */
925
		while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
926 927 928 929 930 931
			/*
			 * Allow other tasks to run while we wait for the
			 * AP to come online. This also gives a chance
			 * for the MTRR work(triggered by the AP coming online)
			 * to be completed in the stop machine context.
			 */
932
			udelay(100);
933
			schedule();
934 935 936 937
		}
	}

	/* mark "stuck" area as not stuck */
938
	*trampoline_status = 0;
939

940 941 942 943 944 945
	if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
		/*
		 * Cleanup possible dangling ends...
		 */
		smpboot_restore_warm_reset_vector();
	}
946 947 948 949 950 951 952
	/*
	 * Clean up the nmi handler. Do this after the callin and callout sync
	 * to avoid impact of possible long unregister time.
	 */
	if (cpu0_nmi_registered)
		unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");

953 954 955
	return boot_error;
}

956
int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
957
{
958
	int apicid = apic->cpu_present_to_apicid(cpu);
959 960 961 962 963
	unsigned long flags;
	int err;

	WARN_ON(irqs_disabled());

964
	pr_debug("++++++++++++++++++++=_---CPU UP  %u\n", cpu);
965

966
	if (apicid == BAD_APICID ||
967
	    !physid_isset(apicid, phys_cpu_present_map) ||
968
	    !apic->apic_id_valid(apicid)) {
969
		pr_err("%s: bad cpu %d\n", __func__, cpu);
970 971 972 973 974 975
		return -EINVAL;
	}

	/*
	 * Already booted CPU?
	 */
976
	if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
977
		pr_debug("do_boot_cpu %d Already started\n", cpu);
978 979 980 981 982 983 984 985 986
		return -ENOSYS;
	}

	/*
	 * Save current MTRR state in case it was changed since early boot
	 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
	 */
	mtrr_save_state();

987 988 989 990
	/* x86 CPUs take themselves offline, so delayed offline is OK. */
	err = cpu_check_up_prepare(cpu);
	if (err && err != -EBUSY)
		return err;
991

992 993 994
	/* the FPU context is blank, nobody can own it */
	__cpu_disable_lazy_restore(cpu);

995 996
	common_cpu_up(cpu, tidle);

997
	err = do_boot_cpu(apicid, cpu, tidle);
998
	if (err) {
999
		pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1000
		return -EIO;
1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
	}

	/*
	 * Check TSC synchronization with the AP (keep irqs disabled
	 * while doing so):
	 */
	local_irq_save(flags);
	check_tsc_sync_source(cpu);
	local_irq_restore(flags);

1011
	while (!cpu_online(cpu)) {
1012 1013 1014 1015 1016 1017 1018
		cpu_relax();
		touch_nmi_watchdog();
	}

	return 0;
}

1019 1020 1021 1022 1023 1024 1025 1026
/**
 * arch_disable_smp_support() - disables SMP support for x86 at runtime
 */
void arch_disable_smp_support(void)
{
	disable_ioapic_support();
}

1027 1028 1029 1030 1031 1032 1033
/*
 * Fall back to non SMP mode after errors.
 *
 * RED-PEN audit/test this more. I bet there is more state messed up here.
 */
static __init void disable_smp(void)
{
1034 1035
	pr_info("SMP disabled\n");

1036 1037
	disable_ioapic_support();

1038 1039
	init_cpu_present(cpumask_of(0));
	init_cpu_possible(cpumask_of(0));
1040

1041
	if (smp_found_config)
1042
		physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1043
	else
1044
		physid_set_mask_of_physid(0, &phys_cpu_present_map);
1045 1046
	cpumask_set_cpu(0, cpu_sibling_mask(0));
	cpumask_set_cpu(0, cpu_core_mask(0));
1047 1048
}

1049 1050 1051 1052 1053 1054 1055
enum {
	SMP_OK,
	SMP_NO_CONFIG,
	SMP_NO_APIC,
	SMP_FORCE_UP,
};

1056 1057 1058 1059 1060
/*
 * Various sanity checks.
 */
static int __init smp_sanity_check(unsigned max_cpus)
{
J
Jack Steiner 已提交
1061
	preempt_disable();
1062

1063
#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1064 1065 1066 1067
	if (def_to_bigsmp && nr_cpu_ids > 8) {
		unsigned int cpu;
		unsigned nr;

1068 1069
		pr_warn("More than 8 CPUs detected - skipping them\n"
			"Use CONFIG_X86_BIGSMP\n");
1070 1071 1072 1073

		nr = 0;
		for_each_present_cpu(cpu) {
			if (nr >= 8)
1074
				set_cpu_present(cpu, false);
1075 1076 1077 1078 1079 1080
			nr++;
		}

		nr = 0;
		for_each_possible_cpu(cpu) {
			if (nr >= 8)
1081
				set_cpu_possible(cpu, false);
1082 1083 1084 1085 1086 1087 1088
			nr++;
		}

		nr_cpu_ids = 8;
	}
#endif

1089
	if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1090
		pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
M
Michael Tokarev 已提交
1091 1092
			hard_smp_processor_id());

1093 1094 1095 1096 1097 1098 1099 1100
		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
	}

	/*
	 * If we couldn't find an SMP configuration at boot time,
	 * get out of here now!
	 */
	if (!smp_found_config && !acpi_lapic) {
J
Jack Steiner 已提交
1101
		preempt_enable();
1102
		pr_notice("SMP motherboard not detected\n");
1103
		return SMP_NO_CONFIG;
1104 1105 1106 1107 1108 1109
	}

	/*
	 * Should not be necessary because the MP table should list the boot
	 * CPU too, but we do it for the sake of robustness anyway.
	 */
1110
	if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1111 1112
		pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
			  boot_cpu_physical_apicid);
1113 1114
		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
	}
J
Jack Steiner 已提交
1115
	preempt_enable();
1116 1117 1118 1119 1120 1121

	/*
	 * If we couldn't find a local APIC, then get out of here now!
	 */
	if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
	    !cpu_has_apic) {
1122 1123 1124
		if (!disable_apic) {
			pr_err("BIOS bug, local APIC #%d not detected!...\n",
				boot_cpu_physical_apicid);
1125
			pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1126
		}
1127
		return SMP_NO_APIC;
1128 1129 1130 1131 1132 1133
	}

	/*
	 * If SMP should be disabled, then really disable it!
	 */
	if (!max_cpus) {
1134
		pr_info("SMP mode deactivated\n");
1135
		return SMP_FORCE_UP;
1136 1137
	}

1138
	return SMP_OK;
1139 1140 1141 1142 1143 1144 1145
}

static void __init smp_cpu_index_default(void)
{
	int i;
	struct cpuinfo_x86 *c;

1146
	for_each_possible_cpu(i) {
1147 1148
		c = &cpu_data(i);
		/* mark all to hotplug */
1149
		c->cpu_index = nr_cpu_ids;
1150 1151 1152 1153 1154 1155 1156 1157 1158
	}
}

/*
 * Prepare for SMP bootup.  The MP table or ACPI has been read
 * earlier.  Just do some sanity checking here and enable APIC mode.
 */
void __init native_smp_prepare_cpus(unsigned int max_cpus)
{
1159 1160
	unsigned int i;

1161
	smp_cpu_index_default();
1162

1163 1164 1165
	/*
	 * Setup boot CPU information
	 */
1166
	smp_store_boot_cpu_info(); /* Final full version of the data */
1167 1168
	cpumask_copy(cpu_callin_mask, cpumask_of(0));
	mb();
1169

1170
	current_thread_info()->cpu = 0;  /* needed? */
1171
	for_each_possible_cpu(i) {
1172 1173
		zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
		zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1174
		zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1175
	}
1176 1177
	set_cpu_sibling_map(0);

1178 1179
	switch (smp_sanity_check(max_cpus)) {
	case SMP_NO_CONFIG:
1180
		disable_smp();
1181 1182 1183 1184 1185 1186 1187 1188
		if (APIC_init_uniprocessor())
			pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
		return;
	case SMP_NO_APIC:
		disable_smp();
		return;
	case SMP_FORCE_UP:
		disable_smp();
1189
		apic_bsp_setup(false);
1190
		return;
1191 1192
	case SMP_OK:
		break;
1193 1194
	}

1195 1196
	default_setup_apic_routing();

1197
	if (read_apic_id() != boot_cpu_physical_apicid) {
1198
		panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1199
		     read_apic_id(), boot_cpu_physical_apicid);
1200 1201 1202
		/* Or can we switch back to PIC here? */
	}

1203
	cpu0_logical_apicid = apic_bsp_setup(false);
1204

1205
	pr_info("CPU%d: ", 0);
1206
	print_cpu_info(&cpu_data(0));
1207 1208 1209

	if (is_uv_system())
		uv_system_init();
1210 1211

	set_mtrr_aps_delayed_init();
1212 1213

	smp_quirk_init_udelay();
1214
}
1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225

void arch_enable_nonboot_cpus_begin(void)
{
	set_mtrr_aps_delayed_init();
}

void arch_enable_nonboot_cpus_end(void)
{
	mtrr_aps_init();
}

1226 1227 1228 1229 1230 1231
/*
 * Early setup to make printk work.
 */
void __init native_smp_prepare_boot_cpu(void)
{
	int me = smp_processor_id();
1232
	switch_to_new_gdt(me);
1233 1234
	/* already set me in cpu_online_mask in boot_cpu_init() */
	cpumask_set_cpu(me, cpu_callout_mask);
1235
	cpu_set_state_online(me);
1236 1237
}

1238 1239
void __init native_smp_cpus_done(unsigned int max_cpus)
{
1240
	pr_debug("Boot done\n");
1241

D
Don Zickus 已提交
1242
	nmi_selftest();
1243 1244
	impress_friends();
	setup_ioapic_dest();
1245
	mtrr_aps_init();
1246 1247
}

1248 1249 1250 1251 1252 1253 1254 1255 1256
static int __initdata setup_possible_cpus = -1;
static int __init _setup_possible_cpus(char *str)
{
	get_option(&str, &setup_possible_cpus);
	return 0;
}
early_param("possible_cpus", _setup_possible_cpus);


1257
/*
1258
 * cpu_possible_mask should be static, it cannot change as cpu's
1259 1260 1261
 * are onlined, or offlined. The reason is per-cpu data-structures
 * are allocated by some modules at init time, and dont expect to
 * do this dynamically on cpu arrival/departure.
1262
 * cpu_present_mask on the other hand can change dynamically.
1263 1264 1265 1266 1267 1268
 * In case when cpu_hotplug is not compiled, then we resort to current
 * behaviour, which is cpu_possible == cpu_present.
 * - Ashok Raj
 *
 * Three ways to find out the number of additional hotplug CPUs:
 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1269
 * - The user can overwrite it with possible_cpus=NUM
1270 1271 1272 1273 1274 1275
 * - Otherwise don't reserve additional CPUs.
 * We do this because additional CPUs waste a lot of memory.
 * -AK
 */
__init void prefill_possible_map(void)
{
T
Thomas Gleixner 已提交
1276
	int i, possible;
1277

1278 1279 1280 1281
	/* no processor from mptable or madt */
	if (!num_processors)
		num_processors = 1;

1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292
	i = setup_max_cpus ?: 1;
	if (setup_possible_cpus == -1) {
		possible = num_processors;
#ifdef CONFIG_HOTPLUG_CPU
		if (setup_max_cpus)
			possible += disabled_cpus;
#else
		if (possible > i)
			possible = i;
#endif
	} else
1293 1294
		possible = setup_possible_cpus;

1295 1296
	total_cpus = max_t(int, possible, num_processors + disabled_cpus);

1297 1298
	/* nr_cpu_ids could be reduced via nr_cpus= */
	if (possible > nr_cpu_ids) {
1299
		pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1300 1301
			possible, nr_cpu_ids);
		possible = nr_cpu_ids;
1302
	}
1303

1304 1305 1306 1307
#ifdef CONFIG_HOTPLUG_CPU
	if (!setup_max_cpus)
#endif
	if (possible > i) {
1308
		pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1309 1310 1311 1312
			possible, setup_max_cpus);
		possible = i;
	}

1313
	pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1314 1315 1316
		possible, max_t(int, possible - num_processors, 0));

	for (i = 0; i < possible; i++)
1317
		set_cpu_possible(i, true);
1318 1319
	for (; i < NR_CPUS; i++)
		set_cpu_possible(i, false);
1320 1321

	nr_cpu_ids = possible;
1322
}
1323

1324 1325 1326 1327 1328 1329 1330
#ifdef CONFIG_HOTPLUG_CPU

static void remove_siblinginfo(int cpu)
{
	int sibling;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

1331 1332
	for_each_cpu(sibling, cpu_core_mask(cpu)) {
		cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1333 1334 1335
		/*/
		 * last thread sibling in this cpu core going down
		 */
1336
		if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1337 1338 1339
			cpu_data(sibling).booted_cores--;
	}

1340 1341
	for_each_cpu(sibling, cpu_sibling_mask(cpu))
		cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1342 1343 1344
	for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
		cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
	cpumask_clear(cpu_llc_shared_mask(cpu));
1345 1346
	cpumask_clear(cpu_sibling_mask(cpu));
	cpumask_clear(cpu_core_mask(cpu));
1347 1348
	c->phys_proc_id = 0;
	c->cpu_core_id = 0;
1349
	cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1350 1351
}

1352 1353
static void __ref remove_cpu_from_maps(int cpu)
{
1354 1355 1356
	set_cpu_online(cpu, false);
	cpumask_clear_cpu(cpu, cpu_callout_mask);
	cpumask_clear_cpu(cpu, cpu_callin_mask);
1357
	/* was set by cpu_init() */
1358
	cpumask_clear_cpu(cpu, cpu_initialized_mask);
1359
	numa_remove_cpu(cpu);
1360 1361
}

1362
void cpu_disable_common(void)
1363 1364 1365 1366 1367 1368
{
	int cpu = smp_processor_id();

	remove_siblinginfo(cpu);

	/* It's now safe to remove this processor from the online map */
1369
	lock_vector_lock();
1370
	remove_cpu_from_maps(cpu);
1371
	unlock_vector_lock();
1372
	fixup_irqs();
1373 1374 1375 1376
}

int native_cpu_disable(void)
{
1377 1378 1379 1380 1381 1382
	int ret;

	ret = check_irq_vectors_for_cpu_disable();
	if (ret)
		return ret;

1383 1384
	clear_local_APIC();
	cpu_disable_common();
1385

1386 1387 1388
	return 0;
}

1389
int common_cpu_die(unsigned int cpu)
1390
{
1391
	int ret = 0;
1392

1393
	/* We don't do anything here: idle task is faking death itself. */
1394

1395
	/* They ack this in play_dead() by setting CPU_DEAD */
1396
	if (cpu_wait_death(cpu, 5)) {
1397 1398 1399 1400
		if (system_state == SYSTEM_RUNNING)
			pr_info("CPU %u is now offline\n", cpu);
	} else {
		pr_err("CPU %u didn't die...\n", cpu);
1401
		ret = -1;
1402
	}
1403 1404 1405 1406 1407 1408 1409

	return ret;
}

void native_cpu_die(unsigned int cpu)
{
	common_cpu_die(cpu);
1410
}
1411 1412 1413 1414 1415

void play_dead_common(void)
{
	idle_task_exit();
	reset_lazy_tlbstate();
1416
	amd_e400_remove_cpu(raw_smp_processor_id());
1417 1418

	/* Ack it */
1419
	(void)cpu_report_death();
1420 1421 1422 1423 1424 1425 1426

	/*
	 * With physical CPU hotplug, we should halt the cpu
	 */
	local_irq_disable();
}

1427 1428 1429 1430 1431 1432 1433 1434
static bool wakeup_cpu0(void)
{
	if (smp_processor_id() == 0 && enable_start_cpu0)
		return true;

	return false;
}

1435 1436 1437 1438 1439 1440 1441 1442 1443
/*
 * We need to flush the caches before going to sleep, lest we have
 * dirty data in our caches when we come back up.
 */
static inline void mwait_play_dead(void)
{
	unsigned int eax, ebx, ecx, edx;
	unsigned int highest_cstate = 0;
	unsigned int highest_subcstate = 0;
1444
	void *mwait_ptr;
1445
	int i;
1446

1447
	if (!this_cpu_has(X86_FEATURE_MWAIT))
1448
		return;
1449
	if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1450
		return;
1451
	if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475
		return;

	eax = CPUID_MWAIT_LEAF;
	ecx = 0;
	native_cpuid(&eax, &ebx, &ecx, &edx);

	/*
	 * eax will be 0 if EDX enumeration is not valid.
	 * Initialized below to cstate, sub_cstate value when EDX is valid.
	 */
	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
		eax = 0;
	} else {
		edx >>= MWAIT_SUBSTATE_SIZE;
		for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
			if (edx & MWAIT_SUBSTATE_MASK) {
				highest_cstate = i;
				highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
			}
		}
		eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
			(highest_subcstate - 1);
	}

1476 1477 1478 1479 1480 1481 1482
	/*
	 * This should be a memory location in a cache line which is
	 * unlikely to be touched by other processors.  The actual
	 * content is immaterial as it is not actually modified in any way.
	 */
	mwait_ptr = &current_thread_info()->flags;

1483 1484
	wbinvd();

1485
	while (1) {
1486 1487 1488 1489 1490 1491 1492
		/*
		 * The CLFLUSH is a workaround for erratum AAI65 for
		 * the Xeon 7400 series.  It's not clear it is actually
		 * needed, but it should be harmless in either case.
		 * The WBINVD is insufficient due to the spurious-wakeup
		 * case where we return around the loop.
		 */
1493
		mb();
1494
		clflush(mwait_ptr);
1495
		mb();
1496
		__monitor(mwait_ptr, 0, 0);
1497 1498
		mb();
		__mwait(eax, 0);
1499 1500 1501 1502 1503
		/*
		 * If NMI wants to wake up CPU0, start CPU0.
		 */
		if (wakeup_cpu0())
			start_cpu0();
1504 1505 1506 1507 1508
	}
}

static inline void hlt_play_dead(void)
{
1509
	if (__this_cpu_read(cpu_info.x86) >= 4)
1510 1511
		wbinvd();

1512 1513
	while (1) {
		native_halt();
1514 1515 1516 1517 1518
		/*
		 * If NMI wants to wake up CPU0, start CPU0.
		 */
		if (wakeup_cpu0())
			start_cpu0();
1519 1520 1521
	}
}

1522 1523 1524
void native_play_dead(void)
{
	play_dead_common();
1525
	tboot_shutdown(TB_SHUTDOWN_WFS);
1526 1527

	mwait_play_dead();	/* Only returns on failure */
1528 1529
	if (cpuidle_play_dead())
		hlt_play_dead();
1530 1531
}

1532
#else /* ... !CONFIG_HOTPLUG_CPU */
1533
int native_cpu_disable(void)
1534 1535 1536 1537
{
	return -ENOSYS;
}

1538
void native_cpu_die(unsigned int cpu)
1539 1540 1541 1542
{
	/* We said "no" in __cpu_disable */
	BUG();
}
1543 1544 1545 1546 1547 1548

void native_play_dead(void)
{
	BUG();
}

1549
#endif