cx23885-core.c 50.8 KB
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/*
 *  Driver for the Conexant CX23885 PCIe bridge
 *
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 *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
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 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kmod.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/div64.h>

#include "cx23885.h"
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#include "cimax2.h"
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MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
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MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
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MODULE_LICENSE("GPL");

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static unsigned int debug;
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module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages");
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static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
module_param_array(card,  int, NULL, 0444);
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MODULE_PARM_DESC(card, "card type");
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#define dprintk(level, fmt, arg...)\
	do { if (debug >= level)\
		printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
	} while (0)
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static unsigned int cx23885_devcount;

static DEFINE_MUTEX(devlist);
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LIST_HEAD(cx23885_devlist);
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#define NO_SYNC_LINE (-1U)

/* FIXME, these allocations will change when
 * analog arrives. The be reviewed.
 * CX23887 Assumptions
 * 1 line = 16 bytes of CDT
 * cmds size = 80
 * cdt size = 16 * linesize
 * iqsize = 64
 * maxlines = 6
 *
 * Address Space:
 * 0x00000000 0x00008fff FIFO clusters
 * 0x00010000 0x000104af Channel Management Data Structures
 * 0x000104b0 0x000104ff Free
 * 0x00010500 0x000108bf 15 channels * iqsize
 * 0x000108c0 0x000108ff Free
 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 *                       15 channels * (iqsize + (maxlines * linesize))
 * 0x00010ea0 0x00010xxx Free
 */

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static struct sram_channel cx23885_sram_channels[] = {
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	[SRAM_CH01] = {
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		.name		= "VID A",
		.cmds_start	= 0x10000,
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		.ctrl_start	= 0x10380,
		.cdt		= 0x104c0,
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		.fifo_start	= 0x40,
		.fifo_size	= 0x2800,
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		.ptr1_reg	= DMA1_PTR1,
		.ptr2_reg	= DMA1_PTR2,
		.cnt1_reg	= DMA1_CNT1,
		.cnt2_reg	= DMA1_CNT2,
	},
	[SRAM_CH02] = {
		.name		= "ch2",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA2_PTR1,
		.ptr2_reg	= DMA2_PTR2,
		.cnt1_reg	= DMA2_CNT1,
		.cnt2_reg	= DMA2_CNT2,
	},
	[SRAM_CH03] = {
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		.name		= "TS1 B",
		.cmds_start	= 0x100A0,
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		.ctrl_start	= 0x10400,
		.cdt		= 0x10580,
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		.fifo_start	= 0x5000,
		.fifo_size	= 0x1000,
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		.ptr1_reg	= DMA3_PTR1,
		.ptr2_reg	= DMA3_PTR2,
		.cnt1_reg	= DMA3_CNT1,
		.cnt2_reg	= DMA3_CNT2,
	},
	[SRAM_CH04] = {
		.name		= "ch4",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA4_PTR1,
		.ptr2_reg	= DMA4_PTR2,
		.cnt1_reg	= DMA4_CNT1,
		.cnt2_reg	= DMA4_CNT2,
	},
	[SRAM_CH05] = {
		.name		= "ch5",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA5_PTR1,
		.ptr2_reg	= DMA5_PTR2,
		.cnt1_reg	= DMA5_CNT1,
		.cnt2_reg	= DMA5_CNT2,
	},
	[SRAM_CH06] = {
		.name		= "TS2 C",
		.cmds_start	= 0x10140,
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		.ctrl_start	= 0x10440,
		.cdt		= 0x105e0,
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		.fifo_start	= 0x6000,
		.fifo_size	= 0x1000,
		.ptr1_reg	= DMA5_PTR1,
		.ptr2_reg	= DMA5_PTR2,
		.cnt1_reg	= DMA5_CNT1,
		.cnt2_reg	= DMA5_CNT2,
	},
	[SRAM_CH07] = {
		.name		= "ch7",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA6_PTR1,
		.ptr2_reg	= DMA6_PTR2,
		.cnt1_reg	= DMA6_CNT1,
		.cnt2_reg	= DMA6_CNT2,
	},
	[SRAM_CH08] = {
		.name		= "ch8",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA7_PTR1,
		.ptr2_reg	= DMA7_PTR2,
		.cnt1_reg	= DMA7_CNT1,
		.cnt2_reg	= DMA7_CNT2,
	},
	[SRAM_CH09] = {
		.name		= "ch9",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA8_PTR1,
		.ptr2_reg	= DMA8_PTR2,
		.cnt1_reg	= DMA8_CNT1,
		.cnt2_reg	= DMA8_CNT2,
	},
};

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static struct sram_channel cx23887_sram_channels[] = {
	[SRAM_CH01] = {
		.name		= "VID A",
		.cmds_start	= 0x10000,
		.ctrl_start	= 0x105b0,
		.cdt		= 0x107b0,
		.fifo_start	= 0x40,
		.fifo_size	= 0x2800,
		.ptr1_reg	= DMA1_PTR1,
		.ptr2_reg	= DMA1_PTR2,
		.cnt1_reg	= DMA1_CNT1,
		.cnt2_reg	= DMA1_CNT2,
	},
	[SRAM_CH02] = {
		.name		= "ch2",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA2_PTR1,
		.ptr2_reg	= DMA2_PTR2,
		.cnt1_reg	= DMA2_CNT1,
		.cnt2_reg	= DMA2_CNT2,
	},
	[SRAM_CH03] = {
		.name		= "TS1 B",
		.cmds_start	= 0x100A0,
		.ctrl_start	= 0x10630,
		.cdt		= 0x10870,
		.fifo_start	= 0x5000,
		.fifo_size	= 0x1000,
		.ptr1_reg	= DMA3_PTR1,
		.ptr2_reg	= DMA3_PTR2,
		.cnt1_reg	= DMA3_CNT1,
		.cnt2_reg	= DMA3_CNT2,
	},
	[SRAM_CH04] = {
		.name		= "ch4",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA4_PTR1,
		.ptr2_reg	= DMA4_PTR2,
		.cnt1_reg	= DMA4_CNT1,
		.cnt2_reg	= DMA4_CNT2,
	},
	[SRAM_CH05] = {
		.name		= "ch5",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA5_PTR1,
		.ptr2_reg	= DMA5_PTR2,
		.cnt1_reg	= DMA5_CNT1,
		.cnt2_reg	= DMA5_CNT2,
	},
	[SRAM_CH06] = {
		.name		= "TS2 C",
		.cmds_start	= 0x10140,
		.ctrl_start	= 0x10670,
		.cdt		= 0x108d0,
		.fifo_start	= 0x6000,
		.fifo_size	= 0x1000,
		.ptr1_reg	= DMA5_PTR1,
		.ptr2_reg	= DMA5_PTR2,
		.cnt1_reg	= DMA5_CNT1,
		.cnt2_reg	= DMA5_CNT2,
	},
	[SRAM_CH07] = {
		.name		= "ch7",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA6_PTR1,
		.ptr2_reg	= DMA6_PTR2,
		.cnt1_reg	= DMA6_CNT1,
		.cnt2_reg	= DMA6_CNT2,
	},
	[SRAM_CH08] = {
		.name		= "ch8",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA7_PTR1,
		.ptr2_reg	= DMA7_PTR2,
		.cnt1_reg	= DMA7_CNT1,
		.cnt2_reg	= DMA7_CNT2,
	},
	[SRAM_CH09] = {
		.name		= "ch9",
		.cmds_start	= 0x0,
		.ctrl_start	= 0x0,
		.cdt		= 0x0,
		.fifo_start	= 0x0,
		.fifo_size	= 0x0,
		.ptr1_reg	= DMA8_PTR1,
		.ptr2_reg	= DMA8_PTR2,
		.cnt1_reg	= DMA8_CNT1,
		.cnt2_reg	= DMA8_CNT2,
	},
};

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static int cx23885_risc_decode(u32 risc)
{
	static char *instr[16] = {
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		[RISC_SYNC    >> 28] = "sync",
		[RISC_WRITE   >> 28] = "write",
		[RISC_WRITEC  >> 28] = "writec",
		[RISC_READ    >> 28] = "read",
		[RISC_READC   >> 28] = "readc",
		[RISC_JUMP    >> 28] = "jump",
		[RISC_SKIP    >> 28] = "skip",
		[RISC_WRITERM >> 28] = "writerm",
		[RISC_WRITECM >> 28] = "writecm",
		[RISC_WRITECR >> 28] = "writecr",
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	};
	static int incr[16] = {
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		[RISC_WRITE   >> 28] = 3,
		[RISC_JUMP    >> 28] = 3,
		[RISC_SKIP    >> 28] = 1,
		[RISC_SYNC    >> 28] = 1,
		[RISC_WRITERM >> 28] = 3,
		[RISC_WRITECM >> 28] = 3,
		[RISC_WRITECR >> 28] = 4,
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	};
	static char *bits[] = {
		"12",   "13",   "14",   "resync",
		"cnt0", "cnt1", "18",   "19",
		"20",   "21",   "22",   "23",
		"irq1", "irq2", "eol",  "sol",
	};
	int i;

	printk("0x%08x [ %s", risc,
	       instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
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	for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
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		if (risc & (1 << (i + 12)))
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			printk(" %s", bits[i]);
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	printk(" count=%d ]\n", risc & 0xfff);
	return incr[risc >> 28] ? incr[risc >> 28] : 1;
}

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void cx23885_wakeup(struct cx23885_tsport *port,
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			   struct cx23885_dmaqueue *q, u32 count)
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{
	struct cx23885_dev *dev = port->dev;
	struct cx23885_buffer *buf;
	int bc;

	for (bc = 0;; bc++) {
		if (list_empty(&q->active))
			break;
		buf = list_entry(q->active.next,
				 struct cx23885_buffer, vb.queue);
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		/* count comes from the hw and is is 16bit wide --
		 * this trick handles wrap-arounds correctly for
		 * up to 32767 buffers in flight... */
		if ((s16) (count - buf->count) < 0)
			break;
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		do_gettimeofday(&buf->vb.ts);
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		dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
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			count, buf->count);
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		buf->vb.state = VIDEOBUF_DONE;
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		list_del(&buf->vb.queue);
		wake_up(&buf->vb.done);
	}
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	if (list_empty(&q->active))
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		del_timer(&q->timeout);
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	else
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		mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
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	if (bc != 1)
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		printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
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		       __func__, bc);
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}

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int cx23885_sram_channel_setup(struct cx23885_dev *dev,
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				      struct sram_channel *ch,
				      unsigned int bpl, u32 risc)
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{
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	unsigned int i, lines;
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	u32 cdt;

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	if (ch->cmds_start == 0) {
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		dprintk(1, "%s() Erasing channel [%s]\n", __func__,
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			ch->name);
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		cx_write(ch->ptr1_reg, 0);
		cx_write(ch->ptr2_reg, 0);
		cx_write(ch->cnt2_reg, 0);
		cx_write(ch->cnt1_reg, 0);
		return 0;
	} else {
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		dprintk(1, "%s() Configuring channel [%s]\n", __func__,
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			ch->name);
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	}

	bpl   = (bpl + 7) & ~7; /* alignment */
	cdt   = ch->cdt;
	lines = ch->fifo_size / bpl;
	if (lines > 6)
		lines = 6;
	BUG_ON(lines < 2);

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	cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
	cx_write(8 + 4, 8);
	cx_write(8 + 8, 0);
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	/* write CDT */
	for (i = 0; i < lines; i++) {
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		dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
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			ch->fifo_start + bpl*i);
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		cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
		cx_write(cdt + 16*i +  4, 0);
		cx_write(cdt + 16*i +  8, 0);
		cx_write(cdt + 16*i + 12, 0);
	}

	/* write CMDS */
	if (ch->jumponly)
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		cx_write(ch->cmds_start + 0, 8);
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	else
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		cx_write(ch->cmds_start + 0, risc);
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	cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
	cx_write(ch->cmds_start +  8, cdt);
	cx_write(ch->cmds_start + 12, (lines*16) >> 3);
	cx_write(ch->cmds_start + 16, ch->ctrl_start);
	if (ch->jumponly)
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		cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
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	else
		cx_write(ch->cmds_start + 20, 64 >> 2);
	for (i = 24; i < 80; i += 4)
		cx_write(ch->cmds_start + i, 0);

	/* fill registers */
	cx_write(ch->ptr1_reg, ch->fifo_start);
	cx_write(ch->ptr2_reg, cdt);
	cx_write(ch->cnt2_reg, (lines*16) >> 3);
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	cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
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	dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
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		dev->bridge,
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		ch->name,
		bpl,
		lines);

	return 0;
}

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void cx23885_sram_channel_dump(struct cx23885_dev *dev,
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				      struct sram_channel *ch)
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{
	static char *name[] = {
		"init risc lo",
		"init risc hi",
		"cdt base",
		"cdt size",
		"iq base",
		"iq size",
		"risc pc lo",
		"risc pc hi",
		"iq wr ptr",
		"iq rd ptr",
		"cdt current",
		"pci target lo",
		"pci target hi",
		"line / byte",
	};
	u32 risc;
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	unsigned int i, j, n;
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	printk(KERN_WARNING "%s: %s - dma channel status dump\n",
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	       dev->name, ch->name);
	for (i = 0; i < ARRAY_SIZE(name); i++)
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		printk(KERN_WARNING "%s:   cmds: %-15s: 0x%08x\n",
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		       dev->name, name[i],
		       cx_read(ch->cmds_start + 4*i));

	for (i = 0; i < 4; i++) {
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		risc = cx_read(ch->cmds_start + 4 * (i + 14));
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		printk(KERN_WARNING "%s:   risc%d: ", dev->name, i);
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		cx23885_risc_decode(risc);
	}
	for (i = 0; i < (64 >> 2); i += n) {
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		risc = cx_read(ch->ctrl_start + 4 * i);
		/* No consideration for bits 63-32 */

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		printk(KERN_WARNING "%s:   (0x%08x) iq %x: ", dev->name,
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		       ch->ctrl_start + 4 * i, i);
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		n = cx23885_risc_decode(risc);
		for (j = 1; j < n; j++) {
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			risc = cx_read(ch->ctrl_start + 4 * (i + j));
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			printk(KERN_WARNING "%s:   iq %x: 0x%08x [ arg #%d ]\n",
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			       dev->name, i+j, risc, j);
		}
	}

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	printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
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	       dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
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	printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
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	       dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
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	printk(KERN_WARNING "%s:   ptr1_reg: 0x%08x\n",
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	       dev->name, cx_read(ch->ptr1_reg));
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	printk(KERN_WARNING "%s:   ptr2_reg: 0x%08x\n",
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	       dev->name, cx_read(ch->ptr2_reg));
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	printk(KERN_WARNING "%s:   cnt1_reg: 0x%08x\n",
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	       dev->name, cx_read(ch->cnt1_reg));
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	printk(KERN_WARNING "%s:   cnt2_reg: 0x%08x\n",
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	       dev->name, cx_read(ch->cnt2_reg));
}

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static void cx23885_risc_disasm(struct cx23885_tsport *port,
				struct btcx_riscmem *risc)
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{
	struct cx23885_dev *dev = port->dev;
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	unsigned int i, j, n;
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	printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
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	       dev->name, risc->cpu, (unsigned long)risc->dma);
	for (i = 0; i < (risc->size >> 2); i += n) {
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		printk(KERN_INFO "%s:   %04d: ", dev->name, i);
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		n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
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		for (j = 1; j < n; j++)
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			printk(KERN_INFO "%s:   %04d: 0x%08x [ arg #%d ]\n",
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			       dev->name, i + j, risc->cpu[i + j], j);
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		if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
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			break;
	}
}

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static void cx23885_shutdown(struct cx23885_dev *dev)
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{
	/* disable RISC controller */
	cx_write(DEV_CNTRL2, 0);

	/* Disable all IR activity */
	cx_write(IR_CNTRL_REG, 0);

	/* Disable Video A/B activity */
	cx_write(VID_A_DMA_CTL, 0);
	cx_write(VID_B_DMA_CTL, 0);
	cx_write(VID_C_DMA_CTL, 0);

	/* Disable Audio activity */
	cx_write(AUD_INT_DMA_CTL, 0);
	cx_write(AUD_EXT_DMA_CTL, 0);

	/* Disable Serial port */
	cx_write(UART_CTL, 0);

	/* Disable Interrupts */
	cx_write(PCI_INT_MSK, 0);
	cx_write(VID_A_INT_MSK, 0);
	cx_write(VID_B_INT_MSK, 0);
	cx_write(VID_C_INT_MSK, 0);
	cx_write(AUDIO_INT_INT_MSK, 0);
	cx_write(AUDIO_EXT_INT_MSK, 0);

}

A
Adrian Bunk 已提交
560
static void cx23885_reset(struct cx23885_dev *dev)
561
{
562
	dprintk(1, "%s()\n", __func__);
563 564 565 566 567 568 569 570 571 572

	cx23885_shutdown(dev);

	cx_write(PCI_INT_STAT, 0xffffffff);
	cx_write(VID_A_INT_STAT, 0xffffffff);
	cx_write(VID_B_INT_STAT, 0xffffffff);
	cx_write(VID_C_INT_STAT, 0xffffffff);
	cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
	cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
	cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
573
	cx_write(PAD_CTRL, 0x00500300);
574 575 576

	mdelay(100);

577 578 579 580 581 582 583 584 585 586 587 588
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
		720*4, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
		188*4, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
		188*4, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
	cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
589

590
	cx23885_gpio_setup(dev);
591 592 593 594 595
}


static int cx23885_pci_quirks(struct cx23885_dev *dev)
{
596
	dprintk(1, "%s()\n", __func__);
597

598 599 600 601
	/* The cx23885 bridge has a weird bug which causes NMI to be asserted
	 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
	 * occur on the cx23887 bridge.
	 */
602
	if (dev->bridge == CX23885_BRIDGE_885)
603
		cx_clear(RDR_TLCTL0, 1 << 4);
604

605 606 607 608 609
	return 0;
}

static int get_resources(struct cx23885_dev *dev)
{
610 611
	if (request_mem_region(pci_resource_start(dev->pci, 0),
			       pci_resource_len(dev->pci, 0),
612
			       dev->name))
613 614 615
		return 0;

	printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
616
		dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
617 618 619 620 621

	return -EBUSY;
}

static void cx23885_timeout(unsigned long data);
622
int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
A
Adrian Bunk 已提交
623
				u32 reg, u32 mask, u32 value);
624

625 626
static int cx23885_init_tsport(struct cx23885_dev *dev,
	struct cx23885_tsport *port, int portno)
627
{
628
	dprintk(1, "%s(portno=%d)\n", __func__, portno);
629 630 631 632

	/* Transport bus init dma queue  - Common settings */
	port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
	port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
633 634
	port->vld_misc_val       = 0x0;
	port->hw_sop_ctrl_val    = (0x47 << 16 | 188 << 4);
635 636 637 638 639 640 641 642 643 644 645

	spin_lock_init(&port->slock);
	port->dev = dev;
	port->nr = portno;

	INIT_LIST_HEAD(&port->mpegq.active);
	INIT_LIST_HEAD(&port->mpegq.queued);
	port->mpegq.timeout.function = cx23885_timeout;
	port->mpegq.timeout.data = (unsigned long)port;
	init_timer(&port->mpegq.timeout);

646
	mutex_init(&port->frontends.lock);
647
	INIT_LIST_HEAD(&port->frontends.felist);
648 649
	port->frontends.active_fe_id = 0;

650 651 652 653
	/* This should be hardcoded allow a single frontend
	 * attachment to this tsport, keeping the -dvb.c
	 * code clean and safe.
	 */
654
	if (!port->num_frontends)
655 656
		port->num_frontends = 1;

657
	switch (portno) {
658 659 660 661 662 663 664 665 666 667 668 669 670 671
	case 1:
		port->reg_gpcnt          = VID_B_GPCNT;
		port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
		port->reg_dma_ctl        = VID_B_DMA_CTL;
		port->reg_lngth          = VID_B_LNGTH;
		port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
		port->reg_gen_ctrl       = VID_B_GEN_CTL;
		port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
		port->reg_sop_status     = VID_B_SOP_STATUS;
		port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
		port->reg_vld_misc       = VID_B_VLD_MISC;
		port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
		port->reg_src_sel        = VID_B_SRC_SEL;
		port->reg_ts_int_msk     = VID_B_INT_MSK;
672
		port->reg_ts_int_stat    = VID_B_INT_STAT;
673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692
		port->sram_chno          = SRAM_CH03; /* VID_B */
		port->pci_irqmask        = 0x02; /* VID_B bit1 */
		break;
	case 2:
		port->reg_gpcnt          = VID_C_GPCNT;
		port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
		port->reg_dma_ctl        = VID_C_DMA_CTL;
		port->reg_lngth          = VID_C_LNGTH;
		port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
		port->reg_gen_ctrl       = VID_C_GEN_CTL;
		port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
		port->reg_sop_status     = VID_C_SOP_STATUS;
		port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
		port->reg_vld_misc       = VID_C_VLD_MISC;
		port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
		port->reg_src_sel        = 0;
		port->reg_ts_int_msk     = VID_C_INT_MSK;
		port->reg_ts_int_stat    = VID_C_INT_STAT;
		port->sram_chno          = SRAM_CH06; /* VID_C */
		port->pci_irqmask        = 0x04; /* VID_C bit2 */
693
		break;
694 695
	default:
		BUG();
696 697
	}

698 699 700
	cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
		     port->reg_dma_ctl, port->dma_ctl_val, 0x00);

701 702 703
	return 0;
}

704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731
static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
{
	switch (cx_read(RDR_CFG2) & 0xff) {
	case 0x00:
		/* cx23885 */
		dev->hwrevision = 0xa0;
		break;
	case 0x01:
		/* CX23885-12Z */
		dev->hwrevision = 0xa1;
		break;
	case 0x02:
		/* CX23885-13Z */
		dev->hwrevision = 0xb0;
		break;
	case 0x03:
		/* CX23888-22Z */
		dev->hwrevision = 0xc0;
		break;
	case 0x0e:
		/* CX23887-15Z */
		dev->hwrevision = 0xc0;
	case 0x0f:
		/* CX23887-14Z */
		dev->hwrevision = 0xb1;
		break;
	default:
		printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
732
			__func__, dev->hwrevision);
733 734 735
	}
	if (dev->hwrevision)
		printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
736
			__func__, dev->hwrevision);
737 738
	else
		printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
739
			__func__, dev->hwrevision);
740 741
}

742 743 744 745 746 747 748 749 750
static int cx23885_dev_setup(struct cx23885_dev *dev)
{
	int i;

	mutex_init(&dev->lock);

	atomic_inc(&dev->refcount);

	dev->nr = cx23885_devcount++;
751 752 753 754 755 756 757
	sprintf(dev->name, "cx23885[%d]", dev->nr);

	mutex_lock(&devlist);
	list_add_tail(&dev->devlist, &cx23885_devlist);
	mutex_unlock(&devlist);

	/* Configure the internal memory */
758
	if (dev->pci->device == 0x8880) {
759
		dev->bridge = CX23885_BRIDGE_887;
760 761
		/* Apply a sensible clock frequency for the PCIe bridge */
		dev->clk_freq = 25000000;
762
		dev->sram_channels = cx23887_sram_channels;
763
	} else
764
	if (dev->pci->device == 0x8852) {
765
		dev->bridge = CX23885_BRIDGE_885;
766 767
		/* Apply a sensible clock frequency for the PCIe bridge */
		dev->clk_freq = 28000000;
768
		dev->sram_channels = cx23885_sram_channels;
769 770 771 772
	} else
		BUG();

	dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
773
		__func__, dev->bridge);
774 775 776 777 778 779 780 781 782 783 784 785 786 787

	/* board config */
	dev->board = UNSET;
	if (card[dev->nr] < cx23885_bcount)
		dev->board = card[dev->nr];
	for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
		if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
		    dev->pci->subsystem_device == cx23885_subids[i].subdevice)
			dev->board = cx23885_subids[i].card;
	if (UNSET == dev->board) {
		dev->board = CX23885_BOARD_UNKNOWN;
		cx23885_card_list(dev);
	}

788 789 790 791
	/* If the user specific a clk freq override, apply it */
	if (cx23885_boards[dev->board].clk_freq > 0)
		dev->clk_freq = cx23885_boards[dev->board].clk_freq;

792 793 794
	dev->pci_bus  = dev->pci->bus->number;
	dev->pci_slot = PCI_SLOT(dev->pci->devfn);
	dev->pci_irqmask = 0x001f00;
795 796
	if (cx23885_boards[dev->board].cimax > 0)
		dev->pci_irqmask |= 0x01800000; /* for CiMaxes */
797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822

	/* External Master 1 Bus */
	dev->i2c_bus[0].nr = 0;
	dev->i2c_bus[0].dev = dev;
	dev->i2c_bus[0].reg_stat  = I2C1_STAT;
	dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
	dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
	dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
	dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
	dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */

	/* External Master 2 Bus */
	dev->i2c_bus[1].nr = 1;
	dev->i2c_bus[1].dev = dev;
	dev->i2c_bus[1].reg_stat  = I2C2_STAT;
	dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
	dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
	dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
	dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
	dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */

	/* Internal Master 3 Bus */
	dev->i2c_bus[2].nr = 2;
	dev->i2c_bus[2].dev = dev;
	dev->i2c_bus[2].reg_stat  = I2C3_STAT;
	dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
823
	dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
824 825 826 827
	dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
	dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
	dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */

828 829
	if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
		(cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
830
		cx23885_init_tsport(dev, &dev->ts1, 1);
831

832 833
	if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
		(cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
834
		cx23885_init_tsport(dev, &dev->ts2, 2);
835 836 837

	if (get_resources(dev) < 0) {
		printk(KERN_ERR "CORE %s No more PCIe resources for "
838 839 840
		       "subsystem: %04x:%04x\n",
		       dev->name, dev->pci->subsystem_vendor,
		       dev->pci->subsystem_device);
841 842

		cx23885_devcount--;
843
		return -ENODEV;
844 845 846
	}

	/* PCIe stuff */
847 848
	dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
			     pci_resource_len(dev->pci, 0));
849 850 851 852

	dev->bmmio = (u8 __iomem *)dev->lmmio;

	printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
853 854 855 856
	       dev->name, dev->pci->subsystem_vendor,
	       dev->pci->subsystem_device, cx23885_boards[dev->board].name,
	       dev->board, card[dev->nr] == dev->board ?
	       "insmod option" : "autodetected");
857

858 859
	cx23885_pci_quirks(dev);

860 861 862 863 864 865 866
	/* Assume some sensible defaults */
	dev->tuner_type = cx23885_boards[dev->board].tuner_type;
	dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
	dev->radio_type = cx23885_boards[dev->board].radio_type;
	dev->radio_addr = cx23885_boards[dev->board].radio_addr;

	dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
867
		__func__, dev->tuner_type, dev->tuner_addr);
868
	dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
869
		__func__, dev->radio_type, dev->radio_addr);
870

871 872 873 874 875 876 877
	/* init hardware */
	cx23885_reset(dev);

	cx23885_i2c_register(&dev->i2c_bus[0]);
	cx23885_i2c_register(&dev->i2c_bus[1]);
	cx23885_i2c_register(&dev->i2c_bus[2]);
	cx23885_card_setup(dev);
878
	call_all(dev, tuner, s_standby);
879 880
	cx23885_ir_init(dev);

881 882 883
	if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
		if (cx23885_video_register(dev) < 0) {
			printk(KERN_ERR "%s() Failed to register analog "
884
				"video adapters on VID_A\n", __func__);
885 886 887 888
		}
	}

	if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
889 890
		if (cx23885_dvb_register(&dev->ts1) < 0) {
			printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
891
			       __func__);
892
		}
893 894 895 896 897 898 899
	} else
	if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
		if (cx23885_417_register(dev) < 0) {
			printk(KERN_ERR
				"%s() Failed to register 417 on VID_B\n",
			       __func__);
		}
900 901
	}

902
	if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
903
		if (cx23885_dvb_register(&dev->ts2) < 0) {
904 905 906 907 908 909 910 911 912
			printk(KERN_ERR
				"%s() Failed to register dvb on VID_C\n",
			       __func__);
		}
	} else
	if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
		if (cx23885_417_register(dev) < 0) {
			printk(KERN_ERR
				"%s() Failed to register 417 on VID_C\n",
913
			       __func__);
914
		}
915 916
	}

917 918
	cx23885_dev_checkrevision(dev);

919 920 921
	return 0;
}

A
Adrian Bunk 已提交
922
static void cx23885_dev_unregister(struct cx23885_dev *dev)
923
{
924 925
	release_mem_region(pci_resource_start(dev->pci, 0),
			   pci_resource_len(dev->pci, 0));
926 927 928 929

	if (!atomic_dec_and_test(&dev->refcount))
		return;

930 931 932
	if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
		cx23885_video_unregister(dev);

933
	if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
934 935
		cx23885_dvb_unregister(&dev->ts1);

936 937 938 939
	if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
		cx23885_417_unregister(dev);

	if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
940 941
		cx23885_dvb_unregister(&dev->ts2);

942 943 944
	if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
		cx23885_417_unregister(dev);

945 946 947 948 949 950 951
	cx23885_i2c_unregister(&dev->i2c_bus[2]);
	cx23885_i2c_unregister(&dev->i2c_bus[1]);
	cx23885_i2c_unregister(&dev->i2c_bus[0]);

	iounmap(dev->lmmio);
}

952
static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
953 954 955
			       unsigned int offset, u32 sync_line,
			       unsigned int bpl, unsigned int padding,
			       unsigned int lines)
956 957
{
	struct scatterlist *sg;
958
	unsigned int line, todo;
959 960 961 962 963 964 965 966 967 968 969 970 971 972

	/* sync instruction */
	if (sync_line != NO_SYNC_LINE)
		*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);

	/* scan lines */
	sg = sglist;
	for (line = 0; line < lines; line++) {
		while (offset && offset >= sg_dma_len(sg)) {
			offset -= sg_dma_len(sg);
			sg++;
		}
		if (bpl <= sg_dma_len(sg)-offset) {
			/* fits into current chunk */
973 974 975 976
			*(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
			*(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
			*(rp++) = cpu_to_le32(0); /* bits 63-32 */
			offset += bpl;
977 978 979
		} else {
			/* scanline needs to be split */
			todo = bpl;
980
			*(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
981
					    (sg_dma_len(sg)-offset));
982 983
			*(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
			*(rp++) = cpu_to_le32(0); /* bits 63-32 */
984 985 986 987
			todo -= (sg_dma_len(sg)-offset);
			offset = 0;
			sg++;
			while (todo > sg_dma_len(sg)) {
988
				*(rp++) = cpu_to_le32(RISC_WRITE|
989
						    sg_dma_len(sg));
990 991
				*(rp++) = cpu_to_le32(sg_dma_address(sg));
				*(rp++) = cpu_to_le32(0); /* bits 63-32 */
992 993 994
				todo -= sg_dma_len(sg);
				sg++;
			}
995 996 997
			*(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
			*(rp++) = cpu_to_le32(sg_dma_address(sg));
			*(rp++) = cpu_to_le32(0); /* bits 63-32 */
998 999 1000 1001 1002 1003 1004 1005
			offset += todo;
		}
		offset += padding;
	}

	return rp;
}

1006 1007 1008 1009 1010 1011
int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
			struct scatterlist *sglist, unsigned int top_offset,
			unsigned int bottom_offset, unsigned int bpl,
			unsigned int padding, unsigned int lines)
{
	u32 instructions, fields;
A
Al Viro 已提交
1012
	__le32 *rp;
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025
	int rc;

	fields = 0;
	if (UNSET != top_offset)
		fields++;
	if (UNSET != bottom_offset)
		fields++;

	/* estimate risc mem: worst case is one write per page border +
	   one write per scan line + syncs + jump (all 2 dwords).  Padding
	   can cause next bpl to start close to a page border.  First DMA
	   region may be smaller than PAGE_SIZE */
	/* write and jump need and extra dword */
1026 1027
	instructions  = fields * (1 + ((bpl + padding) * lines)
		/ PAGE_SIZE + lines);
1028
	instructions += 2;
1029 1030
	rc = btcx_riscmem_alloc(pci, risc, instructions*12);
	if (rc < 0)
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043
		return rc;

	/* write risc instructions */
	rp = risc->cpu;
	if (UNSET != top_offset)
		rp = cx23885_risc_field(rp, sglist, top_offset, 0,
					bpl, padding, lines);
	if (UNSET != bottom_offset)
		rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
					bpl, padding, lines);

	/* save pointer to jmp instruction address */
	risc->jmp = rp;
1044
	BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1045 1046
	return 0;
}
1047

A
Adrian Bunk 已提交
1048 1049 1050 1051 1052
static int cx23885_risc_databuffer(struct pci_dev *pci,
				   struct btcx_riscmem *risc,
				   struct scatterlist *sglist,
				   unsigned int bpl,
				   unsigned int lines)
1053 1054
{
	u32 instructions;
A
Al Viro 已提交
1055
	__le32 *rp;
1056 1057 1058 1059 1060 1061 1062 1063 1064 1065
	int rc;

	/* estimate risc mem: worst case is one write per page border +
	   one write per scan line + syncs + jump (all 2 dwords).  Here
	   there is no padding and no sync.  First DMA region may be smaller
	   than PAGE_SIZE */
	/* Jump and write need an extra dword */
	instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
	instructions += 1;

1066 1067
	rc = btcx_riscmem_alloc(pci, risc, instructions*12);
	if (rc < 0)
1068 1069 1070 1071 1072 1073 1074 1075
		return rc;

	/* write risc instructions */
	rp = risc->cpu;
	rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);

	/* save pointer to jmp instruction address */
	risc->jmp = rp;
1076
	BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1077 1078 1079
	return 0;
}

1080
int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
A
Adrian Bunk 已提交
1081
				u32 reg, u32 mask, u32 value)
1082
{
A
Al Viro 已提交
1083
	__le32 *rp;
1084 1085
	int rc;

1086 1087
	rc = btcx_riscmem_alloc(pci, risc, 4*16);
	if (rc < 0)
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
		return rc;

	/* write risc instructions */
	rp = risc->cpu;
	*(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
	*(rp++) = cpu_to_le32(reg);
	*(rp++) = cpu_to_le32(value);
	*(rp++) = cpu_to_le32(mask);
	*(rp++) = cpu_to_le32(RISC_JUMP);
	*(rp++) = cpu_to_le32(risc->dma);
	*(rp++) = cpu_to_le32(0); /* bits 63-32 */
	return 0;
}

void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
{
1104 1105
	struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);

1106
	BUG_ON(in_interrupt());
1107
	videobuf_waiton(&buf->vb, 0, 0);
1108 1109
	videobuf_dma_unmap(q, dma);
	videobuf_dma_free(dma);
1110
	btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1111
	buf->vb.state = VIDEOBUF_NEEDS_INIT;
1112 1113
}

1114 1115 1116 1117
static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
{
	struct cx23885_dev *dev = port->dev;

1118 1119
	dprintk(1, "%s() Register Dump\n", __func__);
	dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __func__,
1120
		cx_read(DEV_CNTRL2));
1121
	dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __func__,
1122
		cx_read(PCI_INT_MSK));
1123
	dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __func__,
1124
		cx_read(AUDIO_INT_INT_MSK));
1125
	dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __func__,
1126
		cx_read(AUD_INT_DMA_CTL));
1127
	dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __func__,
1128
		cx_read(AUDIO_EXT_INT_MSK));
1129
	dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __func__,
1130
		cx_read(AUD_EXT_DMA_CTL));
1131
	dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __func__,
1132
		cx_read(PAD_CTRL));
1133
	dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __func__,
1134
		cx_read(ALT_PIN_OUT_SEL));
1135
	dprintk(1, "%s() GPIO2                    0x%08X\n", __func__,
1136
		cx_read(GPIO2));
1137
	dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __func__,
1138
		port->reg_gpcnt, cx_read(port->reg_gpcnt));
1139
	dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __func__,
1140
		port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1141
	dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __func__,
1142
		port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1143 1144 1145
	if (port->reg_src_sel)
		dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __func__,
			port->reg_src_sel, cx_read(port->reg_src_sel));
1146
	dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __func__,
1147
		port->reg_lngth, cx_read(port->reg_lngth));
1148
	dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __func__,
1149
		port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1150
	dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __func__,
1151
		port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1152
	dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __func__,
1153
		port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1154
	dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __func__,
1155
		port->reg_sop_status, cx_read(port->reg_sop_status));
1156
	dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1157
		port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1158
	dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __func__,
1159
		port->reg_vld_misc, cx_read(port->reg_vld_misc));
1160
	dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __func__,
1161
		port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1162
	dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __func__,
1163 1164 1165
		port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
}

1166
static int cx23885_start_dma(struct cx23885_tsport *port,
1167 1168
			     struct cx23885_dmaqueue *q,
			     struct cx23885_buffer   *buf)
1169 1170
{
	struct cx23885_dev *dev = port->dev;
1171
	u32 reg;
1172

1173
	dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1174
		buf->vb.width, buf->vb.height, buf->vb.field);
1175

1176 1177 1178
	/* Stop the fifo and risc engine for this port */
	cx_clear(port->reg_dma_ctl, port->dma_ctl_val);

1179 1180
	/* setup fifo + format */
	cx23885_sram_channel_setup(dev,
1181
				   &dev->sram_channels[port->sram_chno],
1182
				   port->ts_packet_size, buf->risc.dma);
1183 1184 1185
	if (debug > 5) {
		cx23885_sram_channel_dump(dev,
			&dev->sram_channels[port->sram_chno]);
1186
		cx23885_risc_disasm(port, &buf->risc);
1187
	}
1188 1189 1190 1191

	/* write TS length to chip */
	cx_write(port->reg_lngth, buf->vb.width);

1192 1193 1194
	if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
		(!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
		printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1195
			__func__,
1196
			cx23885_boards[dev->board].portb,
1197
			cx23885_boards[dev->board].portc);
1198 1199 1200
		return -EINVAL;
	}

1201 1202 1203
	if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
		cx23885_av_clk(dev, 0);

1204 1205
	udelay(100);

1206
	/* If the port supports SRC SELECT, configure it */
1207
	if (port->reg_src_sel)
1208 1209
		cx_write(port->reg_src_sel, port->src_sel_val);

1210
	cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1211
	cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1212
	cx_write(port->reg_vld_misc, port->vld_misc_val);
1213 1214 1215
	cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
	udelay(100);

1216
	/* NOTE: this is 2 (reserved) for portb, does it matter? */
1217 1218 1219 1220
	/* reset counter to zero */
	cx_write(port->reg_gpcnt_ctl, 3);
	q->count = 1;

1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
	/* Set VIDB pins to input */
	if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
		reg = cx_read(PAD_CTRL);
		reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
		cx_write(PAD_CTRL, reg);
	}

	/* Set VIDC pins to input */
	if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
		reg = cx_read(PAD_CTRL);
		reg &= ~0x4; /* Clear TS2_SOP_OE */
		cx_write(PAD_CTRL, reg);
	}

	if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249

		reg = cx_read(PAD_CTRL);
		reg = reg & ~0x1;    /* Clear TS1_OE */

		/* FIXME, bit 2 writing here is questionable */
		/* set TS1_SOP_OE and TS1_OE_HI */
		reg = reg | 0xa;
		cx_write(PAD_CTRL, reg);

		/* FIXME and these two registers should be documented. */
		cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
		cx_write(ALT_PIN_OUT_SEL, 0x10100045);
	}

1250
	switch (dev->bridge) {
1251
	case CX23885_BRIDGE_885:
1252
	case CX23885_BRIDGE_887:
1253
		/* enable irqs */
1254
		dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1255 1256 1257 1258 1259
		cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
		cx_set(port->reg_dma_ctl, port->dma_ctl_val);
		cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
		break;
	default:
1260
		BUG();
1261 1262 1263 1264
	}

	cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */

1265 1266 1267
	if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
		cx23885_av_clk(dev, 1);

1268 1269 1270
	if (debug > 4)
		cx23885_tsport_reg_dump(port);

1271 1272 1273 1274 1275 1276
	return 0;
}

static int cx23885_stop_dma(struct cx23885_tsport *port)
{
	struct cx23885_dev *dev = port->dev;
1277 1278
	u32 reg;

1279
	dprintk(1, "%s()\n", __func__);
1280 1281 1282 1283 1284

	/* Stop interrupts and DMA */
	cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
	cx_clear(port->reg_dma_ctl, port->dma_ctl_val);

1285
	if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302

		reg = cx_read(PAD_CTRL);

		/* Set TS1_OE */
		reg = reg | 0x1;

		/* clear TS1_SOP_OE and TS1_OE_HI */
		reg = reg & ~0xa;
		cx_write(PAD_CTRL, reg);
		cx_write(port->reg_src_sel, 0);
		cx_write(port->reg_gen_ctrl, 8);

	}

	if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
		cx23885_av_clk(dev, 0);

1303 1304 1305
	return 0;
}

1306
int cx23885_restart_queue(struct cx23885_tsport *port,
1307 1308 1309 1310 1311
				struct cx23885_dmaqueue *q)
{
	struct cx23885_dev *dev = port->dev;
	struct cx23885_buffer *buf;

1312
	dprintk(5, "%s()\n", __func__);
1313
	if (list_empty(&q->active)) {
1314 1315
		struct cx23885_buffer *prev;
		prev = NULL;
1316

1317
		dprintk(5, "%s() queue is empty\n", __func__);
1318

1319 1320 1321 1322 1323 1324 1325 1326 1327
		for (;;) {
			if (list_empty(&q->queued))
				return 0;
			buf = list_entry(q->queued.next, struct cx23885_buffer,
					 vb.queue);
			if (NULL == prev) {
				list_del(&buf->vb.queue);
				list_add_tail(&buf->vb.queue, &q->active);
				cx23885_start_dma(port, q, buf);
1328
				buf->vb.state = VIDEOBUF_ACTIVE;
1329 1330
				buf->count    = q->count++;
				mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1331
				dprintk(5, "[%p/%d] restart_queue - f/active\n",
1332 1333 1334 1335 1336 1337 1338
					buf, buf->vb.i);

			} else if (prev->vb.width  == buf->vb.width  &&
				   prev->vb.height == buf->vb.height &&
				   prev->fmt       == buf->fmt) {
				list_del(&buf->vb.queue);
				list_add_tail(&buf->vb.queue, &q->active);
1339
				buf->vb.state = VIDEOBUF_ACTIVE;
1340 1341
				buf->count    = q->count++;
				prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1342 1343 1344
				/* 64 bit bits 63-32 */
				prev->risc.jmp[2] = cpu_to_le32(0);
				dprintk(5, "[%p/%d] restart_queue - m/active\n",
1345 1346 1347 1348 1349 1350
					buf, buf->vb.i);
			} else {
				return 0;
			}
			prev = buf;
		}
1351 1352 1353 1354
		return 0;
	}

	buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1355
	dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1356 1357
		buf, buf->vb.i);
	cx23885_start_dma(port, q, buf);
1358
	list_for_each_entry(buf, &q->active, vb.queue)
1359
		buf->count = q->count++;
1360
	mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
	return 0;
}

/* ------------------------------------------------------------------ */

int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
			struct cx23885_buffer *buf, enum v4l2_field field)
{
	struct cx23885_dev *dev = port->dev;
	int size = port->ts_packet_size * port->ts_packet_count;
	int rc;

1373
	dprintk(1, "%s: %p\n", __func__, buf);
1374 1375 1376
	if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
		return -EINVAL;

1377
	if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1378 1379 1380 1381 1382
		buf->vb.width  = port->ts_packet_size;
		buf->vb.height = port->ts_packet_count;
		buf->vb.size   = size;
		buf->vb.field  = field /*V4L2_FIELD_TOP*/;

1383 1384
		rc = videobuf_iolock(q, &buf->vb, NULL);
		if (0 != rc)
1385 1386
			goto fail;
		cx23885_risc_databuffer(dev->pci, &buf->risc,
1387 1388
					videobuf_to_dma(&buf->vb)->sglist,
					buf->vb.width, buf->vb.height);
1389
	}
1390
	buf->vb.state = VIDEOBUF_PREPARED;
1391 1392 1393
	return 0;

 fail:
1394
	cx23885_free_buffer(q, buf);
1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409
	return rc;
}

void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
{
	struct cx23885_buffer    *prev;
	struct cx23885_dev *dev = port->dev;
	struct cx23885_dmaqueue  *cx88q = &port->mpegq;

	/* add jump to stopper */
	buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
	buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
	buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */

	if (list_empty(&cx88q->active)) {
1410
		dprintk(1, "queue is empty - first active\n");
1411
		list_add_tail(&buf->vb.queue, &cx88q->active);
1412
		cx23885_start_dma(port, cx88q, buf);
1413
		buf->vb.state = VIDEOBUF_ACTIVE;
1414
		buf->count    = cx88q->count++;
1415 1416
		mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
		dprintk(1, "[%p/%d] %s - first active\n",
1417
			buf, buf->vb.i, __func__);
1418
	} else {
1419
		dprintk(1, "queue is not empty - append to active\n");
1420 1421 1422
		prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
				  vb.queue);
		list_add_tail(&buf->vb.queue, &cx88q->active);
1423
		buf->vb.state = VIDEOBUF_ACTIVE;
1424 1425 1426
		buf->count    = cx88q->count++;
		prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
		prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1427
		dprintk(1, "[%p/%d] %s - append to active\n",
1428
			 buf, buf->vb.i, __func__);
1429 1430 1431 1432 1433
	}
}

/* ----------------------------------------------------------- */

1434 1435
static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
			      int restart)
1436 1437 1438 1439 1440 1441
{
	struct cx23885_dev *dev = port->dev;
	struct cx23885_dmaqueue *q = &port->mpegq;
	struct cx23885_buffer *buf;
	unsigned long flags;

1442
	spin_lock_irqsave(&port->slock, flags);
1443
	while (!list_empty(&q->active)) {
1444 1445
		buf = list_entry(q->active.next, struct cx23885_buffer,
				 vb.queue);
1446
		list_del(&buf->vb.queue);
1447
		buf->vb.state = VIDEOBUF_ERROR;
1448
		wake_up(&buf->vb.done);
1449
		dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1450 1451
			buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
	}
1452
	if (restart) {
1453
		dprintk(1, "restarting queue\n");
1454 1455
		cx23885_restart_queue(port, q);
	}
1456
	spin_unlock_irqrestore(&port->slock, flags);
1457 1458
}

1459 1460 1461 1462 1463
void cx23885_cancel_buffers(struct cx23885_tsport *port)
{
	struct cx23885_dev *dev = port->dev;
	struct cx23885_dmaqueue *q = &port->mpegq;

1464
	dprintk(1, "%s()\n", __func__);
1465 1466 1467 1468
	del_timer_sync(&q->timeout);
	cx23885_stop_dma(port);
	do_cancel_buffers(port, "cancel", 0);
}
1469 1470 1471 1472 1473 1474

static void cx23885_timeout(unsigned long data)
{
	struct cx23885_tsport *port = (struct cx23885_tsport *)data;
	struct cx23885_dev *dev = port->dev;

1475
	dprintk(1, "%s()\n", __func__);
1476 1477

	if (debug > 5)
1478 1479
		cx23885_sram_channel_dump(dev,
			&dev->sram_channels[port->sram_chno]);
1480

1481 1482 1483 1484
	cx23885_stop_dma(port);
	do_cancel_buffers(port, "timeout", 1);
}

1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545
int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
{
	/* FIXME: port1 assumption here. */
	struct cx23885_tsport *port = &dev->ts1;
	int count = 0;
	int handled = 0;

	if (status == 0)
		return handled;

	count = cx_read(port->reg_gpcnt);
	dprintk(7, "status: 0x%08x  mask: 0x%08x count: 0x%x\n",
		status, cx_read(port->reg_ts_int_msk), count);

	if ((status & VID_B_MSK_BAD_PKT)         ||
		(status & VID_B_MSK_OPC_ERR)     ||
		(status & VID_B_MSK_VBI_OPC_ERR) ||
		(status & VID_B_MSK_SYNC)        ||
		(status & VID_B_MSK_VBI_SYNC)    ||
		(status & VID_B_MSK_OF)          ||
		(status & VID_B_MSK_VBI_OF)) {
		printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
			"= 0x%x\n", dev->name, status);
		if (status & VID_B_MSK_BAD_PKT)
			dprintk(1, "        VID_B_MSK_BAD_PKT\n");
		if (status & VID_B_MSK_OPC_ERR)
			dprintk(1, "        VID_B_MSK_OPC_ERR\n");
		if (status & VID_B_MSK_VBI_OPC_ERR)
			dprintk(1, "        VID_B_MSK_VBI_OPC_ERR\n");
		if (status & VID_B_MSK_SYNC)
			dprintk(1, "        VID_B_MSK_SYNC\n");
		if (status & VID_B_MSK_VBI_SYNC)
			dprintk(1, "        VID_B_MSK_VBI_SYNC\n");
		if (status & VID_B_MSK_OF)
			dprintk(1, "        VID_B_MSK_OF\n");
		if (status & VID_B_MSK_VBI_OF)
			dprintk(1, "        VID_B_MSK_VBI_OF\n");

		cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
		cx23885_sram_channel_dump(dev,
			&dev->sram_channels[port->sram_chno]);
		cx23885_417_check_encoder(dev);
	} else if (status & VID_B_MSK_RISCI1) {
		dprintk(7, "        VID_B_MSK_RISCI1\n");
		spin_lock(&port->slock);
		cx23885_wakeup(port, &port->mpegq, count);
		spin_unlock(&port->slock);
	} else if (status & VID_B_MSK_RISCI2) {
		dprintk(7, "        VID_B_MSK_RISCI2\n");
		spin_lock(&port->slock);
		cx23885_restart_queue(port, &port->mpegq);
		spin_unlock(&port->slock);
	}
	if (status) {
		cx_write(port->reg_ts_int_stat, status);
		handled = 1;
	}

	return handled;
}

1546 1547 1548 1549 1550 1551
static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
{
	struct cx23885_dev *dev = port->dev;
	int handled = 0;
	u32 count;

1552 1553 1554
	if ((status & VID_BC_MSK_OPC_ERR) ||
		(status & VID_BC_MSK_BAD_PKT) ||
		(status & VID_BC_MSK_SYNC) ||
1555 1556
		(status & VID_BC_MSK_OF)) {

1557
		if (status & VID_BC_MSK_OPC_ERR)
1558 1559 1560
			dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
				VID_BC_MSK_OPC_ERR);

1561
		if (status & VID_BC_MSK_BAD_PKT)
1562 1563 1564
			dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
				VID_BC_MSK_BAD_PKT);

1565
		if (status & VID_BC_MSK_SYNC)
1566 1567 1568
			dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n",
				VID_BC_MSK_SYNC);

1569
		if (status & VID_BC_MSK_OF)
1570 1571
			dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n",
				VID_BC_MSK_OF);
1572 1573 1574 1575

		printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);

		cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1576 1577
		cx23885_sram_channel_dump(dev,
			&dev->sram_channels[port->sram_chno]);
1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604

	} else if (status & VID_BC_MSK_RISCI1) {

		dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);

		spin_lock(&port->slock);
		count = cx_read(port->reg_gpcnt);
		cx23885_wakeup(port, &port->mpegq, count);
		spin_unlock(&port->slock);

	} else if (status & VID_BC_MSK_RISCI2) {

		dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);

		spin_lock(&port->slock);
		cx23885_restart_queue(port, &port->mpegq);
		spin_unlock(&port->slock);

	}
	if (status) {
		cx_write(port->reg_ts_int_stat, status);
		handled = 1;
	}

	return handled;
}

1605
static irqreturn_t cx23885_irq(int irq, void *dev_id)
1606 1607
{
	struct cx23885_dev *dev = dev_id;
1608 1609
	struct cx23885_tsport *ts1 = &dev->ts1;
	struct cx23885_tsport *ts2 = &dev->ts2;
1610
	u32 pci_status, pci_mask;
1611
	u32 vida_status, vida_mask;
1612
	u32 ts1_status, ts1_mask;
1613
	u32 ts2_status, ts2_mask;
1614
	int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1615 1616 1617

	pci_status = cx_read(PCI_INT_STAT);
	pci_mask = cx_read(PCI_INT_MSK);
1618 1619
	vida_status = cx_read(VID_A_INT_STAT);
	vida_mask = cx_read(VID_A_INT_MSK);
1620 1621
	ts1_status = cx_read(VID_B_INT_STAT);
	ts1_mask = cx_read(VID_B_INT_MSK);
1622 1623 1624
	ts2_status = cx_read(VID_C_INT_STAT);
	ts2_mask = cx_read(VID_C_INT_MSK);

1625
	if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1626 1627
		goto out;

1628
	vida_count = cx_read(VID_A_GPCNT);
1629 1630
	ts1_count = cx_read(ts1->reg_gpcnt);
	ts2_count = cx_read(ts2->reg_gpcnt);
1631 1632 1633 1634 1635 1636 1637 1638
	dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
		pci_status, pci_mask);
	dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
		vida_status, vida_mask, vida_count);
	dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
		ts1_status, ts1_mask, ts1_count);
	dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
		ts2_status, ts2_mask, ts2_count);
1639

1640 1641 1642 1643 1644 1645 1646 1647 1648
	if ((pci_status & PCI_MSK_RISC_RD) ||
	    (pci_status & PCI_MSK_RISC_WR) ||
	    (pci_status & PCI_MSK_AL_RD) ||
	    (pci_status & PCI_MSK_AL_WR) ||
	    (pci_status & PCI_MSK_APB_DMA) ||
	    (pci_status & PCI_MSK_VID_C) ||
	    (pci_status & PCI_MSK_VID_B) ||
	    (pci_status & PCI_MSK_VID_A) ||
	    (pci_status & PCI_MSK_AUD_INT) ||
1649 1650 1651
	    (pci_status & PCI_MSK_AUD_EXT) ||
	    (pci_status & PCI_MSK_GPIO0) ||
	    (pci_status & PCI_MSK_GPIO1)) {
1652 1653

		if (pci_status & PCI_MSK_RISC_RD)
1654 1655 1656
			dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n",
				PCI_MSK_RISC_RD);

1657
		if (pci_status & PCI_MSK_RISC_WR)
1658 1659 1660
			dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n",
				PCI_MSK_RISC_WR);

1661
		if (pci_status & PCI_MSK_AL_RD)
1662 1663 1664
			dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n",
				PCI_MSK_AL_RD);

1665
		if (pci_status & PCI_MSK_AL_WR)
1666 1667 1668
			dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n",
				PCI_MSK_AL_WR);

1669
		if (pci_status & PCI_MSK_APB_DMA)
1670 1671 1672
			dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n",
				PCI_MSK_APB_DMA);

1673
		if (pci_status & PCI_MSK_VID_C)
1674 1675 1676
			dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n",
				PCI_MSK_VID_C);

1677
		if (pci_status & PCI_MSK_VID_B)
1678 1679 1680
			dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n",
				PCI_MSK_VID_B);

1681
		if (pci_status & PCI_MSK_VID_A)
1682 1683 1684
			dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n",
				PCI_MSK_VID_A);

1685
		if (pci_status & PCI_MSK_AUD_INT)
1686 1687 1688
			dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n",
				PCI_MSK_AUD_INT);

1689
		if (pci_status & PCI_MSK_AUD_EXT)
1690 1691
			dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n",
				PCI_MSK_AUD_EXT);
1692

1693 1694 1695 1696 1697 1698 1699
		if (pci_status & PCI_MSK_GPIO0)
			dprintk(7, " (PCI_MSK_GPIO0     0x%08x)\n",
				PCI_MSK_GPIO0);

		if (pci_status & PCI_MSK_GPIO1)
			dprintk(7, " (PCI_MSK_GPIO1     0x%08x)\n",
				PCI_MSK_GPIO1);
1700 1701
	}

1702 1703
	if (cx23885_boards[dev->board].cimax > 0 &&
		((pci_status & PCI_MSK_GPIO0) || (pci_status & PCI_MSK_GPIO1)))
1704 1705 1706
		/* handled += cx23885_irq_gpio(dev, pci_status); */
		handled += netup_ci_slot_status(dev, pci_status);

1707 1708 1709
	if (ts1_status) {
		if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
			handled += cx23885_irq_ts(ts1, ts1_status);
1710 1711 1712
		else
		if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
			handled += cx23885_irq_417(dev, ts1_status);
1713 1714 1715 1716 1717
	}

	if (ts2_status) {
		if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
			handled += cx23885_irq_ts(ts2, ts2_status);
1718 1719 1720
		else
		if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
			handled += cx23885_irq_417(dev, ts2_status);
1721
	}
1722

1723 1724
	if (vida_status)
		handled += cx23885_video_irq(dev, vida_status);
1725 1726 1727

	if (handled)
		cx_write(PCI_INT_STAT, pci_status);
1728 1729 1730 1731 1732
out:
	return IRQ_RETVAL(handled);
}

static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1733
				     const struct pci_device_id *pci_id)
1734 1735 1736 1737
{
	struct cx23885_dev *dev;
	int err;

1738
	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1739 1740 1741
	if (NULL == dev)
		return -ENOMEM;

1742 1743 1744 1745
	err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
	if (err < 0)
		goto fail_free;

1746 1747 1748 1749
	/* pci init */
	dev->pci = pci_dev;
	if (pci_enable_device(pci_dev)) {
		err = -EIO;
1750
		goto fail_unreg;
1751 1752 1753 1754
	}

	if (cx23885_dev_setup(dev) < 0) {
		err = -EINVAL;
1755
		goto fail_unreg;
1756 1757 1758 1759 1760 1761 1762 1763
	}

	/* print pci info */
	pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
	pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
	printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
	       "latency: %d, mmio: 0x%llx\n", dev->name,
	       pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1764 1765
	       dev->pci_lat,
		(unsigned long long)pci_resource_start(pci_dev, 0));
1766 1767 1768 1769 1770 1771 1772 1773

	pci_set_master(pci_dev);
	if (!pci_dma_supported(pci_dev, 0xffffffff)) {
		printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
		err = -EIO;
		goto fail_irq;
	}

1774 1775
	err = request_irq(pci_dev->irq, cx23885_irq,
			  IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1776 1777 1778 1779 1780 1781
	if (err < 0) {
		printk(KERN_ERR "%s: can't get IRQ %d\n",
		       dev->name, pci_dev->irq);
		goto fail_irq;
	}

1782 1783 1784 1785 1786
	switch (dev->board) {
	case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
		cx_set(PCI_INT_MSK, 0x01800000); /* for NetUP */
		break;
	}
1787

1788 1789 1790 1791
	return 0;

fail_irq:
	cx23885_dev_unregister(dev);
1792 1793
fail_unreg:
	v4l2_device_unregister(&dev->v4l2_dev);
1794 1795 1796 1797 1798 1799 1800
fail_free:
	kfree(dev);
	return err;
}

static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
{
1801 1802
	struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
	struct cx23885_dev *dev = to_cx23885(v4l2_dev);
1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815

	cx23885_shutdown(dev);

	pci_disable_device(pci_dev);

	/* unregister stuff */
	free_irq(pci_dev->irq, dev);

	mutex_lock(&devlist);
	list_del(&dev->devlist);
	mutex_unlock(&devlist);

	cx23885_dev_unregister(dev);
1816
	v4l2_device_unregister(v4l2_dev);
1817 1818 1819 1820 1821 1822 1823 1824 1825 1826
	kfree(dev);
}

static struct pci_device_id cx23885_pci_tbl[] = {
	{
		/* CX23885 */
		.vendor       = 0x14f1,
		.device       = 0x8852,
		.subvendor    = PCI_ANY_ID,
		.subdevice    = PCI_ANY_ID,
1827
	}, {
1828 1829 1830 1831 1832
		/* CX23887 Rev 2 */
		.vendor       = 0x14f1,
		.device       = 0x8880,
		.subvendor    = PCI_ANY_ID,
		.subdevice    = PCI_ANY_ID,
1833
	}, {
1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851
		/* --- end of list --- */
	}
};
MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);

static struct pci_driver cx23885_pci_driver = {
	.name     = "cx23885",
	.id_table = cx23885_pci_tbl,
	.probe    = cx23885_initdev,
	.remove   = __devexit_p(cx23885_finidev),
	/* TODO */
	.suspend  = NULL,
	.resume   = NULL,
};

static int cx23885_init(void)
{
	printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
S
Steven Toth 已提交
1852 1853 1854
	       (CX23885_VERSION_CODE >> 16) & 0xff,
	       (CX23885_VERSION_CODE >>  8) & 0xff,
	       CX23885_VERSION_CODE & 0xff);
1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870
#ifdef SNAPSHOT
	printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
	       SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
#endif
	return pci_register_driver(&cx23885_pci_driver);
}

static void cx23885_fini(void)
{
	pci_unregister_driver(&cx23885_pci_driver);
}

module_init(cx23885_init);
module_exit(cx23885_fini);

/* ----------------------------------------------------------- */