hazards.h 5.8 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
6
 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
7 8
 * Copyright (C) MIPS Technologies, Inc.
 *   written by Ralf Baechle <ralf@linux-mips.org>
L
Linus Torvalds 已提交
9 10 11 12
 */
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H

13
#ifdef __ASSEMBLY__
R
Ralf Baechle 已提交
14
#define ASMMACRO(name, code...) .macro name; code; .endm
L
Linus Torvalds 已提交
15 16
#else

17 18
#include <asm/cpu-features.h>

R
Ralf Baechle 已提交
19 20 21 22 23 24 25
#define ASMMACRO(name, code...)						\
__asm__(".macro " #name "; " #code "; .endm");				\
									\
static inline void name(void)						\
{									\
	__asm__ __volatile__ (#name);					\
}
L
Linus Torvalds 已提交
26

27 28 29 30 31
/*
 * MIPS R2 instruction hazard barrier.   Needs to be called as a subroutine.
 */
extern void mips_ihb(void);

L
Linus Torvalds 已提交
32 33
#endif

R
Ralf Baechle 已提交
34 35 36 37 38 39 40 41
ASMMACRO(_ssnop,
	 sll	$0, $0, 1
	)

ASMMACRO(_ehb,
	 sll	$0, $0, 3
	)

L
Linus Torvalds 已提交
42
/*
R
Ralf Baechle 已提交
43
 * TLB hazards
L
Linus Torvalds 已提交
44
 */
45
#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
L
Linus Torvalds 已提交
46 47

/*
R
Ralf Baechle 已提交
48
 * MIPSR2 defines ehb for hazard avoidance
L
Linus Torvalds 已提交
49 50
 */

R
Ralf Baechle 已提交
51 52 53 54 55 56 57 58 59 60
ASMMACRO(mtc0_tlbw_hazard,
	 _ehb
	)
ASMMACRO(tlbw_use_hazard,
	 _ehb
	)
ASMMACRO(tlb_probe_hazard,
	 _ehb
	)
ASMMACRO(irq_enable_hazard,
R
Ralf Baechle 已提交
61
	 _ehb
R
Ralf Baechle 已提交
62 63
	)
ASMMACRO(irq_disable_hazard,
L
Linus Torvalds 已提交
64
	_ehb
R
Ralf Baechle 已提交
65 66 67 68
	)
ASMMACRO(back_to_back_c0_hazard,
	 _ehb
	)
L
Linus Torvalds 已提交
69
/*
R
Ralf Baechle 已提交
70 71 72 73 74 75
 * gcc has a tradition of misscompiling the previous construct using the
 * address of a label as argument to inline assembler.  Gas otoh has the
 * annoying difference between la and dla which are only usable for 32-bit
 * rsp. 64-bit code, so can't be used without conditional compilation.
 * The alterantive is switching the assembler to 64-bit code which happens
 * to work right even for 32-bit code ...
L
Linus Torvalds 已提交
76
 */
R
Ralf Baechle 已提交
77 78 79 80 81 82 83 84 85 86 87 88
#define instruction_hazard()						\
do {									\
	unsigned long tmp;						\
									\
	__asm__ __volatile__(						\
	"	.set	mips64r2				\n"	\
	"	dla	%0, 1f					\n"	\
	"	jr.hb	%0					\n"	\
	"	.set	mips0					\n"	\
	"1:							\n"	\
	: "=r" (tmp));							\
} while (0)
L
Linus Torvalds 已提交
89

90
#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140

/*
 * These are slightly complicated by the fact that we guarantee R1 kernels to
 * run fine on R2 processors.
 */
ASMMACRO(mtc0_tlbw_hazard,
	_ssnop; _ssnop; _ehb
	)
ASMMACRO(tlbw_use_hazard,
	_ssnop; _ssnop; _ssnop; _ehb
	)
ASMMACRO(tlb_probe_hazard,
	 _ssnop; _ssnop; _ssnop; _ehb
	)
ASMMACRO(irq_enable_hazard,
	 _ssnop; _ssnop; _ssnop; _ehb
	)
ASMMACRO(irq_disable_hazard,
	_ssnop; _ssnop; _ssnop; _ehb
	)
ASMMACRO(back_to_back_c0_hazard,
	 _ssnop; _ssnop; _ssnop; _ehb
	)
/*
 * gcc has a tradition of misscompiling the previous construct using the
 * address of a label as argument to inline assembler.  Gas otoh has the
 * annoying difference between la and dla which are only usable for 32-bit
 * rsp. 64-bit code, so can't be used without conditional compilation.
 * The alterantive is switching the assembler to 64-bit code which happens
 * to work right even for 32-bit code ...
 */
#define __instruction_hazard()						\
do {									\
	unsigned long tmp;						\
									\
	__asm__ __volatile__(						\
	"	.set	mips64r2				\n"	\
	"	dla	%0, 1f					\n"	\
	"	jr.hb	%0					\n"	\
	"	.set	mips0					\n"	\
	"1:							\n"	\
	: "=r" (tmp));							\
} while (0)

#define instruction_hazard()						\
do {									\
	if (cpu_has_mips_r2)						\
		__instruction_hazard();					\
} while (0)

141 142 143
#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
      defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
      defined(CONFIG_CPU_R5500)
L
Linus Torvalds 已提交
144 145

/*
R
Ralf Baechle 已提交
146
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
L
Linus Torvalds 已提交
147 148
 */

R
Ralf Baechle 已提交
149 150 151 152 153 154 155 156 157 158 159 160 161
ASMMACRO(mtc0_tlbw_hazard,
	)
ASMMACRO(tlbw_use_hazard,
	)
ASMMACRO(tlb_probe_hazard,
	)
ASMMACRO(irq_enable_hazard,
	)
ASMMACRO(irq_disable_hazard,
	)
ASMMACRO(back_to_back_c0_hazard,
	)
#define instruction_hazard() do { } while (0)
L
Linus Torvalds 已提交
162

R
Ralf Baechle 已提交
163
#elif defined(CONFIG_CPU_RM9000)
164

L
Linus Torvalds 已提交
165 166 167 168 169 170
/*
 * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
 * for data translations should not occur for 3 cpu cycles.
 */

R
Ralf Baechle 已提交
171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
ASMMACRO(mtc0_tlbw_hazard,
	 _ssnop; _ssnop; _ssnop; _ssnop
	)
ASMMACRO(tlbw_use_hazard,
	 _ssnop; _ssnop; _ssnop; _ssnop
	)
ASMMACRO(tlb_probe_hazard,
	 _ssnop; _ssnop; _ssnop; _ssnop
	)
ASMMACRO(irq_enable_hazard,
	)
ASMMACRO(irq_disable_hazard,
	)
ASMMACRO(back_to_back_c0_hazard,
	)
#define instruction_hazard() do { } while (0)
L
Linus Torvalds 已提交
187

R
Ralf Baechle 已提交
188
#elif defined(CONFIG_CPU_SB1)
L
Linus Torvalds 已提交
189 190

/*
R
Ralf Baechle 已提交
191
 * Mostly like R4000 for historic reasons
L
Linus Torvalds 已提交
192
 */
R
Ralf Baechle 已提交
193 194 195 196 197 198 199 200 201 202 203 204 205 206
ASMMACRO(mtc0_tlbw_hazard,
	)
ASMMACRO(tlbw_use_hazard,
	)
ASMMACRO(tlb_probe_hazard,
	)
ASMMACRO(irq_enable_hazard,
	)
ASMMACRO(irq_disable_hazard,
	 _ssnop; _ssnop; _ssnop
	)
ASMMACRO(back_to_back_c0_hazard,
	)
#define instruction_hazard() do { } while (0)
207

L
Linus Torvalds 已提交
208 209 210
#else

/*
R
Ralf Baechle 已提交
211 212
 * Finally the catchall case for all other processors including R4000, R4400,
 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
213
 *
R
Ralf Baechle 已提交
214 215 216 217
 * The taken branch will result in a two cycle penalty for the two killed
 * instructions on R4000 / R4400.  Other processors only have a single cycle
 * hazard so this is nice trick to have an optimal code for a range of
 * processors.
218
 */
R
Ralf Baechle 已提交
219
ASMMACRO(mtc0_tlbw_hazard,
220
	nop; nop
R
Ralf Baechle 已提交
221 222 223 224 225 226 227 228
	)
ASMMACRO(tlbw_use_hazard,
	nop; nop; nop
	)
ASMMACRO(tlb_probe_hazard,
	 nop; nop; nop
	)
ASMMACRO(irq_enable_hazard,
229
	 _ssnop; _ssnop; _ssnop;
R
Ralf Baechle 已提交
230 231 232 233 234 235 236
	)
ASMMACRO(irq_disable_hazard,
	nop; nop; nop
	)
ASMMACRO(back_to_back_c0_hazard,
	 _ssnop; _ssnop; _ssnop;
	)
237
#define instruction_hazard() do { } while (0)
238

R
Ralf Baechle 已提交
239
#endif
L
Linus Torvalds 已提交
240

C
Chris Dearman 已提交
241 242 243 244 245 246 247 248 249

/* FPU hazards */

#if defined(CONFIG_CPU_SB1)
ASMMACRO(enable_fpu_hazard,
	 .set	push;
	 .set	mips64;
	 .set	noreorder;
	 _ssnop;
250
	 bnezl	$0, .+4;
R
Ralf Baechle 已提交
251
	 _ssnop;
C
Chris Dearman 已提交
252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272
	 .set	pop
)
ASMMACRO(disable_fpu_hazard,
)

#elif defined(CONFIG_CPU_MIPSR2)
ASMMACRO(enable_fpu_hazard,
	 _ehb
)
ASMMACRO(disable_fpu_hazard,
	 _ehb
)
#else
ASMMACRO(enable_fpu_hazard,
	 nop; nop; nop; nop
)
ASMMACRO(disable_fpu_hazard,
	 _ehb
)
#endif

L
Linus Torvalds 已提交
273
#endif /* _ASM_HAZARDS_H */