dpc.c 8.7 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
 * PCI Express Downstream Port Containment services driver
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 * Author: Keith Busch <keith.busch@intel.com>
 *
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 * Copyright (C) 2016 Intel Corp.
 */

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#include <linux/aer.h>
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#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include "portdrv.h"
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#include "../pci.h"
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struct dpc_dev {
	struct pcie_device	*dev;
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	u16			cap_pos;
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	bool			rp_extensions;
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	u8			rp_log_size;
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};

static const char * const rp_pio_error_string[] = {
	"Configuration Request received UR Completion",	 /* Bit Position 0  */
	"Configuration Request received CA Completion",	 /* Bit Position 1  */
	"Configuration Request Completion Timeout",	 /* Bit Position 2  */
	NULL,
	NULL,
	NULL,
	NULL,
	NULL,
	"I/O Request received UR Completion",		 /* Bit Position 8  */
	"I/O Request received CA Completion",		 /* Bit Position 9  */
	"I/O Request Completion Timeout",		 /* Bit Position 10 */
	NULL,
	NULL,
	NULL,
	NULL,
	NULL,
	"Memory Request received UR Completion",	 /* Bit Position 16 */
	"Memory Request received CA Completion",	 /* Bit Position 17 */
	"Memory Request Completion Timeout",		 /* Bit Position 18 */
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};

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static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
{
	unsigned long timeout = jiffies + HZ;
	struct pci_dev *pdev = dpc->dev->port;
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	struct device *dev = &dpc->dev->device;
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	u16 cap = dpc->cap_pos, status;
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	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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	while (status & PCI_EXP_DPC_RP_BUSY &&
					!time_after(jiffies, timeout)) {
		msleep(10);
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		pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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	}
	if (status & PCI_EXP_DPC_RP_BUSY) {
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		dev_warn(dev, "DPC root port still busy\n");
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		return -EBUSY;
	}
	return 0;
}

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static void dpc_wait_link_inactive(struct dpc_dev *dpc)
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{
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	struct pci_dev *pdev = dpc->dev->port;
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	pcie_wait_for_link(pdev, false);
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}

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static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
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{
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	struct dpc_dev *dpc;
	struct pcie_device *pciedev;
	struct device *devdpc;
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	u16 cap;
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	/*
	 * DPC disables the Link automatically in hardware, so it has
	 * already been reset by the time we get here.
	 */
	devdpc = pcie_port_find_device(pdev, PCIE_PORT_SERVICE_DPC);
	pciedev = to_pcie_device(devdpc);
	dpc = get_service_data(pciedev);
	cap = dpc->cap_pos;

	/*
	 * Wait until the Link is inactive, then clear DPC Trigger Status
	 * to allow the Port to leave DPC.
	 */
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	dpc_wait_link_inactive(dpc);
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	if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
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		return PCI_ERS_RESULT_DISCONNECT;
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	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
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			      PCI_EXP_DPC_STATUS_TRIGGER);
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	return PCI_ERS_RESULT_RECOVERED;
}

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static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
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{
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	struct device *dev = &dpc->dev->device;
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	struct pci_dev *pdev = dpc->dev->port;
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	u16 cap = dpc->cap_pos, dpc_status, first_error;
	u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
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	int i;

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	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
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	dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
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		status, mask);
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	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
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	dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
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		sev, syserr, exc);
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	/* Get First Error Pointer */
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	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
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	first_error = (dpc_status & 0x1f00) >> 8;
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	for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
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		if ((status & ~mask) & (1 << i))
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			dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
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				first_error == i ? " (First)" : "");
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	}

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	if (dpc->rp_log_size < 4)
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		goto clear_status;
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	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
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			      &dw0);
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	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
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			      &dw1);
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	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
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			      &dw2);
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	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
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			      &dw3);
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	dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
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		dw0, dw1, dw2, dw3);
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	if (dpc->rp_log_size < 5)
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		goto clear_status;
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	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
	dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
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	for (i = 0; i < dpc->rp_log_size - 5; i++) {
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		pci_read_config_dword(pdev,
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			cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
		dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
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	}
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 clear_status:
	pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
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}

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static irqreturn_t dpc_handler(int irq, void *context)
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{
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	struct aer_err_info info;
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	struct dpc_dev *dpc = context;
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	struct pci_dev *pdev = dpc->dev->port;
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	struct device *dev = &dpc->dev->device;
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	u16 cap = dpc->cap_pos, status, source, reason, ext_reason;
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	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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	pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
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	dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
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		 status, source);
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	reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
	ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
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	dev_warn(dev, "DPC %s detected, remove downstream devices\n",
		 (reason == 0) ? "unmasked uncorrectable error" :
		 (reason == 1) ? "ERR_NONFATAL" :
		 (reason == 2) ? "ERR_FATAL" :
		 (ext_reason == 0) ? "RP PIO error" :
		 (ext_reason == 1) ? "software trigger" :
				     "reserved error");
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	/* show RP PIO error detail information */
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	if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
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		dpc_process_rp_pio_error(dpc);
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	else if (reason == 0 && aer_get_device_error_info(pdev, &info)) {
		aer_print_error(pdev, &info);
		pci_cleanup_aer_uncorrect_error_status(pdev);
	}
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	/* We configure DPC so it only triggers on ERR_FATAL */
	pcie_do_fatal_recovery(pdev, PCIE_PORT_SERVICE_DPC);
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	return IRQ_HANDLED;
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}

static irqreturn_t dpc_irq(int irq, void *context)
{
	struct dpc_dev *dpc = (struct dpc_dev *)context;
	struct pci_dev *pdev = dpc->dev->port;
	u16 cap = dpc->cap_pos, status;

	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);

	if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || status == (u16)(~0))
		return IRQ_NONE;

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	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
			      PCI_EXP_DPC_STATUS_INTERRUPT);
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	if (status & PCI_EXP_DPC_STATUS_TRIGGER)
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		return IRQ_WAKE_THREAD;
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	return IRQ_HANDLED;
}

#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
static int dpc_probe(struct pcie_device *dev)
{
	struct dpc_dev *dpc;
	struct pci_dev *pdev = dev->port;
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	struct device *device = &dev->device;
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	int status;
	u16 ctl, cap;

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	if (pcie_aer_get_firmware_first(pdev))
		return -ENOTSUPP;

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	dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
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	if (!dpc)
		return -ENOMEM;

	dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
	dpc->dev = dev;
	set_service_data(dev, dpc);

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	status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
					   dpc_handler, IRQF_SHARED,
					   "pcie-dpc", dpc);
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	if (status) {
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		dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
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			 status);
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		return status;
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	}

	pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
	pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);

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	dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
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	if (dpc->rp_extensions) {
		dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
		if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
			dev_err(device, "RP PIO log size %u is invalid\n",
				dpc->rp_log_size);
			dpc->rp_log_size = 0;
		}
	}
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	ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
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	pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);

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	dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
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		cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
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		FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
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		FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
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		FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
	return status;
}

static void dpc_remove(struct pcie_device *dev)
{
	struct dpc_dev *dpc = get_service_data(dev);
	struct pci_dev *pdev = dev->port;
	u16 ctl;

	pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
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	ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
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	pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
}

static struct pcie_port_service_driver dpcdriver = {
	.name		= "dpc",
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	.port_type	= PCIE_ANY_PORT,
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	.service	= PCIE_PORT_SERVICE_DPC,
	.probe		= dpc_probe,
	.remove		= dpc_remove,
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	.reset_link	= dpc_reset_link,
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};

static int __init dpc_service_init(void)
{
	return pcie_port_service_register(&dpcdriver);
}
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device_initcall(dpc_service_init);