nbio_v7_0.c 9.8 KB
Newer Older
C
Chunming Zhou 已提交
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "nbio_v7_0.h"

27 28 29
#include "nbio/nbio_7_0_default.h"
#include "nbio/nbio_7_0_offset.h"
#include "nbio/nbio_7_0_sh_mask.h"
30
#include "vega10_enum.h"
C
Chunming Zhou 已提交
31 32 33

#define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c

34 35
#define smnCPM_CONTROL                                                                                  0x11180460
#define smnPCIE_CNTL2                                                                                   0x11180070
36

37
static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
C
Chunming Zhou 已提交
38
{
39
        u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
C
Chunming Zhou 已提交
40 41 42 43 44 45 46

	tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
	tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;

	return tmp;
}

47
static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
C
Chunming Zhou 已提交
48 49
{
	if (enable)
50
		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
C
Chunming Zhou 已提交
51 52
			BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
	else
53
		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
C
Chunming Zhou 已提交
54 55
}

56
static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
C
Chunming Zhou 已提交
57
{
58
	WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
C
Chunming Zhou 已提交
59 60
}

61
static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
C
Chunming Zhou 已提交
62
{
63
	return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
C
Chunming Zhou 已提交
64 65
}

66 67
static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
					  bool use_doorbell, int doorbell_index)
C
Chunming Zhou 已提交
68
{
69 70 71 72
	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

	u32 doorbell_range = RREG32(reg);
C
Chunming Zhou 已提交
73 74 75 76 77 78 79

	if (use_doorbell) {
		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
	} else
		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

80
	WREG32(reg, doorbell_range);
C
Chunming Zhou 已提交
81 82
}

83 84
static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
					       bool enable)
C
Chunming Zhou 已提交
85
{
86
	WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
C
Chunming Zhou 已提交
87 88
}

89 90 91 92 93 94 95 96
static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
							bool enable)
{

}

static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
					bool use_doorbell, int doorbell_index)
C
Chunming Zhou 已提交
97
{
98
	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
C
Chunming Zhou 已提交
99 100 101 102 103 104 105

	if (use_doorbell) {
		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
	} else
		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

106
	WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
C
Chunming Zhou 已提交
107 108 109 110 111 112
}

static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
{
	uint32_t data;

113 114
	WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
	data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
C
Chunming Zhou 已提交
115 116 117 118 119 120 121

	return data;
}

static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
				       uint32_t data)
{
122 123
	WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
	WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
C
Chunming Zhou 已提交
124 125
}

126 127
static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
						       bool enable)
C
Chunming Zhou 已提交
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164
{
	uint32_t def, data;

	/* NBIF_MGCG_CTRL_LCLK */
	def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
		data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
	else
		data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;

	if (def != data)
		WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);

	/* SYSHUB_MGCG_CTRL_SOCCLK */
	def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
		data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
	else
		data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;

	if (def != data)
		nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);

	/* SYSHUB_MGCG_CTRL_SHUBCLK */
	def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
		data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
	else
		data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;

	if (def != data)
		nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
}

165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201
static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
						      bool enable)
{
	uint32_t def, data;

	def = data = RREG32_PCIE(smnPCIE_CNTL2);
	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
			 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
			 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
	} else {
		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
			  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
			  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
	}

	if (def != data)
		WREG32_PCIE(smnPCIE_CNTL2, data);
}

static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
					    u32 *flags)
{
	int data;

	/* AMD_CG_SUPPORT_BIF_MGCG */
	data = RREG32_PCIE(smnCPM_CONTROL);
	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
		*flags |= AMD_CG_SUPPORT_BIF_MGCG;

	/* AMD_CG_SUPPORT_BIF_LS */
	data = RREG32_PCIE(smnPCIE_CNTL2);
	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
		*flags |= AMD_CG_SUPPORT_BIF_LS;
}

static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
C
Chunming Zhou 已提交
202 203 204 205
{
	u32 interrupt_cntl;

	/* setup interrupt control */
206 207
	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
C
Chunming Zhou 已提交
208 209 210 211 212 213
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
214
	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
C
Chunming Zhou 已提交
215 216
}

217
static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
218 219 220 221
{
	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
}

222
static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
223 224 225 226
{
	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
}

227
static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
228 229 230 231
{
	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
}

232
static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
233 234 235 236
{
	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
}

237 238 239 240 241 242 243 244 245 246 247 248 249 250 251
const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
	.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
	.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
	.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
	.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
	.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
	.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
	.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
	.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
	.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
	.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
};

252 253 254 255 256 257 258 259 260 261 262
static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
{
	if (is_virtual_machine())	/* passthrough mode exclus sriov mod */
		adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
}

static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
{

}

263
const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
264
	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
265 266 267 268
	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
	.get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
	.get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
269 270 271 272 273 274 275 276 277 278 279 280 281 282
	.get_rev_id = nbio_v7_0_get_rev_id,
	.mc_access_enable = nbio_v7_0_mc_access_enable,
	.hdp_flush = nbio_v7_0_hdp_flush,
	.get_memsize = nbio_v7_0_get_memsize,
	.sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
	.enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
	.enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
	.ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
	.update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
	.update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
	.get_clockgating_state = nbio_v7_0_get_clockgating_state,
	.ih_control = nbio_v7_0_ih_control,
	.init_registers = nbio_v7_0_init_registers,
	.detect_hw_virt = nbio_v7_0_detect_hw_virt,
283
};