amd_powerplay.c 26.0 KB
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/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
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#include <linux/slab.h>
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#include "amd_shared.h"
#include "amd_powerplay.h"
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#include "pp_instance.h"
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#include "power_state.h"
#include "eventmanager.h"
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#include "pp_debug.h"
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#define PP_CHECK(handle)						\
	do {								\
		if ((handle) == NULL || (handle)->pp_valid != PP_VALID)	\
			return -EINVAL;					\
	} while (0)

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#define PP_CHECK_HW(hwmgr)						\
	do {								\
		if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL)	\
			return -EINVAL;					\
	} while (0)

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static int pp_early_init(void *handle)
{
	return 0;
}

static int pp_sw_init(void *handle)
{
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	struct pp_instance *pp_handle;
	struct pp_hwmgr  *hwmgr;
	int ret = 0;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	hwmgr = pp_handle->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->pptable_func == NULL ||
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	    hwmgr->pptable_func->pptable_init == NULL ||
	    hwmgr->hwmgr_func->backend_init == NULL)
		return -EINVAL;

	ret = hwmgr->pptable_func->pptable_init(hwmgr);
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	if (ret)
		goto err;
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	ret = hwmgr->hwmgr_func->backend_init(hwmgr);
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	if (ret)
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		goto err1;
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	pr_info("amdgpu: powerplay initialized\n");

	return 0;
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err1:
	if (hwmgr->pptable_func->pptable_fini)
		hwmgr->pptable_func->pptable_fini(hwmgr);
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err:
	pr_err("amdgpu: powerplay initialization failed\n");
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	return ret;
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}

static int pp_sw_fini(void *handle)
{
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	struct pp_instance *pp_handle;
	struct pp_hwmgr  *hwmgr;
	int ret = 0;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	hwmgr = pp_handle->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->backend_fini != NULL)
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		ret = hwmgr->hwmgr_func->backend_fini(hwmgr);

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	if (hwmgr->pptable_func->pptable_fini)
		hwmgr->pptable_func->pptable_fini(hwmgr);

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	return ret;
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}

static int pp_hw_init(void *handle)
{
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	struct pp_instance *pp_handle;
	struct pp_smumgr *smumgr;
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	struct pp_eventmgr *eventmgr;
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	int ret = 0;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	smumgr = pp_handle->smu_mgr;

	if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
		smumgr->smumgr_funcs->smu_init == NULL ||
		smumgr->smumgr_funcs->start_smu == NULL)
		return -EINVAL;

	ret = smumgr->smumgr_funcs->smu_init(smumgr);
	if (ret) {
		printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
		return ret;
	}

	ret = smumgr->smumgr_funcs->start_smu(smumgr);
	if (ret) {
		printk(KERN_ERR "[ powerplay ] smc start failed\n");
		smumgr->smumgr_funcs->smu_fini(smumgr);
		return ret;
	}
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	hw_init_power_state_table(pp_handle->hwmgr);
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	eventmgr = pp_handle->eventmgr;
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	if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
		return -EINVAL;

	ret = eventmgr->pp_eventmgr_init(eventmgr);
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	return 0;
}

static int pp_hw_fini(void *handle)
{
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	struct pp_instance *pp_handle;
	struct pp_smumgr *smumgr;
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	struct pp_eventmgr *eventmgr;
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	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
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	eventmgr = pp_handle->eventmgr;

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	if (eventmgr != NULL && eventmgr->pp_eventmgr_fini != NULL)
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		eventmgr->pp_eventmgr_fini(eventmgr);

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	smumgr = pp_handle->smu_mgr;

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	if (smumgr != NULL && smumgr->smumgr_funcs != NULL &&
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		smumgr->smumgr_funcs->smu_fini != NULL)
		smumgr->smumgr_funcs->smu_fini(smumgr);

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	return 0;
}

static bool pp_is_idle(void *handle)
{
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	return false;
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}

static int pp_wait_for_idle(void *handle)
{
	return 0;
}

static int pp_sw_reset(void *handle)
{
	return 0;
}


static int pp_set_clockgating_state(void *handle,
				    enum amd_clockgating_state state)
{
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	struct pp_hwmgr  *hwmgr;
	uint32_t msg_id, pp_state;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);
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	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
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		return 0;
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	}
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	if (state == AMD_CG_STATE_UNGATE)
		pp_state = 0;
	else
		pp_state = PP_STATE_CG | PP_STATE_LS;

	/* Enable/disable GFX blocks clock gating through SMU */
	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
			PP_BLOCK_GFX_CG,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
			PP_BLOCK_GFX_3D,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
			PP_BLOCK_GFX_RLC,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
			PP_BLOCK_GFX_CP,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
			PP_BLOCK_GFX_MG,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	/* Enable/disable System blocks clock gating through SMU */
	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
			PP_BLOCK_SYS_BIF,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
			PP_BLOCK_SYS_BIF,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
			PP_BLOCK_SYS_MC,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
			PP_BLOCK_SYS_ROM,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
			PP_BLOCK_SYS_DRM,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
			PP_BLOCK_SYS_HDP,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
			PP_BLOCK_SYS_SDMA,
			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
			pp_state);
	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

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	return 0;
}

static int pp_set_powergating_state(void *handle,
				    enum amd_powergating_state state)
{
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	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	/* Enable/disable GFX per cu powergating through SMU */
	return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
			state == AMD_PG_STATE_GATE ? true : false);
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}

static int pp_suspend(void *handle)
{
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	struct pp_instance *pp_handle;
	struct pp_eventmgr *eventmgr;
	struct pem_event_data event_data = { {0} };

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
	eventmgr = pp_handle->eventmgr;
	pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
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	return 0;
}

static int pp_resume(void *handle)
{
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	struct pp_instance *pp_handle;
	struct pp_eventmgr *eventmgr;
	struct pem_event_data event_data = { {0} };
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	struct pp_smumgr *smumgr;
	int ret;
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	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;
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	smumgr = pp_handle->smu_mgr;

	if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
		smumgr->smumgr_funcs->start_smu == NULL)
		return -EINVAL;

	ret = smumgr->smumgr_funcs->start_smu(smumgr);
	if (ret) {
		printk(KERN_ERR "[ powerplay ] smc start failed\n");
		smumgr->smumgr_funcs->smu_fini(smumgr);
		return ret;
	}

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	eventmgr = pp_handle->eventmgr;
	pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
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	return 0;
}

const struct amd_ip_funcs pp_ip_funcs = {
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	.name = "powerplay",
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	.early_init = pp_early_init,
	.late_init = NULL,
	.sw_init = pp_sw_init,
	.sw_fini = pp_sw_fini,
	.hw_init = pp_hw_init,
	.hw_fini = pp_hw_fini,
	.suspend = pp_suspend,
	.resume = pp_resume,
	.is_idle = pp_is_idle,
	.wait_for_idle = pp_wait_for_idle,
	.soft_reset = pp_sw_reset,
	.set_clockgating_state = pp_set_clockgating_state,
	.set_powergating_state = pp_set_powergating_state,
};

static int pp_dpm_load_fw(void *handle)
{
	return 0;
}

static int pp_dpm_fw_loading_complete(void *handle)
{
	return 0;
}

static int pp_dpm_force_performance_level(void *handle,
					enum amd_dpm_forced_level level)
{
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	struct pp_instance *pp_handle;
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	pp_handle = (struct pp_instance *)handle;

	hwmgr = pp_handle->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);

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	return 0;
}
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static enum amd_dpm_forced_level pp_dpm_get_performance_level(
								void *handle)
{
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	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL)
		return -EINVAL;

	return (((struct pp_instance *)handle)->hwmgr->dpm_level);
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}
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static int pp_dpm_get_sclk(void *handle, bool low)
{
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	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->get_sclk == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
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}
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static int pp_dpm_get_mclk(void *handle, bool low)
{
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	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->get_mclk == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
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}
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static int pp_dpm_powergate_vce(void *handle, bool gate)
{
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	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
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}
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static int pp_dpm_powergate_uvd(void *handle, bool gate)
{
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	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
}

static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
{
	switch (state) {
	case POWER_STATE_TYPE_BATTERY:
		return PP_StateUILabel_Battery;
	case POWER_STATE_TYPE_BALANCED:
		return PP_StateUILabel_Balanced;
	case POWER_STATE_TYPE_PERFORMANCE:
		return PP_StateUILabel_Performance;
	default:
		return PP_StateUILabel_None;
	}
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}

int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
{
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	int ret = 0;
	struct pp_instance *pp_handle;
	struct pem_event_data data = { {0} };

	pp_handle = (struct pp_instance *)handle;

	if (pp_handle == NULL)
		return -EINVAL;

	switch (event_id) {
	case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
		break;
	case AMD_PP_EVENT_ENABLE_USER_STATE:
	{
		enum amd_pm_state_type  ps;

		if (input == NULL)
			return -EINVAL;
		ps = *(unsigned long *)input;

		data.requested_ui_label = power_state_convert(ps);
		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
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		break;
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	}
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	case AMD_PP_EVENT_COMPLETE_INIT:
		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
		break;
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	case AMD_PP_EVENT_READJUST_POWER_STATE:
		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
		break;
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	default:
		break;
	}
	return ret;
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}
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enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
{
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	struct pp_hwmgr *hwmgr;
	struct pp_power_state *state;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->current_ps == NULL)
		return -EINVAL;

	state = hwmgr->current_ps;

	switch (state->classification.ui_label) {
	case PP_StateUILabel_Battery:
		return POWER_STATE_TYPE_BATTERY;
	case PP_StateUILabel_Balanced:
		return POWER_STATE_TYPE_BALANCED;
	case PP_StateUILabel_Performance:
		return POWER_STATE_TYPE_PERFORMANCE;
	default:
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		if (state->classification.flags & PP_StateClassificationFlag_Boot)
			return  POWER_STATE_TYPE_INTERNAL_BOOT;
		else
			return POWER_STATE_TYPE_DEFAULT;
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	}
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}
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static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
}

static int pp_dpm_get_fan_control_mode(void *handle)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
}

static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
}

static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
}

static int pp_dpm_get_temperature(void *handle)
{
	struct pp_hwmgr  *hwmgr;

	if (handle == NULL)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

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	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->get_temperature == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
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	return hwmgr->hwmgr_func->get_temperature(hwmgr);
}
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static int pp_dpm_get_pp_num_states(void *handle,
		struct pp_states_info *data)
{
	struct pp_hwmgr *hwmgr;
	int i;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (hwmgr == NULL || hwmgr->ps == NULL)
		return -EINVAL;

	data->nums = hwmgr->num_ps;

	for (i = 0; i < hwmgr->num_ps; i++) {
		struct pp_power_state *state = (struct pp_power_state *)
				((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
		switch (state->classification.ui_label) {
		case PP_StateUILabel_Battery:
			data->states[i] = POWER_STATE_TYPE_BATTERY;
			break;
		case PP_StateUILabel_Balanced:
			data->states[i] = POWER_STATE_TYPE_BALANCED;
			break;
		case PP_StateUILabel_Performance:
			data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
			break;
		default:
			if (state->classification.flags & PP_StateClassificationFlag_Boot)
				data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
			else
				data->states[i] = POWER_STATE_TYPE_DEFAULT;
		}
	}

	return 0;
}

static int pp_dpm_get_pp_table(void *handle, char **table)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

723 724
	PP_CHECK_HW(hwmgr);

725 726 727 728
	if (!hwmgr->soft_pp_table)
		return -EINVAL;

	*table = (char *)hwmgr->soft_pp_table;
729

730
	return hwmgr->soft_pp_table_size;
731 732 733 734 735 736 737 738 739 740 741
}

static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

742 743
	PP_CHECK_HW(hwmgr);

744
	if (!hwmgr->hardcode_pp_table) {
745 746 747
		hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
						   hwmgr->soft_pp_table_size,
						   GFP_KERNEL);
748 749 750

		if (!hwmgr->hardcode_pp_table)
			return -ENOMEM;
751
	}
752

753 754 755 756 757
	memcpy(hwmgr->hardcode_pp_table, buf, size);

	hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;

	return amd_powerplay_reset(handle);
758 759 760
}

static int pp_dpm_force_clock_level(void *handle,
761
		enum pp_clock_type type, uint32_t mask)
762 763 764 765 766 767 768 769
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

770 771 772 773 774 775
	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->force_clock_level == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
776

777
	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
778 779 780 781 782 783 784 785 786 787 788 789
}

static int pp_dpm_print_clock_levels(void *handle,
		enum pp_clock_type type, char *buf)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

790
	PP_CHECK_HW(hwmgr);
791

792 793 794 795
	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}
796 797 798
	return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
}

799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836
static int pp_dpm_get_sclk_od(void *handle)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}

	return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
}

static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}

	return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
}

837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874
static int pp_dpm_get_mclk_od(void *handle)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}

	return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
}

static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}

	return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
}

875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893
static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
{
	struct pp_hwmgr *hwmgr;

	if (!handle)
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	PP_CHECK_HW(hwmgr);

	if (hwmgr->hwmgr_func->read_sensor == NULL) {
		printk(KERN_INFO "%s was not implemented.\n", __func__);
		return 0;
	}

	return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value);
}

894
const struct amd_powerplay_funcs pp_dpm_funcs = {
895
	.get_temperature = pp_dpm_get_temperature,
896 897 898 899 900 901 902 903 904 905
	.load_firmware = pp_dpm_load_fw,
	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
	.force_performance_level = pp_dpm_force_performance_level,
	.get_performance_level = pp_dpm_get_performance_level,
	.get_current_power_state = pp_dpm_get_current_power_state,
	.get_sclk = pp_dpm_get_sclk,
	.get_mclk = pp_dpm_get_mclk,
	.powergate_vce = pp_dpm_powergate_vce,
	.powergate_uvd = pp_dpm_powergate_uvd,
	.dispatch_tasks = pp_dpm_dispatch_tasks,
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	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
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	.get_pp_num_states = pp_dpm_get_pp_num_states,
	.get_pp_table = pp_dpm_get_pp_table,
	.set_pp_table = pp_dpm_set_pp_table,
	.force_clock_level = pp_dpm_force_clock_level,
	.print_clock_levels = pp_dpm_print_clock_levels,
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	.get_sclk_od = pp_dpm_get_sclk_od,
	.set_sclk_od = pp_dpm_set_sclk_od,
917 918
	.get_mclk_od = pp_dpm_get_mclk_od,
	.set_mclk_od = pp_dpm_set_mclk_od,
919
	.read_sensor = pp_dpm_read_sensor,
920 921
};

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static int amd_pp_instance_init(struct amd_pp_init *pp_init,
				struct amd_powerplay *amd_pp)
{
	int ret;
	struct pp_instance *handle;

	handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
	if (handle == NULL)
		return -ENOMEM;

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	handle->pp_valid = PP_VALID;

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	ret = smum_init(pp_init, handle);
	if (ret)
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		goto fail_smum;

	ret = hwmgr_init(pp_init, handle);
	if (ret)
		goto fail_hwmgr;
941

942 943 944 945
	ret = eventmgr_init(handle);
	if (ret)
		goto fail_eventmgr;

946 947
	amd_pp->pp_handle = handle;
	return 0;
948

949 950
fail_eventmgr:
	hwmgr_fini(handle->hwmgr);
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fail_hwmgr:
	smum_fini(handle->smu_mgr);
fail_smum:
	kfree(handle);
	return ret;
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}

static int amd_pp_instance_fini(void *handle)
{
	struct pp_instance *instance = (struct pp_instance *)handle;
961

962 963 964
	if (instance == NULL)
		return -EINVAL;

965 966
	eventmgr_fini(instance->eventmgr);

967 968
	hwmgr_fini(instance->hwmgr);

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	smum_fini(instance->smu_mgr);

	kfree(handle);
	return 0;
}

975 976 977
int amd_powerplay_init(struct amd_pp_init *pp_init,
		       struct amd_powerplay *amd_pp)
{
978 979
	int ret;

980 981 982
	if (pp_init == NULL || amd_pp == NULL)
		return -EINVAL;

983 984 985 986 987
	ret = amd_pp_instance_init(pp_init, amd_pp);

	if (ret)
		return ret;

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	amd_pp->ip_funcs = &pp_ip_funcs;
	amd_pp->pp_funcs = &pp_dpm_funcs;

	return 0;
}

int amd_powerplay_fini(void *handle)
{
996 997
	amd_pp_instance_fini(handle);

998 999
	return 0;
}
1000

1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
int amd_powerplay_reset(void *handle)
{
	struct pp_instance *instance = (struct pp_instance *)handle;
	struct pp_eventmgr *eventmgr;
	struct pem_event_data event_data = { {0} };
	int ret;

	if (instance == NULL)
		return -EINVAL;

	eventmgr = instance->eventmgr;
	if (!eventmgr || !eventmgr->pp_eventmgr_fini)
		return -EINVAL;

	eventmgr->pp_eventmgr_fini(eventmgr);

	ret = pp_sw_fini(handle);
	if (ret)
		return ret;

	kfree(instance->hwmgr->ps);

	ret = pp_sw_init(handle);
	if (ret)
		return ret;

	hw_init_power_state_table(instance->hwmgr);

	if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
		return -EINVAL;

	ret = eventmgr->pp_eventmgr_init(eventmgr);
	if (ret)
		return ret;

	return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
}

1039 1040
/* export this function to DAL */

1041 1042
int amd_powerplay_display_configuration_change(void *handle,
	const struct amd_pp_display_configuration *display_config)
1043 1044 1045
{
	struct pp_hwmgr  *hwmgr;

1046
	PP_CHECK((struct pp_instance *)handle);
1047 1048 1049 1050

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	phm_store_dal_configuration_data(hwmgr, display_config);
1051

1052 1053
	return 0;
}
1054

1055
int amd_powerplay_get_display_power_level(void *handle,
R
Rex Zhu 已提交
1056
		struct amd_pp_simple_clock_info *output)
1057 1058 1059
{
	struct pp_hwmgr  *hwmgr;

1060 1061 1062
	PP_CHECK((struct pp_instance *)handle);

	if (output == NULL)
1063 1064 1065 1066
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

1067
	return phm_get_dal_power_level(hwmgr, output);
1068
}
1069 1070

int amd_powerplay_get_current_clocks(void *handle,
1071
		struct amd_pp_clock_info *clocks)
1072 1073 1074 1075 1076
{
	struct pp_hwmgr  *hwmgr;
	struct amd_pp_simple_clock_info simple_clocks;
	struct pp_clock_info hw_clocks;

1077 1078 1079
	PP_CHECK((struct pp_instance *)handle);

	if (clocks == NULL)
1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	phm_get_dal_power_level(hwmgr, &simple_clocks);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
		if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
			PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
	} else {
		if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
			PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
	}

	clocks->min_engine_clock = hw_clocks.min_eng_clk;
	clocks->max_engine_clock = hw_clocks.max_eng_clk;
	clocks->min_memory_clock = hw_clocks.min_mem_clk;
	clocks->max_memory_clock = hw_clocks.max_mem_clk;
	clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
	clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;

	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;

	clocks->max_clocks_state = simple_clocks.level;

	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
		clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
		clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
	}

	return 0;

}

int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
	int result = -1;

	struct pp_hwmgr *hwmgr;

1121 1122 1123
	PP_CHECK((struct pp_instance *)handle);

	if (clocks == NULL)
1124 1125 1126 1127 1128 1129 1130 1131 1132
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	result = phm_get_clock_by_type(hwmgr, type, clocks);

	return result;
}

1133 1134
int amd_powerplay_get_display_mode_validation_clocks(void *handle,
		struct amd_pp_simple_clock_info *clocks)
1135 1136 1137 1138
{
	int result = -1;
	struct pp_hwmgr  *hwmgr;

1139 1140 1141
	PP_CHECK((struct pp_instance *)handle);

	if (clocks == NULL)
1142 1143 1144 1145 1146 1147 1148 1149 1150 1151
		return -EINVAL;

	hwmgr = ((struct pp_instance *)handle)->hwmgr;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
		result = phm_get_max_high_clocks(hwmgr, clocks);

	return result;
}