mpc8560ads.dts

/*
 * MPC8560 ADS Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/ {
	model = "MPC8560ADS";
	compatible = "MPC8560ADS", "MPC85xxADS";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8560@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;	// 32 bytes
			i-cache-line-size = <20>;	// 32 bytes
			d-cache-size = <8000>;		// L1, 32K
			i-cache-size = <8000>;		// L1, 32K
			timebase-frequency = <04ead9a0>;
			bus-frequency = <13ab6680>;
			clock-frequency = <312c8040>;
			32-bit;
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 10000000>;
	};

	soc8560@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		ranges = <0 e0000000 00100000>;
		reg = <e0000000 00000200>;
		bus-frequency = <13ab6680>;

		memory-controller@2000 {
			compatible = "fsl,8540-memory-controller";
			reg = <2000 1000>;
			interrupt-parent = <&mpic>;
			interrupts = <2 2>;
		};

		l2-cache-controller@20000 {
			compatible = "fsl,8540-l2-cache-controller";
			reg = <20000 1000>;
			cache-line-size = <20>;	// 32 bytes
			cache-size = <40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <0 2>;
		};

		mdio@24520 {
			device_type = "mdio";
			compatible = "gianfar";
			reg = <24520 20>;
			#address-cells = <1>;
			#size-cells = <0>;
			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <35 1>;
				reg = <0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <35 1>;
				reg = <1>;
				device_type = "ethernet-phy";
			};
			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
				interrupts = <37 1>;
				reg = <2>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
				interrupts = <37 1>;
				reg = <3>;
				device_type = "ethernet-phy";
			};
		};

		ethernet@24000 {
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <24000 1000>;
			address = [ 00 00 0C 00 00 FD ];
			interrupts = <d 2 e 2 12 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
		};

		ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <25000 1000>;
			address = [ 00 00 0C 00 01 FD ];
			interrupts = <13 2 14 2 18 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
		};

		pci@8000 {
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "85xx";
			device_type = "pci";
			reg = <8000 1000>;
			clock-frequency = <3f940aa>;
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map = <

					/* IDSEL 0x2 */
					 1000 0 0 1 &mpic 31 1
					 1000 0 0 2 &mpic 32 1
					 1000 0 0 3 &mpic 33 1
					 1000 0 0 4 &mpic 34 1

					/* IDSEL 0x3 */
					 1800 0 0 1 &mpic 34 1
					 1800 0 0 2 &mpic 31 1
					 1800 0 0 3 &mpic 32 1
					 1800 0 0 4 &mpic 33 1

					/* IDSEL 0x4 */
					 2000 0 0 1 &mpic 33 1
					 2000 0 0 2 &mpic 34 1
					 2000 0 0 3 &mpic 31 1
					 2000 0 0 4 &mpic 32 1

					/* IDSEL 0x5  */
					 2800 0 0 1 &mpic 32 1
					 2800 0 0 2 &mpic 33 1
					 2800 0 0 3 &mpic 34 1
					 2800 0 0 4 &mpic 31 1

					/* IDSEL 12 */
					 6000 0 0 1 &mpic 31 1
					 6000 0 0 2 &mpic 32 1
					 6000 0 0 3 &mpic 33 1
					 6000 0 0 4 &mpic 34 1

					/* IDSEL 13 */
					 6800 0 0 1 &mpic 34 1
					 6800 0 0 2 &mpic 31 1
					 6800 0 0 3 &mpic 32 1
					 6800 0 0 4 &mpic 33 1

					/* IDSEL 14*/
					 7000 0 0 1 &mpic 33 1
					 7000 0 0 2 &mpic 34 1
					 7000 0 0 3 &mpic 31 1
					 7000 0 0 4 &mpic 32 1

					/* IDSEL 15 */
					 7800 0 0 1 &mpic 32 1
					 7800 0 0 2 &mpic 33 1
					 7800 0 0 3 &mpic 34 1
					 7800 0 0 4 &mpic 31 1

					/* IDSEL 18 */
					 9000 0 0 1 &mpic 31 1
					 9000 0 0 2 &mpic 32 1
					 9000 0 0 3 &mpic 33 1
					 9000 0 0 4 &mpic 34 1

					/* IDSEL 19 */
					 9800 0 0 1 &mpic 34 1
					 9800 0 0 2 &mpic 31 1
					 9800 0 0 3 &mpic 32 1
					 9800 0 0 4 &mpic 33 1

					/* IDSEL 20 */
					 a000 0 0 1 &mpic 33 1
					 a000 0 0 2 &mpic 34 1
					 a000 0 0 3 &mpic 31 1
					 a000 0 0 4 &mpic 32 1

					/* IDSEL 21 */
					 a800 0 0 1 &mpic 32 1
					 a800 0 0 2 &mpic 33 1
					 a800 0 0 3 &mpic 34 1
					 a800 0 0 4 &mpic 31 1>;

			interrupt-parent = <&mpic>;
			interrupts = <8 0>;
			bus-range = <0 0>;
			ranges = <02000000 0 80000000 80000000 0 20000000
				  01000000 0 00000000 e2000000 0 01000000>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <40000 40000>;
			built-in;
			device_type = "open-pic";
		};

		cpm@e0000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			#interrupt-cells = <2>;
			device_type = "cpm";
			model = "CPM2";
			ranges = <0 0 c0000>;
			reg = <80000 40000>;
			command-proc = <919c0>;
			brg-frequency = <9d5b340>;

			cpmpic: pic@90c00 {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				interrupts = <1e 0>;
				interrupt-parent = <&mpic>;
				reg = <90c00 80>;
				built-in;
				device_type = "cpm-pic";
			};

			scc@91a00 {
				device_type = "serial";
				compatible = "cpm_uart";
				model = "SCC";
				device-id = <1>;
				reg = <91a00 20 88000 100>;
				clock-setup = <00ffffff 0>;
				rx-clock = <1>;
				tx-clock = <1>;
				current-speed = <1c200>;
				interrupts = <28 8>;
				interrupt-parent = <&cpmpic>;
			};

			scc@91a20 {
				device_type = "serial";
				compatible = "cpm_uart";
				model = "SCC";
				device-id = <2>;
				reg = <91a20 20 88100 100>;
				clock-setup = <ff00ffff 90000>;
				rx-clock = <2>;
				tx-clock = <2>;
				current-speed = <1c200>;
				interrupts = <29 8>;
				interrupt-parent = <&cpmpic>;
			};

			fcc@91320 {
				device_type = "network";
				compatible = "fs_enet";
				model = "FCC";
				device-id = <2>;
				reg = <91320 20 88500 100 913a0 30>;
				mac-address = [ 00 00 0C 00 02 FD ];
				clock-setup = <ff00ffff 250000>;
				rx-clock = <15>;
				tx-clock = <16>;
				interrupts = <21 8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy2>;
			};

			fcc@91340 {
				device_type = "network";
				compatible = "fs_enet";
				model = "FCC";
				device-id = <3>;
				reg = <91340 20 88600 100 913d0 30>;
				mac-address = [ 00 00 0C 00 03 FD ];
				clock-setup = <ffff00ff 3700>;
				rx-clock = <17>;
				tx-clock = <18>;
				interrupts = <22 8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy3>;
			};
		};
	};
};