ds.c 39.5 KB
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#include <linux/bitops.h>
#include <linux/types.h>
#include <linux/slab.h>
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#include <asm/perf_event.h>
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#include <asm/insn.h>
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#include "../perf_event.h"
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/* The size of a BTS record in bytes: */
#define BTS_RECORD_SIZE		24

#define BTS_BUFFER_SIZE		(PAGE_SIZE << 4)
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#define PEBS_BUFFER_SIZE	(PAGE_SIZE << 4)
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#define PEBS_FIXUP_SIZE		PAGE_SIZE
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/*
 * pebs_record_32 for p4 and core not supported

struct pebs_record_32 {
	u32 flags, ip;
	u32 ax, bc, cx, dx;
	u32 si, di, bp, sp;
};

 */

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union intel_x86_pebs_dse {
	u64 val;
	struct {
		unsigned int ld_dse:4;
		unsigned int ld_stlb_miss:1;
		unsigned int ld_locked:1;
		unsigned int ld_reserved:26;
	};
	struct {
		unsigned int st_l1d_hit:1;
		unsigned int st_reserved1:3;
		unsigned int st_stlb_miss:1;
		unsigned int st_locked:1;
		unsigned int st_reserved2:26;
	};
};


/*
 * Map PEBS Load Latency Data Source encodings to generic
 * memory data source information
 */
#define P(a, b) PERF_MEM_S(a, b)
#define OP_LH (P(OP, LOAD) | P(LVL, HIT))
#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))

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/* Version for Sandy Bridge and later */
static u64 pebs_data_source[] = {
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	P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
	OP_LH | P(LVL, L1)  | P(SNOOP, NONE),	/* 0x01: L1 local */
	OP_LH | P(LVL, LFB) | P(SNOOP, NONE),	/* 0x02: LFB hit */
	OP_LH | P(LVL, L2)  | P(SNOOP, NONE),	/* 0x03: L2 hit */
	OP_LH | P(LVL, L3)  | P(SNOOP, NONE),	/* 0x04: L3 hit */
	OP_LH | P(LVL, L3)  | P(SNOOP, MISS),	/* 0x05: L3 hit, snoop miss */
	OP_LH | P(LVL, L3)  | P(SNOOP, HIT),	/* 0x06: L3 hit, snoop hit */
	OP_LH | P(LVL, L3)  | P(SNOOP, HITM),	/* 0x07: L3 hit, snoop hitm */
	OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
	OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
	OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
	OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
	OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
	OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
	OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
	OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
};

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/* Patch up minor differences in the bits */
void __init intel_pmu_pebs_data_source_nhm(void)
{
	pebs_data_source[0x05] = OP_LH | P(LVL, L3)  | P(SNOOP, HIT);
	pebs_data_source[0x06] = OP_LH | P(LVL, L3)  | P(SNOOP, HITM);
	pebs_data_source[0x07] = OP_LH | P(LVL, L3)  | P(SNOOP, HITM);
}

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static u64 precise_store_data(u64 status)
{
	union intel_x86_pebs_dse dse;
	u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);

	dse.val = status;

	/*
	 * bit 4: TLB access
	 * 1 = stored missed 2nd level TLB
	 *
	 * so it either hit the walker or the OS
	 * otherwise hit 2nd level TLB
	 */
	if (dse.st_stlb_miss)
		val |= P(TLB, MISS);
	else
		val |= P(TLB, HIT);

	/*
	 * bit 0: hit L1 data cache
	 * if not set, then all we know is that
	 * it missed L1D
	 */
	if (dse.st_l1d_hit)
		val |= P(LVL, HIT);
	else
		val |= P(LVL, MISS);

	/*
	 * bit 5: Locked prefix
	 */
	if (dse.st_locked)
		val |= P(LOCK, LOCKED);

	return val;
}

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static u64 precise_datala_hsw(struct perf_event *event, u64 status)
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{
	union perf_mem_data_src dse;

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	dse.val = PERF_MEM_NA;

	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
		dse.mem_op = PERF_MEM_OP_STORE;
	else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
		dse.mem_op = PERF_MEM_OP_LOAD;
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	/*
	 * L1 info only valid for following events:
	 *
	 * MEM_UOPS_RETIRED.STLB_MISS_STORES
	 * MEM_UOPS_RETIRED.LOCK_STORES
	 * MEM_UOPS_RETIRED.SPLIT_STORES
	 * MEM_UOPS_RETIRED.ALL_STORES
	 */
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	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
		if (status & 1)
			dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
		else
			dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
	}
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	return dse.val;
}

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static u64 load_latency_data(u64 status)
{
	union intel_x86_pebs_dse dse;
	u64 val;
	int model = boot_cpu_data.x86_model;
	int fam = boot_cpu_data.x86;

	dse.val = status;

	/*
	 * use the mapping table for bit 0-3
	 */
	val = pebs_data_source[dse.ld_dse];

	/*
	 * Nehalem models do not support TLB, Lock infos
	 */
	if (fam == 0x6 && (model == 26 || model == 30
	    || model == 31 || model == 46)) {
		val |= P(TLB, NA) | P(LOCK, NA);
		return val;
	}
	/*
	 * bit 4: TLB access
	 * 0 = did not miss 2nd level TLB
	 * 1 = missed 2nd level TLB
	 */
	if (dse.ld_stlb_miss)
		val |= P(TLB, MISS) | P(TLB, L2);
	else
		val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);

	/*
	 * bit 5: locked prefix
	 */
	if (dse.ld_locked)
		val |= P(LOCK, LOCKED);

	return val;
}

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struct pebs_record_core {
	u64 flags, ip;
	u64 ax, bx, cx, dx;
	u64 si, di, bp, sp;
	u64 r8,  r9,  r10, r11;
	u64 r12, r13, r14, r15;
};

struct pebs_record_nhm {
	u64 flags, ip;
	u64 ax, bx, cx, dx;
	u64 si, di, bp, sp;
	u64 r8,  r9,  r10, r11;
	u64 r12, r13, r14, r15;
	u64 status, dla, dse, lat;
};

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/*
 * Same as pebs_record_nhm, with two additional fields.
 */
struct pebs_record_hsw {
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	u64 flags, ip;
	u64 ax, bx, cx, dx;
	u64 si, di, bp, sp;
	u64 r8,  r9,  r10, r11;
	u64 r12, r13, r14, r15;
	u64 status, dla, dse, lat;
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	u64 real_ip, tsx_tuning;
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};

union hsw_tsx_tuning {
	struct {
		u32 cycles_last_block     : 32,
		    hle_abort		  : 1,
		    rtm_abort		  : 1,
		    instruction_abort     : 1,
		    non_instruction_abort : 1,
		    retry		  : 1,
		    data_conflict	  : 1,
		    capacity_writes	  : 1,
		    capacity_reads	  : 1;
	};
	u64	    value;
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};

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#define PEBS_HSW_TSX_FLAGS	0xff00000000ULL

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/* Same as HSW, plus TSC */

struct pebs_record_skl {
	u64 flags, ip;
	u64 ax, bx, cx, dx;
	u64 si, di, bp, sp;
	u64 r8,  r9,  r10, r11;
	u64 r12, r13, r14, r15;
	u64 status, dla, dse, lat;
	u64 real_ip, tsx_tuning;
	u64 tsc;
};

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void init_debug_store_on_cpu(int cpu)
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{
	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;

	if (!ds)
		return;

	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
		     (u32)((u64)(unsigned long)ds),
		     (u32)((u64)(unsigned long)ds >> 32));
}

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void fini_debug_store_on_cpu(int cpu)
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{
	if (!per_cpu(cpu_hw_events, cpu).ds)
		return;

	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
}

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static DEFINE_PER_CPU(void *, insn_buffer);

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static int alloc_pebs_buffer(int cpu)
{
	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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	int node = cpu_to_node(cpu);
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	int max;
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	void *buffer, *ibuffer;
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	if (!x86_pmu.pebs)
		return 0;

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	buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
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	if (unlikely(!buffer))
		return -ENOMEM;

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	/*
	 * HSW+ already provides us the eventing ip; no need to allocate this
	 * buffer then.
	 */
	if (x86_pmu.intel_cap.pebs_format < 2) {
		ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
		if (!ibuffer) {
			kfree(buffer);
			return -ENOMEM;
		}
		per_cpu(insn_buffer, cpu) = ibuffer;
	}

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	max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
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	ds->pebs_buffer_base = (u64)(unsigned long)buffer;
	ds->pebs_index = ds->pebs_buffer_base;
	ds->pebs_absolute_maximum = ds->pebs_buffer_base +
		max * x86_pmu.pebs_record_size;

	return 0;
}

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static void release_pebs_buffer(int cpu)
{
	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;

	if (!ds || !x86_pmu.pebs)
		return;

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	kfree(per_cpu(insn_buffer, cpu));
	per_cpu(insn_buffer, cpu) = NULL;

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	kfree((void *)(unsigned long)ds->pebs_buffer_base);
	ds->pebs_buffer_base = 0;
}

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static int alloc_bts_buffer(int cpu)
{
	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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	int node = cpu_to_node(cpu);
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	int max, thresh;
	void *buffer;

	if (!x86_pmu.bts)
		return 0;

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	buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
	if (unlikely(!buffer)) {
		WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
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		return -ENOMEM;
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	}
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	max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
	thresh = max / 16;

	ds->bts_buffer_base = (u64)(unsigned long)buffer;
	ds->bts_index = ds->bts_buffer_base;
	ds->bts_absolute_maximum = ds->bts_buffer_base +
		max * BTS_RECORD_SIZE;
	ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
		thresh * BTS_RECORD_SIZE;

	return 0;
}

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static void release_bts_buffer(int cpu)
{
	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;

	if (!ds || !x86_pmu.bts)
		return;

	kfree((void *)(unsigned long)ds->bts_buffer_base);
	ds->bts_buffer_base = 0;
}

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static int alloc_ds_buffer(int cpu)
{
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	int node = cpu_to_node(cpu);
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	struct debug_store *ds;

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	ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
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	if (unlikely(!ds))
		return -ENOMEM;

	per_cpu(cpu_hw_events, cpu).ds = ds;

	return 0;
}

static void release_ds_buffer(int cpu)
{
	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;

	if (!ds)
		return;

	per_cpu(cpu_hw_events, cpu).ds = NULL;
	kfree(ds);
}

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void release_ds_buffers(void)
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{
	int cpu;

	if (!x86_pmu.bts && !x86_pmu.pebs)
		return;

	get_online_cpus();
	for_each_online_cpu(cpu)
		fini_debug_store_on_cpu(cpu);

	for_each_possible_cpu(cpu) {
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		release_pebs_buffer(cpu);
		release_bts_buffer(cpu);
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		release_ds_buffer(cpu);
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	}
	put_online_cpus();
}

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void reserve_ds_buffers(void)
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{
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	int bts_err = 0, pebs_err = 0;
	int cpu;

	x86_pmu.bts_active = 0;
	x86_pmu.pebs_active = 0;
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	if (!x86_pmu.bts && !x86_pmu.pebs)
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		return;
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	if (!x86_pmu.bts)
		bts_err = 1;

	if (!x86_pmu.pebs)
		pebs_err = 1;

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	get_online_cpus();

	for_each_possible_cpu(cpu) {
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		if (alloc_ds_buffer(cpu)) {
			bts_err = 1;
			pebs_err = 1;
		}
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		if (!bts_err && alloc_bts_buffer(cpu))
			bts_err = 1;

		if (!pebs_err && alloc_pebs_buffer(cpu))
			pebs_err = 1;
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		if (bts_err && pebs_err)
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			break;
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	}

	if (bts_err) {
		for_each_possible_cpu(cpu)
			release_bts_buffer(cpu);
	}
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	if (pebs_err) {
		for_each_possible_cpu(cpu)
			release_pebs_buffer(cpu);
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	}

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	if (bts_err && pebs_err) {
		for_each_possible_cpu(cpu)
			release_ds_buffer(cpu);
	} else {
		if (x86_pmu.bts && !bts_err)
			x86_pmu.bts_active = 1;

		if (x86_pmu.pebs && !pebs_err)
			x86_pmu.pebs_active = 1;

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		for_each_online_cpu(cpu)
			init_debug_store_on_cpu(cpu);
	}

	put_online_cpus();
}

/*
 * BTS
 */

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struct event_constraint bts_constraint =
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	EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
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void intel_pmu_enable_bts(u64 config)
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{
	unsigned long debugctlmsr;

	debugctlmsr = get_debugctlmsr();

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	debugctlmsr |= DEBUGCTLMSR_TR;
	debugctlmsr |= DEBUGCTLMSR_BTS;
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	if (config & ARCH_PERFMON_EVENTSEL_INT)
		debugctlmsr |= DEBUGCTLMSR_BTINT;
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	if (!(config & ARCH_PERFMON_EVENTSEL_OS))
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		debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
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	if (!(config & ARCH_PERFMON_EVENTSEL_USR))
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		debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
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	update_debugctlmsr(debugctlmsr);
}

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void intel_pmu_disable_bts(void)
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{
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	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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	unsigned long debugctlmsr;

	if (!cpuc->ds)
		return;

	debugctlmsr = get_debugctlmsr();

	debugctlmsr &=
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		~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
		  DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
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	update_debugctlmsr(debugctlmsr);
}

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int intel_pmu_drain_bts_buffer(void)
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{
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	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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	struct debug_store *ds = cpuc->ds;
	struct bts_record {
		u64	from;
		u64	to;
		u64	flags;
	};
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	struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
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	struct bts_record *at, *base, *top;
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	struct perf_output_handle handle;
	struct perf_event_header header;
	struct perf_sample_data data;
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	unsigned long skip = 0;
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	struct pt_regs regs;

	if (!event)
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		return 0;
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	if (!x86_pmu.bts_active)
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		return 0;
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	base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
	top  = (struct bts_record *)(unsigned long)ds->bts_index;
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	if (top <= base)
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		return 0;
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	memset(&regs, 0, sizeof(regs));

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	ds->bts_index = ds->bts_buffer_base;

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	perf_sample_data_init(&data, 0, event->hw.last_period);
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	/*
	 * BTS leaks kernel addresses in branches across the cpl boundary,
	 * such as traps or system calls, so unless the user is asking for
	 * kernel tracing (and right now it's not possible), we'd need to
	 * filter them out. But first we need to count how many of those we
	 * have in the current batch. This is an extra O(n) pass, however,
	 * it's much faster than the other one especially considering that
	 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
	 * alloc_bts_buffer()).
	 */
	for (at = base; at < top; at++) {
		/*
		 * Note that right now *this* BTS code only works if
		 * attr::exclude_kernel is set, but let's keep this extra
		 * check here in case that changes.
		 */
		if (event->attr.exclude_kernel &&
		    (kernel_ip(at->from) || kernel_ip(at->to)))
			skip++;
	}

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	/*
	 * Prepare a generic sample, i.e. fill in the invariant fields.
	 * We will overwrite the from and to address before we output
	 * the sample.
	 */
P
Peter Zijlstra 已提交
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	rcu_read_lock();
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	perf_prepare_sample(&header, &data, event, &regs);

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	if (perf_output_begin(&handle, event, header.size *
			      (top - base - skip)))
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		goto unlock;
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	for (at = base; at < top; at++) {
		/* Filter out any records that contain kernel addresses. */
		if (event->attr.exclude_kernel &&
		    (kernel_ip(at->from) || kernel_ip(at->to)))
			continue;

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		data.ip		= at->from;
		data.addr	= at->to;

		perf_output_sample(&handle, &header, &data, event);
	}

	perf_output_end(&handle);

	/* There's new data available. */
	event->hw.interrupts++;
	event->pending_kill = POLL_IN;
P
Peter Zijlstra 已提交
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unlock:
	rcu_read_unlock();
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	return 1;
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}

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static inline void intel_pmu_drain_pebs_buffer(void)
{
	struct pt_regs regs;

	x86_pmu.drain_pebs(&regs);
}

void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
{
	if (!sched_in)
		intel_pmu_drain_pebs_buffer();
}

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/*
 * PEBS
 */
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struct event_constraint intel_core2_pebs_event_constraints[] = {
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	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
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	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
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	EVENT_CONSTRAINT_END
};

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struct event_constraint intel_atom_pebs_event_constraints[] = {
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	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
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	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
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	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
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	EVENT_CONSTRAINT_END
};

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struct event_constraint intel_slm_pebs_event_constraints[] = {
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	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
643 644
	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
645 646 647
	EVENT_CONSTRAINT_END
};

648 649 650 651 652 653
struct event_constraint intel_glm_pebs_event_constraints[] = {
	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
	EVENT_CONSTRAINT_END
};

654
struct event_constraint intel_nehalem_pebs_event_constraints[] = {
655
	INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
656 657 658
	INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
659
	INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
660 661 662 663 664 665
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
666 667
	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
668 669 670
	EVENT_CONSTRAINT_END
};

671
struct event_constraint intel_westmere_pebs_event_constraints[] = {
672
	INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
673 674 675
	INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
676
	INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
677 678 679 680 681 682
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
683 684
	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
685 686 687
	EVENT_CONSTRAINT_END
};

688
struct event_constraint intel_snb_pebs_event_constraints[] = {
689
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
690
	INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
691
	INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
692 693
	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
694 695 696 697
        INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
        INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
        INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
        INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
698 699
	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
700 701 702
	EVENT_CONSTRAINT_END
};

703
struct event_constraint intel_ivb_pebs_event_constraints[] = {
704
        INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
705
        INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
706
	INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
707 708
	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
709 710
	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
711 712 713 714
	INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
	INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
	INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
	INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
715 716
	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
717 718 719
        EVENT_CONSTRAINT_END
};

720
struct event_constraint intel_hsw_pebs_event_constraints[] = {
721
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
722 723 724
	INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
725 726
	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
727
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
728 729 730 731 732 733 734 735 736 737
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
738 739 740 741 742
	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
	EVENT_CONSTRAINT_END
};

743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
struct event_constraint intel_bdw_pebs_event_constraints[] = {
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
	INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
	EVENT_CONSTRAINT_END
};


767 768
struct event_constraint intel_skl_pebs_event_constraints[] = {
	INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),	/* INST_RETIRED.PREC_DIST */
769 770
	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
771 772
	/* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
	INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
773 774 775 776 777 778 779 780 781 782 783 784
	INTEL_PLD_CONSTRAINT(0x1cd, 0xf),		      /* MEM_TRANS_RETIRED.* */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
785 786
	/* Allow all events as PEBS with no flags */
	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
787 788 789
	EVENT_CONSTRAINT_END
};

790
struct event_constraint *intel_pebs_constraints(struct perf_event *event)
791 792 793
{
	struct event_constraint *c;

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Peter Zijlstra 已提交
794
	if (!event->attr.precise_ip)
795 796 797 798
		return NULL;

	if (x86_pmu.pebs_constraints) {
		for_each_event_constraint(c, x86_pmu.pebs_constraints) {
799 800
			if ((event->hw.config & c->cmask) == c->code) {
				event->hw.flags |= c->flags;
801
				return c;
802
			}
803 804 805 806 807 808
		}
	}

	return &emptyconstraint;
}

809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836
/*
 * We need the sched_task callback even for per-cpu events when we use
 * the large interrupt threshold, such that we can provide PID and TID
 * to PEBS samples.
 */
static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
{
	return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
}

static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
{
	struct debug_store *ds = cpuc->ds;
	u64 threshold;

	if (cpuc->n_pebs == cpuc->n_large_pebs) {
		threshold = ds->pebs_absolute_maximum -
			x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
	} else {
		threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
	}

	ds->pebs_interrupt_threshold = threshold;
}

static void
pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu)
{
837 838 839 840 841 842 843
	/*
	 * Make sure we get updated with the first PEBS
	 * event. It will trigger also during removal, but
	 * that does not hurt:
	 */
	bool update = cpuc->n_pebs == 1;

844 845 846 847 848 849
	if (needed_cb != pebs_needs_sched_cb(cpuc)) {
		if (!needed_cb)
			perf_sched_cb_inc(pmu);
		else
			perf_sched_cb_dec(pmu);

850
		update = true;
851
	}
852 853 854

	if (update)
		pebs_update_threshold(cpuc);
855 856
}

857
void intel_pmu_pebs_add(struct perf_event *event)
858
{
859 860 861 862 863 864 865 866 867
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;
	bool needed_cb = pebs_needs_sched_cb(cpuc);

	cpuc->n_pebs++;
	if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
		cpuc->n_large_pebs++;

	pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
868 869
}

870
void intel_pmu_pebs_enable(struct perf_event *event)
871
{
872
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
873
	struct hw_perf_event *hwc = &event->hw;
874
	struct debug_store *ds = cpuc->ds;
875

876 877
	hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;

878
	cpuc->pebs_enabled |= 1ULL << hwc->idx;
879 880 881

	if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
		cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
882 883
	else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
		cpuc->pebs_enabled |= 1ULL << 63;
884

885
	/*
886 887
	 * Use auto-reload if possible to save a MSR write in the PMI.
	 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
888
	 */
889 890 891 892
	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
		ds->pebs_event_reset[hwc->idx] =
			(u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
	}
893 894
}

895
void intel_pmu_pebs_del(struct perf_event *event)
896 897 898 899 900 901 902 903
{
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;
	bool needed_cb = pebs_needs_sched_cb(cpuc);

	cpuc->n_pebs--;
	if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
		cpuc->n_large_pebs--;
904

905
	pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
906 907
}

908
void intel_pmu_pebs_disable(struct perf_event *event)
909
{
910
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
911
	struct hw_perf_event *hwc = &event->hw;
912

913
	if (cpuc->n_pebs == cpuc->n_large_pebs)
914
		intel_pmu_drain_pebs_buffer();
915

916
	cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
917

918
	if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
919
		cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
920
	else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
921 922
		cpuc->pebs_enabled &= ~(1ULL << 63);

923
	if (cpuc->enabled)
924
		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
925 926 927 928

	hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
}

929
void intel_pmu_pebs_enable_all(void)
930
{
931
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
932 933 934 935 936

	if (cpuc->pebs_enabled)
		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
}

937
void intel_pmu_pebs_disable_all(void)
938
{
939
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
940 941 942 943 944

	if (cpuc->pebs_enabled)
		wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
}

945 946
static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
{
947
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
948 949 950
	unsigned long from = cpuc->lbr_entries[0].from;
	unsigned long old_to, to = cpuc->lbr_entries[0].to;
	unsigned long ip = regs->ip;
951
	int is_64bit = 0;
952
	void *kaddr;
953
	int size;
954

955 956 957 958 959 960
	/*
	 * We don't need to fixup if the PEBS assist is fault like
	 */
	if (!x86_pmu.intel_cap.pebs_trap)
		return 1;

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Peter Zijlstra 已提交
961 962 963
	/*
	 * No LBR entry, no basic block, no rewinding
	 */
964 965 966
	if (!cpuc->lbr_stack.nr || !from || !to)
		return 0;

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Peter Zijlstra 已提交
967 968 969 970 971 972 973 974 975 976
	/*
	 * Basic blocks should never cross user/kernel boundaries
	 */
	if (kernel_ip(ip) != kernel_ip(to))
		return 0;

	/*
	 * unsigned math, either ip is before the start (impossible) or
	 * the basic block is larger than 1 page (sanity)
	 */
977
	if ((ip - to) > PEBS_FIXUP_SIZE)
978 979 980 981 982 983
		return 0;

	/*
	 * We sampled a branch insn, rewind using the LBR stack
	 */
	if (ip == to) {
984
		set_linear_ip(regs, from);
985 986 987
		return 1;
	}

988
	size = ip - to;
989
	if (!kernel_ip(ip)) {
990
		int bytes;
991 992
		u8 *buf = this_cpu_read(insn_buffer);

993
		/* 'size' must fit our buffer, see above */
994
		bytes = copy_from_user_nmi(buf, (void __user *)to, size);
995
		if (bytes != 0)
996 997 998 999 1000 1001 1002
			return 0;

		kaddr = buf;
	} else {
		kaddr = (void *)to;
	}

1003 1004 1005 1006 1007
	do {
		struct insn insn;

		old_to = to;

1008 1009 1010
#ifdef CONFIG_X86_64
		is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
#endif
1011
		insn_init(&insn, kaddr, size, is_64bit);
1012
		insn_get_length(&insn);
1013 1014 1015 1016 1017 1018 1019 1020
		/*
		 * Make sure there was not a problem decoding the
		 * instruction and getting the length.  This is
		 * doubly important because we have an infinite
		 * loop if insn.length=0.
		 */
		if (!insn.length)
			break;
1021

1022
		to += insn.length;
1023
		kaddr += insn.length;
1024
		size -= insn.length;
1025 1026 1027
	} while (to < ip);

	if (to == ip) {
1028
		set_linear_ip(regs, old_to);
1029 1030 1031
		return 1;
	}

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Peter Zijlstra 已提交
1032 1033 1034 1035
	/*
	 * Even though we decoded the basic block, the instruction stream
	 * never matched the given IP, either the TO or the IP got corrupted.
	 */
1036 1037 1038
	return 0;
}

1039
static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
1040 1041 1042 1043 1044 1045 1046 1047
{
	if (pebs->tsx_tuning) {
		union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
		return tsx.cycles_last_block;
	}
	return 0;
}

1048
static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1049 1050 1051 1052 1053 1054 1055 1056 1057
{
	u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;

	/* For RTM XABORTs also log the abort code from AX */
	if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
		txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
	return txn;
}

1058 1059 1060 1061
static void setup_pebs_sample_data(struct perf_event *event,
				   struct pt_regs *iregs, void *__pebs,
				   struct perf_sample_data *data,
				   struct pt_regs *regs)
1062
{
1063 1064 1065 1066
#define PERF_X86_EVENT_PEBS_HSW_PREC \
		(PERF_X86_EVENT_PEBS_ST_HSW | \
		 PERF_X86_EVENT_PEBS_LD_HSW | \
		 PERF_X86_EVENT_PEBS_NA_HSW)
1067
	/*
1068 1069
	 * We cast to the biggest pebs_record but are careful not to
	 * unconditionally access the 'extra' entries.
1070
	 */
1071
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1072
	struct pebs_record_skl *pebs = __pebs;
1073
	u64 sample_type;
1074 1075
	int fll, fst, dsrc;
	int fl = event->hw.flags;
1076

1077 1078 1079
	if (pebs == NULL)
		return;

1080 1081 1082 1083 1084
	sample_type = event->attr.sample_type;
	dsrc = sample_type & PERF_SAMPLE_DATA_SRC;

	fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
	fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1085

1086
	perf_sample_data_init(data, 0, event->hw.last_period);
1087

1088
	data->period = event->hw.last_period;
1089 1090

	/*
1091
	 * Use latency for weight (only avail with PEBS-LL)
1092
	 */
1093
	if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1094
		data->weight = pebs->lat;
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106

	/*
	 * data.data_src encodes the data source
	 */
	if (dsrc) {
		u64 val = PERF_MEM_NA;
		if (fll)
			val = load_latency_data(pebs->dse);
		else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
			val = precise_datala_hsw(event, pebs->dse);
		else if (fst)
			val = precise_store_data(pebs->dse);
1107
		data->data_src.val = val;
1108 1109
	}

1110
	/*
1111 1112 1113
	 * We use the interrupt regs as a base because the PEBS record does not
	 * contain a full regs set, specifically it seems to lack segment
	 * descriptors, which get used by things like user_mode().
1114
	 *
1115 1116 1117 1118 1119 1120
	 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
	 *
	 * We must however always use BP,SP from iregs for the unwinder to stay
	 * sane; the record BP,SP can point into thin air when the record is
	 * from a previous PMI context or an (I)RET happend between the record
	 * and PMI.
1121
	 */
1122 1123 1124
	*regs = *iregs;
	regs->flags = pebs->flags;
	set_linear_ip(regs, pebs->ip);
1125

1126
	if (sample_type & PERF_SAMPLE_REGS_INTR) {
1127 1128 1129 1130 1131 1132 1133
		regs->ax = pebs->ax;
		regs->bx = pebs->bx;
		regs->cx = pebs->cx;
		regs->dx = pebs->dx;
		regs->si = pebs->si;
		regs->di = pebs->di;

1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
		/*
		 * Per the above; only set BP,SP if we don't need callchains.
		 *
		 * XXX: does this make sense?
		 */
		if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) {
			regs->bp = pebs->bp;
			regs->sp = pebs->sp;
		}

		/*
		 * Preserve PERF_EFLAGS_VM from set_linear_ip().
		 */
		regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM);
1148
#ifndef CONFIG_X86_32
1149 1150 1151 1152 1153 1154 1155 1156
		regs->r8 = pebs->r8;
		regs->r9 = pebs->r9;
		regs->r10 = pebs->r10;
		regs->r11 = pebs->r11;
		regs->r12 = pebs->r12;
		regs->r13 = pebs->r13;
		regs->r14 = pebs->r14;
		regs->r15 = pebs->r15;
1157 1158 1159
#endif
	}

1160
	if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1161 1162 1163 1164
		regs->ip = pebs->real_ip;
		regs->flags |= PERF_EFLAGS_EXACT;
	} else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
		regs->flags |= PERF_EFLAGS_EXACT;
1165
	else
1166
		regs->flags &= ~PERF_EFLAGS_EXACT;
1167

1168
	if ((sample_type & PERF_SAMPLE_ADDR) &&
1169
	    x86_pmu.intel_cap.pebs_format >= 1)
1170
		data->addr = pebs->dla;
1171

1172 1173
	if (x86_pmu.intel_cap.pebs_format >= 2) {
		/* Only set the TSX weight when no memory weight. */
1174
		if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1175
			data->weight = intel_hsw_weight(pebs);
1176

1177
		if (sample_type & PERF_SAMPLE_TRANSACTION)
1178
			data->txn = intel_hsw_transaction(pebs);
1179
	}
1180

1181 1182 1183 1184 1185 1186 1187 1188 1189 1190
	/*
	 * v3 supplies an accurate time stamp, so we use that
	 * for the time stamp.
	 *
	 * We can only do this for the default trace clock.
	 */
	if (x86_pmu.intel_cap.pebs_format >= 3 &&
		event->attr.use_clockid == 0)
		data->time = native_sched_clock_from_tsc(pebs->tsc);

1191
	if (has_branch_stack(event))
1192 1193 1194
		data->br_stack = &cpuc->lbr_stack;
}

1195 1196 1197 1198 1199 1200 1201
static inline void *
get_next_pebs_record_by_bit(void *base, void *top, int bit)
{
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
	void *at;
	u64 pebs_status;

1202 1203 1204 1205 1206 1207 1208
	/*
	 * fmt0 does not have a status bitfield (does not use
	 * perf_record_nhm format)
	 */
	if (x86_pmu.intel_cap.pebs_format < 1)
		return base;

1209 1210 1211 1212 1213 1214 1215
	if (base == NULL)
		return NULL;

	for (at = base; at < top; at += x86_pmu.pebs_record_size) {
		struct pebs_record_nhm *p = at;

		if (test_bit(bit, (unsigned long *)&p->status)) {
1216 1217 1218
			/* PEBS v3 has accurate status bits */
			if (x86_pmu.intel_cap.pebs_format >= 3)
				return at;
1219 1220 1221 1222 1223 1224

			if (p->status == (1 << bit))
				return at;

			/* clear non-PEBS bit and re-check */
			pebs_status = p->status & cpuc->pebs_enabled;
1225
			pebs_status &= PEBS_COUNTER_MASK;
1226 1227 1228 1229 1230 1231 1232
			if (pebs_status == (1 << bit))
				return at;
		}
	}
	return NULL;
}

1233
static void __intel_pmu_pebs_event(struct perf_event *event,
1234 1235 1236
				   struct pt_regs *iregs,
				   void *base, void *top,
				   int bit, int count)
1237 1238 1239
{
	struct perf_sample_data data;
	struct pt_regs regs;
1240
	void *at = get_next_pebs_record_by_bit(base, top, bit);
1241

1242 1243
	if (!intel_pmu_save_and_restart(event) &&
	    !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1244 1245
		return;

1246 1247 1248 1249 1250 1251
	while (count > 1) {
		setup_pebs_sample_data(event, iregs, at, &data, &regs);
		perf_event_output(event, &data, &regs);
		at += x86_pmu.pebs_record_size;
		at = get_next_pebs_record_by_bit(at, top, bit);
		count--;
1252 1253 1254
	}

	setup_pebs_sample_data(event, iregs, at, &data, &regs);
1255

1256 1257 1258 1259 1260
	/*
	 * All but the last records are processed.
	 * The last one is left to be able to call the overflow handler.
	 */
	if (perf_event_overflow(event, &data, &regs)) {
P
Peter Zijlstra 已提交
1261
		x86_pmu_stop(event, 0);
1262 1263 1264
		return;
	}

1265 1266
}

1267 1268
static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
{
1269
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1270 1271 1272 1273 1274
	struct debug_store *ds = cpuc->ds;
	struct perf_event *event = cpuc->events[0]; /* PMC0 only */
	struct pebs_record_core *at, *top;
	int n;

1275
	if (!x86_pmu.pebs_active)
1276 1277 1278 1279 1280
		return;

	at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
	top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;

1281 1282 1283 1284 1285 1286
	/*
	 * Whatever else happens, drain the thing
	 */
	ds->pebs_index = ds->pebs_buffer_base;

	if (!test_bit(0, cpuc->active_mask))
P
Peter Zijlstra 已提交
1287
		return;
1288

1289 1290
	WARN_ON_ONCE(!event);

P
Peter Zijlstra 已提交
1291
	if (!event->attr.precise_ip)
1292 1293
		return;

1294
	n = top - at;
1295 1296
	if (n <= 0)
		return;
1297

1298
	__intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1299 1300
}

1301
static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1302
{
1303
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1304
	struct debug_store *ds = cpuc->ds;
1305 1306 1307
	struct perf_event *event;
	void *base, *at, *top;
	short counts[MAX_PEBS_EVENTS] = {};
1308
	short error[MAX_PEBS_EVENTS] = {};
1309
	int bit, i;
1310 1311 1312 1313

	if (!x86_pmu.pebs_active)
		return;

1314
	base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1315
	top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1316 1317 1318

	ds->pebs_index = ds->pebs_buffer_base;

1319
	if (unlikely(base >= top))
1320 1321
		return;

1322
	for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1323
		struct pebs_record_nhm *p = at;
1324
		u64 pebs_status;
1325

1326 1327 1328 1329
		pebs_status = p->status & cpuc->pebs_enabled;
		pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;

		/* PEBS v3 has more accurate status bits */
1330
		if (x86_pmu.intel_cap.pebs_format >= 3) {
1331 1332
			for_each_set_bit(bit, (unsigned long *)&pebs_status,
					 x86_pmu.max_pebs_events)
1333 1334 1335 1336 1337
				counts[bit]++;

			continue;
		}

1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349
		/*
		 * On some CPUs the PEBS status can be zero when PEBS is
		 * racing with clearing of GLOBAL_STATUS.
		 *
		 * Normally we would drop that record, but in the
		 * case when there is only a single active PEBS event
		 * we can assume it's for that event.
		 */
		if (!pebs_status && cpuc->pebs_enabled &&
			!(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
			pebs_status = cpuc->pebs_enabled;

1350
		bit = find_first_bit((unsigned long *)&pebs_status,
1351
					x86_pmu.max_pebs_events);
1352
		if (bit >= x86_pmu.max_pebs_events)
1353
			continue;
1354

1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369
		/*
		 * The PEBS hardware does not deal well with the situation
		 * when events happen near to each other and multiple bits
		 * are set. But it should happen rarely.
		 *
		 * If these events include one PEBS and multiple non-PEBS
		 * events, it doesn't impact PEBS record. The record will
		 * be handled normally. (slow path)
		 *
		 * If these events include two or more PEBS events, the
		 * records for the events can be collapsed into a single
		 * one, and it's not possible to reconstruct all events
		 * that caused the PEBS record. It's called collision.
		 * If collision happened, the record will be dropped.
		 */
1370 1371 1372 1373 1374
		if (p->status != (1ULL << bit)) {
			for_each_set_bit(i, (unsigned long *)&pebs_status,
					 x86_pmu.max_pebs_events)
				error[i]++;
			continue;
1375
		}
1376

1377 1378
		counts[bit]++;
	}
1379

1380
	for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1381
		if ((counts[bit] == 0) && (error[bit] == 0))
1382
			continue;
1383

1384
		event = cpuc->events[bit];
1385 1386 1387 1388 1389
		if (WARN_ON_ONCE(!event))
			continue;

		if (WARN_ON_ONCE(!event->attr.precise_ip))
			continue;
1390

1391
		/* log dropped samples number */
1392
		if (error[bit]) {
1393 1394
			perf_log_lost_samples(event, error[bit]);

1395 1396 1397 1398
			if (perf_event_account_interrupt(event))
				x86_pmu_stop(event, 0);
		}

1399 1400 1401 1402
		if (counts[bit]) {
			__intel_pmu_pebs_event(event, iregs, base,
					       top, bit, counts[bit]);
		}
1403 1404 1405 1406 1407 1408 1409
	}
}

/*
 * BTS, PEBS probe and setup
 */

1410
void __init intel_ds_init(void)
1411 1412 1413 1414 1415 1416 1417 1418 1419
{
	/*
	 * No support for 32bit formats
	 */
	if (!boot_cpu_has(X86_FEATURE_DTES64))
		return;

	x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1420
	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1421
	if (x86_pmu.pebs) {
1422 1423
		char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
		int format = x86_pmu.intel_cap.pebs_format;
1424 1425 1426

		switch (format) {
		case 0:
1427
			pr_cont("PEBS fmt0%c, ", pebs_type);
1428
			x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1429 1430 1431 1432 1433 1434 1435 1436
			/*
			 * Using >PAGE_SIZE buffers makes the WRMSR to
			 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
			 * mysteriously hang on Core2.
			 *
			 * As a workaround, we don't do this.
			 */
			x86_pmu.pebs_buffer_size = PAGE_SIZE;
1437 1438 1439 1440
			x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
			break;

		case 1:
1441
			pr_cont("PEBS fmt1%c, ", pebs_type);
1442 1443 1444 1445
			x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
			break;

1446 1447 1448
		case 2:
			pr_cont("PEBS fmt2%c, ", pebs_type);
			x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1449
			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1450 1451
			break;

1452 1453 1454 1455 1456
		case 3:
			pr_cont("PEBS fmt3%c, ", pebs_type);
			x86_pmu.pebs_record_size =
						sizeof(struct pebs_record_skl);
			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1457
			x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1458 1459
			break;

1460
		default:
1461
			pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
1462 1463 1464 1465
			x86_pmu.pebs = 0;
		}
	}
}
1466 1467 1468

void perf_restore_debug_store(void)
{
1469 1470
	struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);

1471 1472 1473
	if (!x86_pmu.bts && !x86_pmu.pebs)
		return;

1474
	wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1475
}