spi-davinci.c 27.2 KB
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/*
 * Copyright (C) 2009 Texas Instruments.
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 * Copyright (C) 2010 EF Johnson Technologies
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/edma.h>
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#include <linux/of.h>
#include <linux/of_device.h>
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#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
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#include <linux/slab.h>
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#include <linux/platform_data/spi-davinci.h>
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#define SPI_NO_RESOURCE		((resource_size_t)-1)

#define SPI_MAX_CHIPSELECT	2

#define CS_DEFAULT	0xFF

#define SPIFMT_PHASE_MASK	BIT(16)
#define SPIFMT_POLARITY_MASK	BIT(17)
#define SPIFMT_DISTIMER_MASK	BIT(18)
#define SPIFMT_SHIFTDIR_MASK	BIT(20)
#define SPIFMT_WAITENA_MASK	BIT(21)
#define SPIFMT_PARITYENA_MASK	BIT(22)
#define SPIFMT_ODD_PARITY_MASK	BIT(23)
#define SPIFMT_WDELAY_MASK	0x3f000000u
#define SPIFMT_WDELAY_SHIFT	24
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#define SPIFMT_PRESCALE_SHIFT	8
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/* SPIPC0 */
#define SPIPC0_DIFUN_MASK	BIT(11)		/* MISO */
#define SPIPC0_DOFUN_MASK	BIT(10)		/* MOSI */
#define SPIPC0_CLKFUN_MASK	BIT(9)		/* CLK */
#define SPIPC0_SPIENA_MASK	BIT(8)		/* nREADY */

#define SPIINT_MASKALL		0x0101035F
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#define SPIINT_MASKINT		0x0000015F
#define SPI_INTLVL_1		0x000001FF
#define SPI_INTLVL_0		0x00000000
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/* SPIDAT1 (upper 16 bit defines) */
#define SPIDAT1_CSHOLD_MASK	BIT(12)

/* SPIGCR1 */
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#define SPIGCR1_CLKMOD_MASK	BIT(1)
#define SPIGCR1_MASTER_MASK     BIT(0)
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#define SPIGCR1_POWERDOWN_MASK	BIT(8)
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#define SPIGCR1_LOOPBACK_MASK	BIT(16)
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#define SPIGCR1_SPIENA_MASK	BIT(24)
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/* SPIBUF */
#define SPIBUF_TXFULL_MASK	BIT(29)
#define SPIBUF_RXEMPTY_MASK	BIT(31)

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/* SPIDELAY */
#define SPIDELAY_C2TDELAY_SHIFT 24
#define SPIDELAY_C2TDELAY_MASK  (0xFF << SPIDELAY_C2TDELAY_SHIFT)
#define SPIDELAY_T2CDELAY_SHIFT 16
#define SPIDELAY_T2CDELAY_MASK  (0xFF << SPIDELAY_T2CDELAY_SHIFT)
#define SPIDELAY_T2EDELAY_SHIFT 8
#define SPIDELAY_T2EDELAY_MASK  (0xFF << SPIDELAY_T2EDELAY_SHIFT)
#define SPIDELAY_C2EDELAY_SHIFT 0
#define SPIDELAY_C2EDELAY_MASK  0xFF

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/* Error Masks */
#define SPIFLG_DLEN_ERR_MASK		BIT(0)
#define SPIFLG_TIMEOUT_MASK		BIT(1)
#define SPIFLG_PARERR_MASK		BIT(2)
#define SPIFLG_DESYNC_MASK		BIT(3)
#define SPIFLG_BITERR_MASK		BIT(4)
#define SPIFLG_OVRRUN_MASK		BIT(6)
#define SPIFLG_BUF_INIT_ACTIVE_MASK	BIT(24)
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#define SPIFLG_ERROR_MASK		(SPIFLG_DLEN_ERR_MASK \
				| SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
				| SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
				| SPIFLG_OVRRUN_MASK)
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#define SPIINT_DMA_REQ_EN	BIT(16)

/* SPI Controller registers */
#define SPIGCR0		0x00
#define SPIGCR1		0x04
#define SPIINT		0x08
#define SPILVL		0x0c
#define SPIFLG		0x10
#define SPIPC0		0x14
#define SPIDAT1		0x3c
#define SPIBUF		0x40
#define SPIDELAY	0x48
#define SPIDEF		0x4c
#define SPIFMT0		0x50

/* SPI Controller driver's private data. */
struct davinci_spi {
	struct spi_bitbang	bitbang;
	struct clk		*clk;

	u8			version;
	resource_size_t		pbase;
	void __iomem		*base;
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	u32			irq;
	struct completion	done;
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	const void		*tx;
	void			*rx;
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	int			rcount;
	int			wcount;
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	struct dma_chan		*dma_rx;
	struct dma_chan		*dma_tx;
	int			dma_rx_chnum;
	int			dma_tx_chnum;

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	struct davinci_spi_platform_data pdata;
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	void			(*get_rx)(u32 rx_data, struct davinci_spi *);
	u32			(*get_tx)(struct davinci_spi *);

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	u8			bytes_per_word[SPI_MAX_CHIPSELECT];
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};

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static struct davinci_spi_config davinci_spi_default_cfg;

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static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
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{
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	if (dspi->rx) {
		u8 *rx = dspi->rx;
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		*rx++ = (u8)data;
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		dspi->rx = rx;
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	}
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}

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static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
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{
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	if (dspi->rx) {
		u16 *rx = dspi->rx;
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		*rx++ = (u16)data;
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		dspi->rx = rx;
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	}
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}

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static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
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{
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	u32 data = 0;
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	if (dspi->tx) {
		const u8 *tx = dspi->tx;
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		data = *tx++;
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		dspi->tx = tx;
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	}
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	return data;
}

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static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
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{
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	u32 data = 0;
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	if (dspi->tx) {
		const u16 *tx = dspi->tx;
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		data = *tx++;
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		dspi->tx = tx;
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	}
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	return data;
}

static inline void set_io_bits(void __iomem *addr, u32 bits)
{
	u32 v = ioread32(addr);

	v |= bits;
	iowrite32(v, addr);
}

static inline void clear_io_bits(void __iomem *addr, u32 bits)
{
	u32 v = ioread32(addr);

	v &= ~bits;
	iowrite32(v, addr);
}

/*
 * Interface to control the chip select signal
 */
static void davinci_spi_chipselect(struct spi_device *spi, int value)
{
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	struct davinci_spi *dspi;
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	struct davinci_spi_platform_data *pdata;
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	u8 chip_sel = spi->chip_select;
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	u16 spidat1 = CS_DEFAULT;
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	bool gpio_chipsel = false;
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	dspi = spi_master_get_devdata(spi->master);
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	pdata = &dspi->pdata;
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	if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
				pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
		gpio_chipsel = true;

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	/*
	 * Board specific chip select logic decides the polarity and cs
	 * line for the controller
	 */
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	if (gpio_chipsel) {
		if (value == BITBANG_CS_ACTIVE)
			gpio_set_value(pdata->chip_sel[chip_sel], 0);
		else
			gpio_set_value(pdata->chip_sel[chip_sel], 1);
	} else {
		if (value == BITBANG_CS_ACTIVE) {
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			spidat1 |= SPIDAT1_CSHOLD_MASK;
			spidat1 &= ~(0x1 << chip_sel);
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		}
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		iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
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	}
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}

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/**
 * davinci_spi_get_prescale - Calculates the correct prescale value
 * @maxspeed_hz: the maximum rate the SPI clock can run at
 *
 * This function calculates the prescale value that generates a clock rate
 * less than or equal to the specified maximum.
 *
 * Returns: calculated prescale - 1 for easy programming into SPI registers
 * or negative error number if valid prescalar cannot be updated.
 */
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static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
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							u32 max_speed_hz)
{
	int ret;

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	ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
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	if (ret < 3 || ret > 256)
		return -EINVAL;

	return ret - 1;
}

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/**
 * davinci_spi_setup_transfer - This functions will determine transfer method
 * @spi: spi device on which data transfer to be done
 * @t: spi transfer in which transfer info is filled
 *
 * This function determines data transfer method (8/16/32 bit transfer).
 * It will also set the SPI Clock Control register according to
 * SPI slave device freq.
 */
static int davinci_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{

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	struct davinci_spi *dspi;
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	struct davinci_spi_config *spicfg;
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	u8 bits_per_word = 0;
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	u32 hz = 0, spifmt = 0, prescale = 0;
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	dspi = spi_master_get_devdata(spi->master);
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	spicfg = (struct davinci_spi_config *)spi->controller_data;
	if (!spicfg)
		spicfg = &davinci_spi_default_cfg;
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	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	}

	/* if bits_per_word is not set then set it default */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	/*
	 * Assign function pointer to appropriate transfer method
	 * 8bit, 16bit or 32bit transfer
	 */
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	if (bits_per_word <= 8) {
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		dspi->get_rx = davinci_spi_rx_buf_u8;
		dspi->get_tx = davinci_spi_tx_buf_u8;
		dspi->bytes_per_word[spi->chip_select] = 1;
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	} else {
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		dspi->get_rx = davinci_spi_rx_buf_u16;
		dspi->get_tx = davinci_spi_tx_buf_u16;
		dspi->bytes_per_word[spi->chip_select] = 2;
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	}
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	if (!hz)
		hz = spi->max_speed_hz;

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	/* Set up SPIFMTn register, unique to this chipselect. */

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	prescale = davinci_spi_get_prescale(dspi, hz);
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	if (prescale < 0)
		return prescale;

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	spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);

	if (spi->mode & SPI_LSB_FIRST)
		spifmt |= SPIFMT_SHIFTDIR_MASK;

	if (spi->mode & SPI_CPOL)
		spifmt |= SPIFMT_POLARITY_MASK;

	if (!(spi->mode & SPI_CPHA))
		spifmt |= SPIFMT_PHASE_MASK;

	/*
	 * Version 1 hardware supports two basic SPI modes:
	 *  - Standard SPI mode uses 4 pins, with chipselect
	 *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
	 *	(distinct from SPI_3WIRE, with just one data wire;
	 *	or similar variants without MOSI or without MISO)
	 *
	 * Version 2 hardware supports an optional handshaking signal,
	 * so it can support two more modes:
	 *  - 5 pin SPI variant is standard SPI plus SPI_READY
	 *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
	 */

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	if (dspi->version == SPI_VERSION_2) {
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		u32 delay = 0;

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		spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
							& SPIFMT_WDELAY_MASK);
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		if (spicfg->odd_parity)
			spifmt |= SPIFMT_ODD_PARITY_MASK;

		if (spicfg->parity_enable)
			spifmt |= SPIFMT_PARITYENA_MASK;

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		if (spicfg->timer_disable) {
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			spifmt |= SPIFMT_DISTIMER_MASK;
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		} else {
			delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
						& SPIDELAY_C2TDELAY_MASK;
			delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
						& SPIDELAY_T2CDELAY_MASK;
		}
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		if (spi->mode & SPI_READY) {
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			spifmt |= SPIFMT_WAITENA_MASK;
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			delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
						& SPIDELAY_T2EDELAY_MASK;
			delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
						& SPIDELAY_C2EDELAY_MASK;
		}

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		iowrite32(delay, dspi->base + SPIDELAY);
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	}

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	iowrite32(spifmt, dspi->base + SPIFMT0);
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	return 0;
}

/**
 * davinci_spi_setup - This functions will set default transfer method
 * @spi: spi device on which data transfer to be done
 *
 * This functions sets the default transfer method.
 */
static int davinci_spi_setup(struct spi_device *spi)
{
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	int retval = 0;
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	struct davinci_spi *dspi;
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	struct davinci_spi_platform_data *pdata;
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	dspi = spi_master_get_devdata(spi->master);
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	pdata = &dspi->pdata;
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	/* if bits per word length is zero then set it default 8 */
	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

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	if (!(spi->mode & SPI_NO_CS)) {
		if ((pdata->chip_sel == NULL) ||
		    (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
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			set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
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	}

	if (spi->mode & SPI_READY)
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		set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
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	if (spi->mode & SPI_LOOP)
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		set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
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	else
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		clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
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	return retval;
}

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static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
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{
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	struct device *sdev = dspi->bitbang.master->dev.parent;
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	if (int_status & SPIFLG_TIMEOUT_MASK) {
		dev_dbg(sdev, "SPI Time-out Error\n");
		return -ETIMEDOUT;
	}
	if (int_status & SPIFLG_DESYNC_MASK) {
		dev_dbg(sdev, "SPI Desynchronization Error\n");
		return -EIO;
	}
	if (int_status & SPIFLG_BITERR_MASK) {
		dev_dbg(sdev, "SPI Bit error\n");
		return -EIO;
	}

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	if (dspi->version == SPI_VERSION_2) {
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		if (int_status & SPIFLG_DLEN_ERR_MASK) {
			dev_dbg(sdev, "SPI Data Length Error\n");
			return -EIO;
		}
		if (int_status & SPIFLG_PARERR_MASK) {
			dev_dbg(sdev, "SPI Parity Error\n");
			return -EIO;
		}
		if (int_status & SPIFLG_OVRRUN_MASK) {
			dev_dbg(sdev, "SPI Data Overrun error\n");
			return -EIO;
		}
		if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
			dev_dbg(sdev, "SPI Buffer Init Active\n");
			return -EBUSY;
		}
	}

	return 0;
}

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/**
 * davinci_spi_process_events - check for and handle any SPI controller events
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 * @dspi: the controller data
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 *
 * This function will check the SPIFLG register and handle any events that are
 * detected there
 */
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static int davinci_spi_process_events(struct davinci_spi *dspi)
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{
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	u32 buf, status, errors = 0, spidat1;
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	buf = ioread32(dspi->base + SPIBUF);
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	if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
		dspi->get_rx(buf & 0xFFFF, dspi);
		dspi->rcount--;
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	}

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	status = ioread32(dspi->base + SPIFLG);
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	if (unlikely(status & SPIFLG_ERROR_MASK)) {
		errors = status & SPIFLG_ERROR_MASK;
		goto out;
	}

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	if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
		spidat1 = ioread32(dspi->base + SPIDAT1);
		dspi->wcount--;
		spidat1 &= ~0xFFFF;
		spidat1 |= 0xFFFF & dspi->get_tx(dspi);
		iowrite32(spidat1, dspi->base + SPIDAT1);
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	}

out:
	return errors;
}

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static void davinci_spi_dma_rx_callback(void *data)
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{
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	struct davinci_spi *dspi = (struct davinci_spi *)data;
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	dspi->rcount = 0;
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	if (!dspi->wcount && !dspi->rcount)
		complete(&dspi->done);
}
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static void davinci_spi_dma_tx_callback(void *data)
{
	struct davinci_spi *dspi = (struct davinci_spi *)data;

	dspi->wcount = 0;

	if (!dspi->wcount && !dspi->rcount)
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		complete(&dspi->done);
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}

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/**
 * davinci_spi_bufs - functions which will handle transfer data
 * @spi: spi device on which data transfer to be done
 * @t: spi transfer in which transfer info is filled
 *
 * This function will put data to be transferred into data register
 * of SPI controller and then wait until the completion will be marked
 * by the IRQ Handler.
 */
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static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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	struct davinci_spi *dspi;
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	int data_type, ret = -ENOMEM;
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	u32 tx_data, spidat1;
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	u32 errors = 0;
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	struct davinci_spi_config *spicfg;
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	struct davinci_spi_platform_data *pdata;
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	unsigned uninitialized_var(rx_buf_count);
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	void *dummy_buf = NULL;
	struct scatterlist sg_rx, sg_tx;
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	dspi = spi_master_get_devdata(spi->master);
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	pdata = &dspi->pdata;
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	spicfg = (struct davinci_spi_config *)spi->controller_data;
	if (!spicfg)
		spicfg = &davinci_spi_default_cfg;
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	/* convert len to words based on bits_per_word */
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	data_type = dspi->bytes_per_word[spi->chip_select];
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	dspi->tx = t->tx_buf;
	dspi->rx = t->rx_buf;
	dspi->wcount = t->len / data_type;
	dspi->rcount = dspi->wcount;
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	spidat1 = ioread32(dspi->base + SPIDAT1);
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	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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	INIT_COMPLETION(dspi->done);
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	if (spicfg->io_type == SPI_IO_TYPE_INTR)
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		set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
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561 562
	if (spicfg->io_type != SPI_IO_TYPE_DMA) {
		/* start the transfer */
S
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563 564 565 566 567
		dspi->wcount--;
		tx_data = dspi->get_tx(dspi);
		spidat1 &= 0xFFFF0000;
		spidat1 |= tx_data & 0xFFFF;
		iowrite32(spidat1, dspi->base + SPIDAT1);
568
	} else {
569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594
		struct dma_slave_config dma_rx_conf = {
			.direction = DMA_DEV_TO_MEM,
			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
			.src_addr_width = data_type,
			.src_maxburst = 1,
		};
		struct dma_slave_config dma_tx_conf = {
			.direction = DMA_MEM_TO_DEV,
			.dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
			.dst_addr_width = data_type,
			.dst_maxburst = 1,
		};
		struct dma_async_tx_descriptor *rxdesc;
		struct dma_async_tx_descriptor *txdesc;
		void *buf;

		dummy_buf = kzalloc(t->len, GFP_KERNEL);
		if (!dummy_buf)
			goto err_alloc_dummy_buf;

		dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
		dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);

		sg_init_table(&sg_rx, 1);
		if (!t->rx_buf)
			buf = dummy_buf;
595
		else
596 597 598 599 600 601
			buf = t->rx_buf;
		t->rx_dma = dma_map_single(&spi->dev, buf,
				t->len, DMA_FROM_DEVICE);
		if (!t->rx_dma) {
			ret = -EFAULT;
			goto err_rx_map;
602
		}
603 604
		sg_dma_address(&sg_rx) = t->rx_dma;
		sg_dma_len(&sg_rx) = t->len;
605

606 607 608 609 610 611 612 613 614 615
		sg_init_table(&sg_tx, 1);
		if (!t->tx_buf)
			buf = dummy_buf;
		else
			buf = (void *)t->tx_buf;
		t->tx_dma = dma_map_single(&spi->dev, buf,
				t->len, DMA_FROM_DEVICE);
		if (!t->tx_dma) {
			ret = -EFAULT;
			goto err_tx_map;
616
		}
617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635
		sg_dma_address(&sg_tx) = t->tx_dma;
		sg_dma_len(&sg_tx) = t->len;

		rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
				&sg_rx, 1, DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
		if (!rxdesc)
			goto err_desc;

		txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
				&sg_tx, 1, DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
		if (!txdesc)
			goto err_desc;

		rxdesc->callback = davinci_spi_dma_rx_callback;
		rxdesc->callback_param = (void *)dspi;
		txdesc->callback = davinci_spi_dma_tx_callback;
		txdesc->callback_param = (void *)dspi;
636 637

		if (pdata->cshold_bug)
S
Sekhar Nori 已提交
638
			iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
639

640 641 642 643 644 645
		dmaengine_submit(rxdesc);
		dmaengine_submit(txdesc);

		dma_async_issue_pending(dspi->dma_rx);
		dma_async_issue_pending(dspi->dma_tx);

S
Sekhar Nori 已提交
646
		set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
647
	}
648

649
	/* Wait for the transfer to complete */
650
	if (spicfg->io_type != SPI_IO_TYPE_POLL) {
S
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651
		wait_for_completion_interruptible(&(dspi->done));
652
	} else {
S
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653 654
		while (dspi->rcount > 0 || dspi->wcount > 0) {
			errors = davinci_spi_process_events(dspi);
655 656 657
			if (errors)
				break;
			cpu_relax();
658 659 660
		}
	}

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661
	clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
662
	if (spicfg->io_type == SPI_IO_TYPE_DMA) {
S
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663
		clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
664 665 666 667 668 669

		dma_unmap_single(&spi->dev, t->rx_dma,
				t->len, DMA_FROM_DEVICE);
		dma_unmap_single(&spi->dev, t->tx_dma,
				t->len, DMA_TO_DEVICE);
		kfree(dummy_buf);
670
	}
671

S
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672 673
	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
674

675 676 677 678
	/*
	 * Check for bit error, desync error,parity error,timeout error and
	 * receive overflow errors
	 */
679
	if (errors) {
S
Sekhar Nori 已提交
680
		ret = davinci_spi_check_error(dspi, errors);
681 682
		WARN(!ret, "%s: error reported but no error found!\n",
							dev_name(&spi->dev));
683
		return ret;
684
	}
685

S
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686
	if (dspi->rcount != 0 || dspi->wcount != 0) {
687
		dev_err(&spi->dev, "SPI data transfer error\n");
688 689 690
		return -EIO;
	}

691
	return t->len;
692 693 694 695 696 697 698 699 700

err_desc:
	dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
err_tx_map:
	dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
err_rx_map:
	kfree(dummy_buf);
err_alloc_dummy_buf:
	return ret;
701 702
}

703 704 705 706 707 708 709 710 711 712 713 714 715
/**
 * dummy_thread_fn - dummy thread function
 * @irq: IRQ number for this SPI Master
 * @context_data: structure for SPI Master controller davinci_spi
 *
 * This is to satisfy the request_threaded_irq() API so that the irq
 * handler is called in interrupt context.
 */
static irqreturn_t dummy_thread_fn(s32 irq, void *data)
{
	return IRQ_HANDLED;
}

716 717 718 719 720 721 722 723 724 725 726
/**
 * davinci_spi_irq - Interrupt handler for SPI Master Controller
 * @irq: IRQ number for this SPI Master
 * @context_data: structure for SPI Master controller davinci_spi
 *
 * ISR will determine that interrupt arrives either for READ or WRITE command.
 * According to command it will do the appropriate action. It will check
 * transfer length and if it is not zero then dispatch transfer command again.
 * If transfer length is zero then it will indicate the COMPLETION so that
 * davinci_spi_bufs function can go ahead.
 */
S
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727
static irqreturn_t davinci_spi_irq(s32 irq, void *data)
728
{
S
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729
	struct davinci_spi *dspi = data;
730 731
	int status;

S
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732
	status = davinci_spi_process_events(dspi);
733
	if (unlikely(status != 0))
S
Sekhar Nori 已提交
734
		clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
735

S
Sekhar Nori 已提交
736 737
	if ((!dspi->rcount && !dspi->wcount) || status)
		complete(&dspi->done);
738 739 740 741

	return IRQ_HANDLED;
}

S
Sekhar Nori 已提交
742
static int davinci_spi_request_dma(struct davinci_spi *dspi)
743
{
744 745
	dma_cap_mask_t mask;
	struct device *sdev = dspi->bitbang.master->dev.parent;
746 747
	int r;

748 749 750 751 752 753 754 755
	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
					   &dspi->dma_rx_chnum);
	if (!dspi->dma_rx) {
		dev_err(sdev, "request RX DMA channel failed\n");
		r = -ENODEV;
756
		goto rx_dma_failed;
757 758
	}

759 760 761 762 763
	dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
					   &dspi->dma_tx_chnum);
	if (!dspi->dma_tx) {
		dev_err(sdev, "request TX DMA channel failed\n");
		r = -ENODEV;
764
		goto tx_dma_failed;
765 766 767
	}

	return 0;
768

769
tx_dma_failed:
770
	dma_release_channel(dspi->dma_rx);
771 772
rx_dma_failed:
	return r;
773 774
}

775 776 777
#if defined(CONFIG_OF)
static const struct of_device_id davinci_spi_of_match[] = {
	{
778
		.compatible = "ti,dm6441-spi",
779 780
	},
	{
781
		.compatible = "ti,da830-spi",
782 783 784 785
		.data = (void *)SPI_VERSION_2,
	},
	{ },
};
786
MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838

/**
 * spi_davinci_get_pdata - Get platform data from DTS binding
 * @pdev: ptr to platform data
 * @dspi: ptr to driver data
 *
 * Parses and populates pdata in dspi from device tree bindings.
 *
 * NOTE: Not all platform data params are supported currently.
 */
static int spi_davinci_get_pdata(struct platform_device *pdev,
			struct davinci_spi *dspi)
{
	struct device_node *node = pdev->dev.of_node;
	struct davinci_spi_platform_data *pdata;
	unsigned int num_cs, intr_line = 0;
	const struct of_device_id *match;

	pdata = &dspi->pdata;

	pdata->version = SPI_VERSION_1;
	match = of_match_device(of_match_ptr(davinci_spi_of_match),
				&pdev->dev);
	if (!match)
		return -ENODEV;

	/* match data has the SPI version number for SPI_VERSION_2 */
	if (match->data == (void *)SPI_VERSION_2)
		pdata->version = SPI_VERSION_2;

	/*
	 * default num_cs is 1 and all chipsel are internal to the chip
	 * indicated by chip_sel being NULL. GPIO based CS is not
	 * supported yet in DT bindings.
	 */
	num_cs = 1;
	of_property_read_u32(node, "num-cs", &num_cs);
	pdata->num_chipselect = num_cs;
	of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
	pdata->intr_line = intr_line;
	return 0;
}
#else
#define davinci_spi_of_match NULL
static struct davinci_spi_platform_data
	*spi_davinci_get_pdata(struct platform_device *pdev,
		struct davinci_spi *dspi)
{
	return -ENODEV;
}
#endif

839 840 841
/**
 * davinci_spi_probe - probe function for SPI Master Controller
 * @pdev: platform_device structure which contains plateform specific data
842 843 844 845 846 847 848
 *
 * According to Linux Device Model this function will be invoked by Linux
 * with platform_device struct which contains the device specific info.
 * This function will map the SPI controller's memory, register IRQ,
 * Reset SPI controller and setting its registers to default value.
 * It will invoke spi_bitbang_start to create work queue so that client driver
 * can register transfer method to work queue.
849
 */
850
static int davinci_spi_probe(struct platform_device *pdev)
851 852
{
	struct spi_master *master;
S
Sekhar Nori 已提交
853
	struct davinci_spi *dspi;
854 855 856 857 858
	struct davinci_spi_platform_data *pdata;
	struct resource *r, *mem;
	resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
	resource_size_t	dma_tx_chan = SPI_NO_RESOURCE;
	int i = 0, ret = 0;
859
	u32 spipc0;
860 861 862 863 864 865 866

	master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
	if (master == NULL) {
		ret = -ENOMEM;
		goto err;
	}

867
	platform_set_drvdata(pdev, master);
868

S
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869 870
	dspi = spi_master_get_devdata(master);
	if (dspi == NULL) {
871 872 873 874
		ret = -ENOENT;
		goto free_master;
	}

875 876 877 878 879 880 881 882 883 884 885 886 887
	if (pdev->dev.platform_data) {
		pdata = pdev->dev.platform_data;
		dspi->pdata = *pdata;
	} else {
		/* update dspi pdata with that from the DT */
		ret = spi_davinci_get_pdata(pdev, dspi);
		if (ret < 0)
			goto free_master;
	}

	/* pdata in dspi is now updated and point pdata to that */
	pdata = &dspi->pdata;

888 889 890 891 892 893
	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENOENT;
		goto free_master;
	}

S
Sekhar Nori 已提交
894
	dspi->pbase = r->start;
895

896
	mem = request_mem_region(r->start, resource_size(r), pdev->name);
897 898 899 900 901
	if (mem == NULL) {
		ret = -EBUSY;
		goto free_master;
	}

S
Sekhar Nori 已提交
902 903
	dspi->base = ioremap(r->start, resource_size(r));
	if (dspi->base == NULL) {
904 905 906 907
		ret = -ENOMEM;
		goto release_region;
	}

S
Sekhar Nori 已提交
908 909
	dspi->irq = platform_get_irq(pdev, 0);
	if (dspi->irq <= 0) {
910 911 912 913
		ret = -EINVAL;
		goto unmap_io;
	}

914 915
	ret = request_threaded_irq(dspi->irq, davinci_spi_irq, dummy_thread_fn,
				 0, dev_name(&pdev->dev), dspi);
916 917 918
	if (ret)
		goto unmap_io;

S
Sekhar Nori 已提交
919 920
	dspi->bitbang.master = spi_master_get(master);
	if (dspi->bitbang.master == NULL) {
921
		ret = -ENODEV;
922
		goto irq_free;
923 924
	}

S
Sekhar Nori 已提交
925 926
	dspi->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(dspi->clk)) {
927 928 929
		ret = -ENODEV;
		goto put_master;
	}
930
	clk_prepare_enable(dspi->clk);
931

932
	master->dev.of_node = pdev->dev.of_node;
933 934
	master->bus_num = pdev->id;
	master->num_chipselect = pdata->num_chipselect;
935
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
936 937
	master->setup = davinci_spi_setup;

S
Sekhar Nori 已提交
938 939
	dspi->bitbang.chipselect = davinci_spi_chipselect;
	dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
940

S
Sekhar Nori 已提交
941
	dspi->version = pdata->version;
942

S
Sekhar Nori 已提交
943 944 945
	dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
	if (dspi->version == SPI_VERSION_2)
		dspi->bitbang.flags |= SPI_READY;
946

947 948 949 950 951 952 953
	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (r)
		dma_rx_chan = r->start;
	r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
	if (r)
		dma_tx_chan = r->start;

S
Sekhar Nori 已提交
954
	dspi->bitbang.txrx_bufs = davinci_spi_bufs;
955
	if (dma_rx_chan != SPI_NO_RESOURCE &&
956
	    dma_tx_chan != SPI_NO_RESOURCE) {
957 958
		dspi->dma_rx_chnum = dma_rx_chan;
		dspi->dma_tx_chnum = dma_tx_chan;
959

S
Sekhar Nori 已提交
960
		ret = davinci_spi_request_dma(dspi);
961 962 963
		if (ret)
			goto free_clk;

964 965 966
		dev_info(&pdev->dev, "DMA: supported\n");
		dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
				"event queue: %d\n", dma_rx_chan, dma_tx_chan,
967
				pdata->dma_event_q);
968 969
	}

S
Sekhar Nori 已提交
970 971
	dspi->get_rx = davinci_spi_rx_buf_u8;
	dspi->get_tx = davinci_spi_tx_buf_u8;
972

S
Sekhar Nori 已提交
973
	init_completion(&dspi->done);
974

975
	/* Reset In/OUT SPI module */
S
Sekhar Nori 已提交
976
	iowrite32(0, dspi->base + SPIGCR0);
977
	udelay(100);
S
Sekhar Nori 已提交
978
	iowrite32(1, dspi->base + SPIGCR0);
979

980
	/* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
981
	spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
S
Sekhar Nori 已提交
982
	iowrite32(spipc0, dspi->base + SPIPC0);
983

984 985 986 987 988 989 990 991
	/* initialize chip selects */
	if (pdata->chip_sel) {
		for (i = 0; i < pdata->num_chipselect; i++) {
			if (pdata->chip_sel[i] != SPI_INTERN_CS)
				gpio_direction_output(pdata->chip_sel[i], 1);
		}
	}

992
	if (pdata->intr_line)
S
Sekhar Nori 已提交
993
		iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
994
	else
S
Sekhar Nori 已提交
995
		iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
996

S
Sekhar Nori 已提交
997
	iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
998

999
	/* master mode default */
S
Sekhar Nori 已提交
1000 1001 1002
	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
1003

S
Sekhar Nori 已提交
1004
	ret = spi_bitbang_start(&dspi->bitbang);
1005
	if (ret)
1006
		goto free_dma;
1007

S
Sekhar Nori 已提交
1008
	dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1009 1010 1011

	return ret;

1012
free_dma:
1013 1014
	dma_release_channel(dspi->dma_rx);
	dma_release_channel(dspi->dma_tx);
1015
free_clk:
1016
	clk_disable_unprepare(dspi->clk);
S
Sekhar Nori 已提交
1017
	clk_put(dspi->clk);
1018 1019
put_master:
	spi_master_put(master);
1020
irq_free:
S
Sekhar Nori 已提交
1021
	free_irq(dspi->irq, dspi);
1022
unmap_io:
S
Sekhar Nori 已提交
1023
	iounmap(dspi->base);
1024
release_region:
S
Sekhar Nori 已提交
1025
	release_mem_region(dspi->pbase, resource_size(r));
1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040
free_master:
	kfree(master);
err:
	return ret;
}

/**
 * davinci_spi_remove - remove function for SPI Master Controller
 * @pdev: platform_device structure which contains plateform specific data
 *
 * This function will do the reverse action of davinci_spi_probe function
 * It will free the IRQ and SPI controller's memory region.
 * It will also call spi_bitbang_stop to destroy the work queue which was
 * created by spi_bitbang_start.
 */
1041
static int davinci_spi_remove(struct platform_device *pdev)
1042
{
S
Sekhar Nori 已提交
1043
	struct davinci_spi *dspi;
1044
	struct spi_master *master;
1045
	struct resource *r;
1046

1047
	master = platform_get_drvdata(pdev);
S
Sekhar Nori 已提交
1048
	dspi = spi_master_get_devdata(master);
1049

S
Sekhar Nori 已提交
1050
	spi_bitbang_stop(&dspi->bitbang);
1051

1052
	clk_disable_unprepare(dspi->clk);
S
Sekhar Nori 已提交
1053
	clk_put(dspi->clk);
1054
	spi_master_put(master);
S
Sekhar Nori 已提交
1055 1056
	free_irq(dspi->irq, dspi);
	iounmap(dspi->base);
1057
	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
S
Sekhar Nori 已提交
1058
	release_mem_region(dspi->pbase, resource_size(r));
1059 1060 1061 1062 1063

	return 0;
}

static struct platform_driver davinci_spi_driver = {
1064 1065 1066
	.driver = {
		.name = "spi_davinci",
		.owner = THIS_MODULE,
1067
		.of_match_table = davinci_spi_of_match,
1068
	},
1069
	.probe = davinci_spi_probe,
1070
	.remove = davinci_spi_remove,
1071
};
1072
module_platform_driver(davinci_spi_driver);
1073 1074 1075

MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
MODULE_LICENSE("GPL");