b44.c 58.1 KB
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/* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
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 *
 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
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 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
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 * Copyright (C) 2006 Broadcom Corporation.
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 * Copyright (C) 2007 Michael Buesch <m@bues.ch>
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 *
 * Distribute under GPL.
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_ether.h>
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#include <linux/if_vlan.h>
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#include <linux/etherdevice.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/ssb/ssb.h>
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#include <linux/slab.h>
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#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/irq.h>

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#include "b44.h"

#define DRV_MODULE_NAME		"b44"
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#define DRV_MODULE_VERSION	"2.0"
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#define DRV_DESCRIPTION		"Broadcom 44xx/47xx 10/100 PCI ethernet driver"
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#define B44_DEF_MSG_ENABLE	  \
	(NETIF_MSG_DRV		| \
	 NETIF_MSG_PROBE	| \
	 NETIF_MSG_LINK		| \
	 NETIF_MSG_TIMER	| \
	 NETIF_MSG_IFDOWN	| \
	 NETIF_MSG_IFUP		| \
	 NETIF_MSG_RX_ERR	| \
	 NETIF_MSG_TX_ERR)

/* length of time before we decide the hardware is borked,
 * and dev->tx_timeout() should be called to fix the problem
 */
#define B44_TX_TIMEOUT			(5 * HZ)

/* hardware minimum and maximum for a single frame's data payload */
#define B44_MIN_MTU			60
#define B44_MAX_MTU			1500

#define B44_RX_RING_SIZE		512
#define B44_DEF_RX_RING_PENDING		200
#define B44_RX_RING_BYTES	(sizeof(struct dma_desc) * \
				 B44_RX_RING_SIZE)
#define B44_TX_RING_SIZE		512
#define B44_DEF_TX_RING_PENDING		(B44_TX_RING_SIZE - 1)
#define B44_TX_RING_BYTES	(sizeof(struct dma_desc) * \
				 B44_TX_RING_SIZE)

#define TX_RING_GAP(BP)	\
	(B44_TX_RING_SIZE - (BP)->tx_pending)
#define TX_BUFFS_AVAIL(BP)						\
	(((BP)->tx_cons <= (BP)->tx_prod) ?				\
	  (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :		\
	  (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
#define NEXT_TX(N)		(((N) + 1) & (B44_TX_RING_SIZE - 1))

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#define RX_PKT_OFFSET		(RX_HEADER_LEN + 2)
#define RX_PKT_BUF_SZ		(1536 + RX_PKT_OFFSET)
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/* minimum number of free TX descriptors required to wake up TX process */
#define B44_TX_WAKEUP_THRESH		(B44_TX_RING_SIZE / 4)

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/* b44 internal pattern match filter info */
#define B44_PATTERN_BASE	0x400
#define B44_PATTERN_SIZE	0x80
#define B44_PMASK_BASE		0x600
#define B44_PMASK_SIZE		0x10
#define B44_MAX_PATTERNS	16
#define B44_ETHIPV6UDP_HLEN	62
#define B44_ETHIPV4UDP_HLEN	42

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MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
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MODULE_DESCRIPTION(DRV_DESCRIPTION);
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MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);

static int b44_debug = -1;	/* -1 == use B44_DEF_MSG_ENABLE as value */
module_param(b44_debug, int, 0);
MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");


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#ifdef CONFIG_B44_PCI
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static DEFINE_PCI_DEVICE_TABLE(b44_pci_tbl) = {
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	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
	{ 0 } /* terminate list with empty entry */
};
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MODULE_DEVICE_TABLE(pci, b44_pci_tbl);

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static struct pci_driver b44_pci_driver = {
	.name		= DRV_MODULE_NAME,
	.id_table	= b44_pci_tbl,
};
#endif /* CONFIG_B44_PCI */

static const struct ssb_device_id b44_ssb_tbl[] = {
	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
	SSB_DEVTABLE_END
};
MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);

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static void b44_halt(struct b44 *);
static void b44_init_rings(struct b44 *);
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#define B44_FULL_RESET		1
#define B44_FULL_RESET_SKIP_PHY	2
#define B44_PARTIAL_RESET	3
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#define B44_CHIP_RESET_FULL	4
#define B44_CHIP_RESET_PARTIAL	5
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static void b44_init_hw(struct b44 *, int);
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static int dma_desc_sync_size;
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static int instance;
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static const char b44_gstrings[][ETH_GSTRING_LEN] = {
#define _B44(x...)	# x,
B44_STAT_REG_DECLARE
#undef _B44
};

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static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
						dma_addr_t dma_base,
						unsigned long offset,
						enum dma_data_direction dir)
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{
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	dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
				   dma_desc_sync_size, dir);
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}

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static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
					     dma_addr_t dma_base,
					     unsigned long offset,
					     enum dma_data_direction dir)
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{
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	dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
				dma_desc_sync_size, dir);
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}

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static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
{
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	return ssb_read32(bp->sdev, reg);
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}

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static inline void bw32(const struct b44 *bp,
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			unsigned long reg, unsigned long val)
{
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	ssb_write32(bp->sdev, reg, val);
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}

static int b44_wait_bit(struct b44 *bp, unsigned long reg,
			u32 bit, unsigned long timeout, const int clear)
{
	unsigned long i;

	for (i = 0; i < timeout; i++) {
		u32 val = br32(bp, reg);

		if (clear && !(val & bit))
			break;
		if (!clear && (val & bit))
			break;
		udelay(10);
	}
	if (i == timeout) {
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		if (net_ratelimit())
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			netdev_err(bp->dev, "BUG!  Timeout waiting for bit %08x of register %lx to %s\n",
				   bit, reg, clear ? "clear" : "set");

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		return -ENODEV;
	}
	return 0;
}

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static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
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{
	u32 val;

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	bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
			    (index << CAM_CTRL_INDEX_SHIFT)));
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	b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
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	val = br32(bp, B44_CAM_DATA_LO);
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	data[2] = (val >> 24) & 0xFF;
	data[3] = (val >> 16) & 0xFF;
	data[4] = (val >> 8) & 0xFF;
	data[5] = (val >> 0) & 0xFF;
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	val = br32(bp, B44_CAM_DATA_HI);
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	data[0] = (val >> 8) & 0xFF;
	data[1] = (val >> 0) & 0xFF;
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}

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static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
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{
	u32 val;

	val  = ((u32) data[2]) << 24;
	val |= ((u32) data[3]) << 16;
	val |= ((u32) data[4]) <<  8;
	val |= ((u32) data[5]) <<  0;
	bw32(bp, B44_CAM_DATA_LO, val);
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	val = (CAM_DATA_HI_VALID |
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	       (((u32) data[0]) << 8) |
	       (((u32) data[1]) << 0));
	bw32(bp, B44_CAM_DATA_HI, val);
	bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
			    (index << CAM_CTRL_INDEX_SHIFT)));
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	b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
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}

static inline void __b44_disable_ints(struct b44 *bp)
{
	bw32(bp, B44_IMASK, 0);
}

static void b44_disable_ints(struct b44 *bp)
{
	__b44_disable_ints(bp);

	/* Flush posted writes. */
	br32(bp, B44_IMASK);
}

static void b44_enable_ints(struct b44 *bp)
{
	bw32(bp, B44_IMASK, bp->imask);
}

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static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
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{
	int err;

	bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
	bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
			     (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
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			     (phy_addr << MDIO_DATA_PMD_SHIFT) |
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			     (reg << MDIO_DATA_RA_SHIFT) |
			     (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
	err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
	*val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;

	return err;
}

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static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
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{
	bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
	bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
			     (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
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			     (phy_addr << MDIO_DATA_PMD_SHIFT) |
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			     (reg << MDIO_DATA_RA_SHIFT) |
			     (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
			     (val & MDIO_DATA_DATA)));
	return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
}

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static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
{
	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
		return 0;

	return __b44_readphy(bp, bp->phy_addr, reg, val);
}

static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
{
	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
		return 0;

	return __b44_writephy(bp, bp->phy_addr, reg, val);
}

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/* miilib interface */
static int b44_mii_read(struct net_device *dev, int phy_id, int location)
{
	u32 val;
	struct b44 *bp = netdev_priv(dev);
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	int rc = __b44_readphy(bp, phy_id, location, &val);
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	if (rc)
		return 0xffffffff;
	return val;
}

static void b44_mii_write(struct net_device *dev, int phy_id, int location,
			 int val)
{
	struct b44 *bp = netdev_priv(dev);
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	__b44_writephy(bp, phy_id, location, val);
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}

static int b44_phy_reset(struct b44 *bp)
{
	u32 val;
	int err;

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	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
		return 0;
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	err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
	if (err)
		return err;
	udelay(100);
	err = b44_readphy(bp, MII_BMCR, &val);
	if (!err) {
		if (val & BMCR_RESET) {
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			netdev_err(bp->dev, "PHY Reset would not complete\n");
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			err = -ENODEV;
		}
	}

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	return err;
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}

static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
{
	u32 val;

	bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
	bp->flags |= pause_flags;

	val = br32(bp, B44_RXCONFIG);
	if (pause_flags & B44_FLAG_RX_PAUSE)
		val |= RXCONFIG_FLOW;
	else
		val &= ~RXCONFIG_FLOW;
	bw32(bp, B44_RXCONFIG, val);

	val = br32(bp, B44_MAC_FLOW);
	if (pause_flags & B44_FLAG_TX_PAUSE)
		val |= (MAC_FLOW_PAUSE_ENAB |
			(0xc0 & MAC_FLOW_RX_HI_WATER));
	else
		val &= ~MAC_FLOW_PAUSE_ENAB;
	bw32(bp, B44_MAC_FLOW, val);
}

static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
{
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	u32 pause_enab = 0;
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	/* The driver supports only rx pause by default because
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	   the b44 mac tx pause mechanism generates excessive
	   pause frames.
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	   Use ethtool to turn on b44 tx pause if necessary.
	 */
	if ((local & ADVERTISE_PAUSE_CAP) &&
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	    (local & ADVERTISE_PAUSE_ASYM)){
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		if ((remote & LPA_PAUSE_ASYM) &&
		    !(remote & LPA_PAUSE_CAP))
			pause_enab |= B44_FLAG_RX_PAUSE;
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	}

	__b44_set_flow_ctrl(bp, pause_enab);
}

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#ifdef CONFIG_BCM47XX
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#include <bcm47xx_nvram.h>
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static void b44_wap54g10_workaround(struct b44 *bp)
{
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	char buf[20];
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	u32 val;
	int err;

	/*
	 * workaround for bad hardware design in Linksys WAP54G v1.0
	 * see https://dev.openwrt.org/ticket/146
	 * check and reset bit "isolate"
	 */
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	if (bcm47xx_nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
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		return;
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	if (simple_strtoul(buf, NULL, 0) == 2) {
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		err = __b44_readphy(bp, 0, MII_BMCR, &val);
		if (err)
			goto error;
		if (!(val & BMCR_ISOLATE))
			return;
		val &= ~BMCR_ISOLATE;
		err = __b44_writephy(bp, 0, MII_BMCR, val);
		if (err)
			goto error;
	}
	return;
error:
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	pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
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}
#else
static inline void b44_wap54g10_workaround(struct b44 *bp)
{
}
#endif

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static int b44_setup_phy(struct b44 *bp)
{
	u32 val;
	int err;

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	b44_wap54g10_workaround(bp);

	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
		return 0;
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	if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
		goto out;
	if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
				val & MII_ALEDCTRL_ALLMSK)) != 0)
		goto out;
	if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
		goto out;
	if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
				val | MII_TLEDCTRL_ENABLE)) != 0)
		goto out;

	if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
		u32 adv = ADVERTISE_CSMA;

		if (bp->flags & B44_FLAG_ADV_10HALF)
			adv |= ADVERTISE_10HALF;
		if (bp->flags & B44_FLAG_ADV_10FULL)
			adv |= ADVERTISE_10FULL;
		if (bp->flags & B44_FLAG_ADV_100HALF)
			adv |= ADVERTISE_100HALF;
		if (bp->flags & B44_FLAG_ADV_100FULL)
			adv |= ADVERTISE_100FULL;

		if (bp->flags & B44_FLAG_PAUSE_AUTO)
			adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;

		if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
			goto out;
		if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
						       BMCR_ANRESTART))) != 0)
			goto out;
	} else {
		u32 bmcr;

		if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
			goto out;
		bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
		if (bp->flags & B44_FLAG_100_BASE_T)
			bmcr |= BMCR_SPEED100;
		if (bp->flags & B44_FLAG_FULL_DUPLEX)
			bmcr |= BMCR_FULLDPLX;
		if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
			goto out;

		/* Since we will not be negotiating there is no safe way
		 * to determine if the link partner supports flow control
		 * or not.  So just disable it completely in this case.
		 */
		b44_set_flow_ctrl(bp, 0, 0);
	}

out:
	return err;
}

static void b44_stats_update(struct b44 *bp)
{
	unsigned long reg;
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	u64 *val;
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	val = &bp->hw_stats.tx_good_octets;
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	u64_stats_update_begin(&bp->hw_stats.syncp);

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	for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
		*val++ += br32(bp, reg);
	}
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	/* Pad */
	reg += 8*4UL;

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	for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
		*val++ += br32(bp, reg);
	}
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	u64_stats_update_end(&bp->hw_stats.syncp);
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}

static void b44_link_report(struct b44 *bp)
{
	if (!netif_carrier_ok(bp->dev)) {
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		netdev_info(bp->dev, "Link is down\n");
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	} else {
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		netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
			    (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
			    (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");

		netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
			    (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
			    (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
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	}
}

static void b44_check_phy(struct b44 *bp)
{
	u32 bmsr, aux;

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	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
		bp->flags |= B44_FLAG_100_BASE_T;
		bp->flags |= B44_FLAG_FULL_DUPLEX;
		if (!netif_carrier_ok(bp->dev)) {
			u32 val = br32(bp, B44_TX_CTRL);
			val |= TX_CTRL_DUPLEX;
			bw32(bp, B44_TX_CTRL, val);
			netif_carrier_on(bp->dev);
			b44_link_report(bp);
		}
		return;
	}

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	if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
	    !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
	    (bmsr != 0xffff)) {
		if (aux & MII_AUXCTRL_SPEED)
			bp->flags |= B44_FLAG_100_BASE_T;
		else
			bp->flags &= ~B44_FLAG_100_BASE_T;
		if (aux & MII_AUXCTRL_DUPLEX)
			bp->flags |= B44_FLAG_FULL_DUPLEX;
		else
			bp->flags &= ~B44_FLAG_FULL_DUPLEX;

		if (!netif_carrier_ok(bp->dev) &&
		    (bmsr & BMSR_LSTATUS)) {
			u32 val = br32(bp, B44_TX_CTRL);
			u32 local_adv, remote_adv;

			if (bp->flags & B44_FLAG_FULL_DUPLEX)
				val |= TX_CTRL_DUPLEX;
			else
				val &= ~TX_CTRL_DUPLEX;
			bw32(bp, B44_TX_CTRL, val);

			if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
			    !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
			    !b44_readphy(bp, MII_LPA, &remote_adv))
				b44_set_flow_ctrl(bp, local_adv, remote_adv);

			/* Link now up */
			netif_carrier_on(bp->dev);
			b44_link_report(bp);
		} else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
			/* Link now down */
			netif_carrier_off(bp->dev);
			b44_link_report(bp);
		}

		if (bmsr & BMSR_RFAULT)
575
			netdev_warn(bp->dev, "Remote fault detected in PHY\n");
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		if (bmsr & BMSR_JCD)
577
			netdev_warn(bp->dev, "Jabber detected in PHY\n");
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	}
}

static void b44_timer(unsigned long __opaque)
{
	struct b44 *bp = (struct b44 *) __opaque;

	spin_lock_irq(&bp->lock);

	b44_check_phy(bp);

	b44_stats_update(bp);

	spin_unlock_irq(&bp->lock);

593
	mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
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}

static void b44_tx(struct b44 *bp)
{
	u32 cur, cons;

	cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
	cur /= sizeof(struct dma_desc);

	/* XXX needs updating when NETIF_F_SG is supported */
	for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
		struct ring_info *rp = &bp->tx_buffers[cons];
		struct sk_buff *skb = rp->skb;

608
		BUG_ON(skb == NULL);
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610 611 612 613
		dma_unmap_single(bp->sdev->dma_dev,
				 rp->mapping,
				 skb->len,
				 DMA_TO_DEVICE);
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		rp->skb = NULL;
615
		dev_kfree_skb_irq(skb);
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	}

	bp->tx_cons = cons;
	if (netif_queue_stopped(bp->dev) &&
	    TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
		netif_wake_queue(bp->dev);

	bw32(bp, B44_GPTIMER, 0);
}

/* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 * before the DMA address you give it.  So we allocate 30 more bytes
 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 * point the chip at 30 bytes past where the rx_header will go.
 */
static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
{
	struct dma_desc *dp;
	struct ring_info *src_map, *map;
	struct rx_header *rh;
	struct sk_buff *skb;
	dma_addr_t mapping;
	int dest_idx;
	u32 ctrl;

	src_map = NULL;
	if (src_idx >= 0)
		src_map = &bp->rx_buffers[src_idx];
	dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
	map = &bp->rx_buffers[dest_idx];
646
	skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
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	if (skb == NULL)
		return -ENOMEM;

650 651 652
	mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
				 RX_PKT_BUF_SZ,
				 DMA_FROM_DEVICE);
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	/* Hardware bug work-around, the chip is unable to do PCI DMA
	   to/from anything above 1GB :-( */
656
	if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
657
		mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
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		/* Sigh... */
659 660
		if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
			dma_unmap_single(bp->sdev->dma_dev, mapping,
661
					     RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
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		dev_kfree_skb_any(skb);
663
		skb = alloc_skb(RX_PKT_BUF_SZ, GFP_ATOMIC | GFP_DMA);
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		if (skb == NULL)
			return -ENOMEM;
666 667 668 669 670 671 672
		mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
					 RX_PKT_BUF_SZ,
					 DMA_FROM_DEVICE);
		if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
		    mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
			if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
				dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
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			dev_kfree_skb_any(skb);
			return -ENOMEM;
		}
676
		bp->force_copybreak = 1;
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	}

679
	rh = (struct rx_header *) skb->data;
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	rh->len = 0;
	rh->flags = 0;

	map->skb = skb;
685
	map->mapping = mapping;
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	if (src_map != NULL)
		src_map->skb = NULL;

690
	ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
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	if (dest_idx == (B44_RX_RING_SIZE - 1))
		ctrl |= DESC_CTRL_EOT;

	dp = &bp->rx_ring[dest_idx];
	dp->ctrl = cpu_to_le32(ctrl);
696
	dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
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698
	if (bp->flags & B44_FLAG_RX_RING_HACK)
699
		b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
700
			                    dest_idx * sizeof(*dp),
701
			                    DMA_BIDIRECTIONAL);
702

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	return RX_PKT_BUF_SZ;
}

static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
{
	struct dma_desc *src_desc, *dest_desc;
	struct ring_info *src_map, *dest_map;
	struct rx_header *rh;
	int dest_idx;
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	__le32 ctrl;
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	dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
	dest_desc = &bp->rx_ring[dest_idx];
	dest_map = &bp->rx_buffers[dest_idx];
	src_desc = &bp->rx_ring[src_idx];
	src_map = &bp->rx_buffers[src_idx];

	dest_map->skb = src_map->skb;
	rh = (struct rx_header *) src_map->skb->data;
	rh->len = 0;
	rh->flags = 0;
724
	dest_map->mapping = src_map->mapping;
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726
	if (bp->flags & B44_FLAG_RX_RING_HACK)
727
		b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
728
			                 src_idx * sizeof(*src_desc),
729
			                 DMA_BIDIRECTIONAL);
730

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	ctrl = src_desc->ctrl;
	if (dest_idx == (B44_RX_RING_SIZE - 1))
		ctrl |= cpu_to_le32(DESC_CTRL_EOT);
	else
		ctrl &= cpu_to_le32(~DESC_CTRL_EOT);

	dest_desc->ctrl = ctrl;
	dest_desc->addr = src_desc->addr;
739

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	src_map->skb = NULL;

742
	if (bp->flags & B44_FLAG_RX_RING_HACK)
743
		b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
744
					     dest_idx * sizeof(*dest_desc),
745
					     DMA_BIDIRECTIONAL);
746

747 748 749
	dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
				   RX_PKT_BUF_SZ,
				   DMA_FROM_DEVICE);
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}

static int b44_rx(struct b44 *bp, int budget)
{
	int received;
	u32 cons, prod;

	received = 0;
	prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
	prod /= sizeof(struct dma_desc);
	cons = bp->rx_cons;

	while (cons != prod && budget > 0) {
		struct ring_info *rp = &bp->rx_buffers[cons];
		struct sk_buff *skb = rp->skb;
765
		dma_addr_t map = rp->mapping;
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		struct rx_header *rh;
		u16 len;

769 770 771
		dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
					RX_PKT_BUF_SZ,
					DMA_FROM_DEVICE);
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		rh = (struct rx_header *) skb->data;
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		len = le16_to_cpu(rh->len);
774
		if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
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		    (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
		drop_it:
			b44_recycle_rx(bp, cons, bp->rx_prod);
		drop_it_no_recycle:
779
			bp->dev->stats.rx_dropped++;
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			goto next_pkt;
		}

		if (len == 0) {
			int i = 0;

			do {
				udelay(2);
				barrier();
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				len = le16_to_cpu(rh->len);
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			} while (len == 0 && i++ < 5);
			if (len == 0)
				goto drop_it;
		}

		/* Omit CRC. */
		len -= 4;

798
		if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
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			int skb_size;
			skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
			if (skb_size < 0)
				goto drop_it;
803 804
			dma_unmap_single(bp->sdev->dma_dev, map,
					 skb_size, DMA_FROM_DEVICE);
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			/* Leave out rx_header */
806 807
			skb_put(skb, len + RX_PKT_OFFSET);
			skb_pull(skb, RX_PKT_OFFSET);
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		} else {
			struct sk_buff *copy_skb;

			b44_recycle_rx(bp, cons, bp->rx_prod);
812
			copy_skb = netdev_alloc_skb_ip_align(bp->dev, len);
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			if (copy_skb == NULL)
				goto drop_it_no_recycle;

			skb_put(copy_skb, len);
			/* DMA sync done above, copy just the actual packet */
818
			skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
819
							 copy_skb->data, len);
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			skb = copy_skb;
		}
822
		skb_checksum_none_assert(skb);
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		skb->protocol = eth_type_trans(skb, bp->dev);
		netif_receive_skb(skb);
		received++;
		budget--;
	next_pkt:
		bp->rx_prod = (bp->rx_prod + 1) &
			(B44_RX_RING_SIZE - 1);
		cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
	}

	bp->rx_cons = cons;
	bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));

	return received;
}

839
static int b44_poll(struct napi_struct *napi, int budget)
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{
841 842
	struct b44 *bp = container_of(napi, struct b44, napi);
	int work_done;
843
	unsigned long flags;
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844

845
	spin_lock_irqsave(&bp->lock, flags);
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	if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
		/* spin_lock(&bp->tx_lock); */
		b44_tx(bp);
		/* spin_unlock(&bp->tx_lock); */
	}
852 853 854 855 856 857 858 859 860
	if (bp->istat & ISTAT_RFO) {	/* fast recovery, in ~20msec */
		bp->istat &= ~ISTAT_RFO;
		b44_disable_ints(bp);
		ssb_device_enable(bp->sdev, 0); /* resets ISTAT_RFO */
		b44_init_rings(bp);
		b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
		netif_wake_queue(bp->dev);
	}

861
	spin_unlock_irqrestore(&bp->lock, flags);
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863 864 865
	work_done = 0;
	if (bp->istat & ISTAT_RX)
		work_done += b44_rx(bp, budget);
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	if (bp->istat & ISTAT_ERRORS) {
868
		spin_lock_irqsave(&bp->lock, flags);
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		b44_halt(bp);
		b44_init_rings(bp);
871
		b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
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		netif_wake_queue(bp->dev);
873
		spin_unlock_irqrestore(&bp->lock, flags);
874
		work_done = 0;
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	}

877
	if (work_done < budget) {
878
		napi_complete(napi);
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		b44_enable_ints(bp);
	}

882
	return work_done;
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}

885
static irqreturn_t b44_interrupt(int irq, void *dev_id)
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{
	struct net_device *dev = dev_id;
	struct b44 *bp = netdev_priv(dev);
	u32 istat, imask;
	int handled = 0;

892
	spin_lock(&bp->lock);
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	istat = br32(bp, B44_ISTAT);
	imask = br32(bp, B44_IMASK);

897 898 899
	/* The interrupt mask register controls which interrupt bits
	 * will actually raise an interrupt to the CPU when set by hw/firmware,
	 * but doesn't mask off the bits.
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	 */
	istat &= imask;
	if (istat) {
		handled = 1;
904 905

		if (unlikely(!netif_running(dev))) {
906
			netdev_info(dev, "late interrupt\n");
907 908 909
			goto irq_ack;
		}

910
		if (napi_schedule_prep(&bp->napi)) {
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			/* NOTE: These writes are posted by the readback of
			 *       the ISTAT register below.
			 */
			bp->istat = istat;
			__b44_disable_ints(bp);
916
			__napi_schedule(&bp->napi);
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917 918
		}

919
irq_ack:
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		bw32(bp, B44_ISTAT, istat);
		br32(bp, B44_ISTAT);
	}
923
	spin_unlock(&bp->lock);
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	return IRQ_RETVAL(handled);
}

static void b44_tx_timeout(struct net_device *dev)
{
	struct b44 *bp = netdev_priv(dev);

931
	netdev_err(dev, "transmit timed out, resetting\n");
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	spin_lock_irq(&bp->lock);

	b44_halt(bp);
	b44_init_rings(bp);
937
	b44_init_hw(bp, B44_FULL_RESET);
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	spin_unlock_irq(&bp->lock);

	b44_enable_ints(bp);

	netif_wake_queue(dev);
}

946
static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
	struct b44 *bp = netdev_priv(dev);
949
	int rc = NETDEV_TX_OK;
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	dma_addr_t mapping;
	u32 len, entry, ctrl;
952
	unsigned long flags;
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	len = skb->len;
955
	spin_lock_irqsave(&bp->lock, flags);
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	/* This is a hard error, log it. */
	if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
		netif_stop_queue(dev);
960
		netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
961
		goto err_out;
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	}

964 965
	mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
	if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
966 967
		struct sk_buff *bounce_skb;

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		/* Chip can't handle DMA to/from >1GB, use bounce buffer */
969 970
		if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
			dma_unmap_single(bp->sdev->dma_dev, mapping, len,
971
					     DMA_TO_DEVICE);
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973
		bounce_skb = alloc_skb(len, GFP_ATOMIC | GFP_DMA);
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		if (!bounce_skb)
975
			goto err_out;
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977 978 979 980 981
		mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
					 len, DMA_TO_DEVICE);
		if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
			if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
				dma_unmap_single(bp->sdev->dma_dev, mapping,
982
						     len, DMA_TO_DEVICE);
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			dev_kfree_skb_any(bounce_skb);
984
			goto err_out;
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		}

987
		skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
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		dev_kfree_skb_any(skb);
		skb = bounce_skb;
	}

	entry = bp->tx_prod;
	bp->tx_buffers[entry].skb = skb;
994
	bp->tx_buffers[entry].mapping = mapping;
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	ctrl  = (len & DESC_CTRL_LEN);
	ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
	if (entry == (B44_TX_RING_SIZE - 1))
		ctrl |= DESC_CTRL_EOT;

	bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
	bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);

1004
	if (bp->flags & B44_FLAG_TX_RING_HACK)
1005 1006 1007
		b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
			                    entry * sizeof(bp->tx_ring[0]),
			                    DMA_TO_DEVICE);
1008

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	entry = NEXT_TX(entry);

	bp->tx_prod = entry;

	wmb();

	bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
	if (bp->flags & B44_FLAG_BUGGY_TXPTR)
		bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
	if (bp->flags & B44_FLAG_REORDER_BUG)
		br32(bp, B44_DMATX_PTR);

	if (TX_BUFFS_AVAIL(bp) < 1)
		netif_stop_queue(dev);

1024
out_unlock:
1025
	spin_unlock_irqrestore(&bp->lock, flags);
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1027
	return rc;
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1029 1030 1031
err_out:
	rc = NETDEV_TX_BUSY;
	goto out_unlock;
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}

static int b44_change_mtu(struct net_device *dev, int new_mtu)
{
	struct b44 *bp = netdev_priv(dev);

	if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
		return -EINVAL;

	if (!netif_running(dev)) {
		/* We'll just catch it later when the
		 * device is up'd.
		 */
		dev->mtu = new_mtu;
		return 0;
	}

	spin_lock_irq(&bp->lock);
	b44_halt(bp);
	dev->mtu = new_mtu;
	b44_init_rings(bp);
1053
	b44_init_hw(bp, B44_FULL_RESET);
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	spin_unlock_irq(&bp->lock);

	b44_enable_ints(bp);
1057

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	return 0;
}

/* Free up pending packets in all rx/tx rings.
 *
 * The chip has been shut down and the driver detached from
 * the networking, so no interrupts or new tx packets will
 * end up in the driver.  bp->lock is not held and we are not
 * in an interrupt context and thus may sleep.
 */
static void b44_free_rings(struct b44 *bp)
{
	struct ring_info *rp;
	int i;

	for (i = 0; i < B44_RX_RING_SIZE; i++) {
		rp = &bp->rx_buffers[i];

		if (rp->skb == NULL)
			continue;
1078 1079
		dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
				 DMA_FROM_DEVICE);
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		dev_kfree_skb_any(rp->skb);
		rp->skb = NULL;
	}

	/* XXX needs changes once NETIF_F_SG is set... */
	for (i = 0; i < B44_TX_RING_SIZE; i++) {
		rp = &bp->tx_buffers[i];

		if (rp->skb == NULL)
			continue;
1090 1091
		dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
				 DMA_TO_DEVICE);
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		dev_kfree_skb_any(rp->skb);
		rp->skb = NULL;
	}
}

/* Initialize tx/rx rings for packet processing.
 *
 * The chip has been shut down and the driver detached from
 * the networking, so no interrupts or new tx packets will
1101
 * end up in the driver.
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 */
static void b44_init_rings(struct b44 *bp)
{
	int i;

	b44_free_rings(bp);

	memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
	memset(bp->tx_ring, 0, B44_TX_RING_BYTES);

1112
	if (bp->flags & B44_FLAG_RX_RING_HACK)
1113 1114
		dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
					   DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1115 1116

	if (bp->flags & B44_FLAG_TX_RING_HACK)
1117 1118
		dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
					   DMA_TABLE_BYTES, DMA_TO_DEVICE);
1119

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	for (i = 0; i < bp->rx_pending; i++) {
		if (b44_alloc_rx_skb(bp, -1, i) < 0)
			break;
	}
}

/*
 * Must not be invoked with interrupt sources disabled and
 * the hardware shutdown down.
 */
static void b44_free_consistent(struct b44 *bp)
{
1132 1133 1134 1135
	kfree(bp->rx_buffers);
	bp->rx_buffers = NULL;
	kfree(bp->tx_buffers);
	bp->tx_buffers = NULL;
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	if (bp->rx_ring) {
1137
		if (bp->flags & B44_FLAG_RX_RING_HACK) {
1138 1139
			dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
					 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1140 1141
			kfree(bp->rx_ring);
		} else
1142 1143
			dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
					  bp->rx_ring, bp->rx_ring_dma);
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		bp->rx_ring = NULL;
1145
		bp->flags &= ~B44_FLAG_RX_RING_HACK;
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	}
	if (bp->tx_ring) {
1148
		if (bp->flags & B44_FLAG_TX_RING_HACK) {
1149 1150
			dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
					 DMA_TABLE_BYTES, DMA_TO_DEVICE);
1151 1152
			kfree(bp->tx_ring);
		} else
1153 1154
			dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
					  bp->tx_ring, bp->tx_ring_dma);
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		bp->tx_ring = NULL;
1156
		bp->flags &= ~B44_FLAG_TX_RING_HACK;
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	}
}

/*
 * Must not be invoked with interrupt sources disabled and
 * the hardware shutdown down.  Can sleep.
 */
1164
static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
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{
	int size;

	size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1169
	bp->rx_buffers = kzalloc(size, gfp);
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	if (!bp->rx_buffers)
		goto out_err;

	size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1174
	bp->tx_buffers = kzalloc(size, gfp);
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	if (!bp->tx_buffers)
		goto out_err;

	size = DMA_TABLE_BYTES;
1179 1180
	bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
					 &bp->rx_ring_dma, gfp);
1181 1182 1183 1184 1185 1186 1187
	if (!bp->rx_ring) {
		/* Allocation may have failed due to pci_alloc_consistent
		   insisting on use of GFP_DMA, which is more restrictive
		   than necessary...  */
		struct dma_desc *rx_ring;
		dma_addr_t rx_ring_dma;

1188
		rx_ring = kzalloc(size, gfp);
1189
		if (!rx_ring)
1190 1191
			goto out_err;

1192 1193 1194
		rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
					     DMA_TABLE_BYTES,
					     DMA_BIDIRECTIONAL);
1195

1196
		if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
1197
			rx_ring_dma + size > DMA_BIT_MASK(30)) {
1198 1199 1200 1201 1202 1203 1204 1205
			kfree(rx_ring);
			goto out_err;
		}

		bp->rx_ring = rx_ring;
		bp->rx_ring_dma = rx_ring_dma;
		bp->flags |= B44_FLAG_RX_RING_HACK;
	}
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1207 1208
	bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
					 &bp->tx_ring_dma, gfp);
1209
	if (!bp->tx_ring) {
1210
		/* Allocation may have failed due to ssb_dma_alloc_consistent
1211 1212 1213 1214 1215
		   insisting on use of GFP_DMA, which is more restrictive
		   than necessary...  */
		struct dma_desc *tx_ring;
		dma_addr_t tx_ring_dma;

1216
		tx_ring = kzalloc(size, gfp);
1217
		if (!tx_ring)
1218 1219
			goto out_err;

1220 1221 1222
		tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
					     DMA_TABLE_BYTES,
					     DMA_TO_DEVICE);
1223

1224
		if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
1225
			tx_ring_dma + size > DMA_BIT_MASK(30)) {
1226 1227 1228 1229 1230 1231 1232 1233
			kfree(tx_ring);
			goto out_err;
		}

		bp->tx_ring = tx_ring;
		bp->tx_ring_dma = tx_ring_dma;
		bp->flags |= B44_FLAG_TX_RING_HACK;
	}
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1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254

	return 0;

out_err:
	b44_free_consistent(bp);
	return -ENOMEM;
}

/* bp->lock is held. */
static void b44_clear_stats(struct b44 *bp)
{
	unsigned long reg;

	bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
	for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
		br32(bp, reg);
	for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
		br32(bp, reg);
}

/* bp->lock is held. */
1255
static void b44_chip_reset(struct b44 *bp, int reset_kind)
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{
1257
	struct ssb_device *sdev = bp->sdev;
1258
	bool was_enabled;
1259

1260 1261 1262 1263 1264 1265
	was_enabled = ssb_device_is_enabled(bp->sdev);

	ssb_device_enable(bp->sdev, 0);
	ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);

	if (was_enabled) {
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		bw32(bp, B44_RCV_LAZY, 0);
		bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
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		b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
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		bw32(bp, B44_DMATX_CTRL, 0);
		bp->tx_prod = bp->tx_cons = 0;
		if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
			b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
				     100, 0);
		}
		bw32(bp, B44_DMARX_CTRL, 0);
		bp->rx_prod = bp->rx_cons = 0;
1277
	}
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	b44_clear_stats(bp);

1281 1282 1283 1284 1285 1286 1287
	/*
	 * Don't enable PHY if we are doing a partial reset
	 * we are probably going to power down
	 */
	if (reset_kind == B44_CHIP_RESET_PARTIAL)
		return;

1288 1289 1290
	switch (sdev->bus->bustype) {
	case SSB_BUSTYPE_SSB:
		bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1291 1292
		     (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
					B44_MDC_RATIO)
1293 1294 1295 1296 1297 1298
		     & MDIO_CTRL_MAXF_MASK)));
		break;
	case SSB_BUSTYPE_PCI:
		bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
		     (0x0d & MDIO_CTRL_MAXF_MASK)));
		break;
1299 1300 1301 1302
	case SSB_BUSTYPE_PCMCIA:
	case SSB_BUSTYPE_SDIO:
		WARN_ON(1); /* A device with this bus does not exist. */
		break;
1303 1304
	}

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	br32(bp, B44_MDIO_CTRL);

	if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
		bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
		br32(bp, B44_ENET_CTRL);
		bp->flags &= ~B44_FLAG_INTERNAL_PHY;
	} else {
		u32 val = br32(bp, B44_DEVCTRL);

		if (val & DEVCTRL_EPR) {
			bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
			br32(bp, B44_DEVCTRL);
			udelay(100);
		}
		bp->flags |= B44_FLAG_INTERNAL_PHY;
	}
}

/* bp->lock is held. */
static void b44_halt(struct b44 *bp)
{
	b44_disable_ints(bp);
1327 1328 1329
	/* reset PHY */
	b44_phy_reset(bp);
	/* power down PHY */
1330
	netdev_info(bp->dev, "powering down PHY\n");
1331 1332 1333 1334
	bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
	/* now reset the chip, but without enabling the MAC&PHY
	 * part of it. This has to be done _after_ we shut down the PHY */
	b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
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}

/* bp->lock is held. */
static void __b44_set_mac_addr(struct b44 *bp)
{
	bw32(bp, B44_CAM_CTRL, 0);
	if (!(bp->dev->flags & IFF_PROMISC)) {
		u32 val;

		__b44_cam_write(bp, bp->dev->dev_addr, 0);
		val = br32(bp, B44_CAM_CTRL);
		bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
	}
}

static int b44_set_mac_addr(struct net_device *dev, void *p)
{
	struct b44 *bp = netdev_priv(dev);
	struct sockaddr *addr = p;
1354
	u32 val;
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	if (netif_running(dev))
		return -EBUSY;

1359 1360 1361
	if (!is_valid_ether_addr(addr->sa_data))
		return -EINVAL;

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	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);

	spin_lock_irq(&bp->lock);
1365 1366 1367 1368 1369

	val = br32(bp, B44_RXCONFIG);
	if (!(val & RXCONFIG_CAM_ABSENT))
		__b44_set_mac_addr(bp);

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	spin_unlock_irq(&bp->lock);

	return 0;
}

/* Called at device open time to get the chip ready for
 * packet processing.  Invoked with bp->lock held.
 */
static void __b44_set_rx_mode(struct net_device *);
1379
static void b44_init_hw(struct b44 *bp, int reset_kind)
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{
	u32 val;

1383
	b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1384
	if (reset_kind == B44_FULL_RESET) {
1385 1386 1387
		b44_phy_reset(bp);
		b44_setup_phy(bp);
	}
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	/* Enable CRC32, set proper LED modes and power on PHY */
	bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
	bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));

	/* This sets the MAC address too.  */
	__b44_set_rx_mode(bp->dev);

	/* MTU + eth header + possible VLAN tag + struct rx_header */
	bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
	bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);

	bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1401 1402
	if (reset_kind == B44_PARTIAL_RESET) {
		bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1403
				      (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1404
	} else {
1405 1406 1407
		bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
		bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
		bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1408
				      (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1409
		bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
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1411 1412
		bw32(bp, B44_DMARX_PTR, bp->rx_pending);
		bp->rx_prod = bp->rx_pending;
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1414 1415
		bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
	}
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1416 1417 1418 1419 1420 1421 1422 1423 1424 1425

	val = br32(bp, B44_ENET_CTRL);
	bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
}

static int b44_open(struct net_device *dev)
{
	struct b44 *bp = netdev_priv(dev);
	int err;

1426
	err = b44_alloc_consistent(bp, GFP_KERNEL);
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	if (err)
1428
		goto out;
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1429

1430 1431
	napi_enable(&bp->napi);

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	b44_init_rings(bp);
1433
	b44_init_hw(bp, B44_FULL_RESET);
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1435 1436
	b44_check_phy(bp);

1437
	err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1438
	if (unlikely(err < 0)) {
1439
		napi_disable(&bp->napi);
1440
		b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1441 1442 1443 1444
		b44_free_rings(bp);
		b44_free_consistent(bp);
		goto out;
	}
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1445 1446 1447 1448 1449 1450 1451 1452

	init_timer(&bp->timer);
	bp->timer.expires = jiffies + HZ;
	bp->timer.data = (unsigned long) bp;
	bp->timer.function = b44_timer;
	add_timer(&bp->timer);

	b44_enable_ints(bp);
1453
	netif_start_queue(dev);
1454
out:
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	return err;
}

#ifdef CONFIG_NET_POLL_CONTROLLER
/*
 * Polling receive - used by netconsole and other diagnostic tools
 * to allow network i/o with interrupts disabled.
 */
static void b44_poll_controller(struct net_device *dev)
{
	disable_irq(dev->irq);
1466
	b44_interrupt(dev->irq, dev);
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	enable_irq(dev->irq);
}
#endif

1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
{
	u32 i;
	u32 *pattern = (u32 *) pp;

	for (i = 0; i < bytes; i += sizeof(u32)) {
		bw32(bp, B44_FILT_ADDR, table_offset + i);
		bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
	}
}

static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
{
	int magicsync = 6;
	int k, j, len = offset;
	int ethaddr_bytes = ETH_ALEN;

	memset(ppattern + offset, 0xff, magicsync);
	for (j = 0; j < magicsync; j++)
		set_bit(len++, (unsigned long *) pmask);

	for (j = 0; j < B44_MAX_PATTERNS; j++) {
		if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
			ethaddr_bytes = ETH_ALEN;
		else
			ethaddr_bytes = B44_PATTERN_SIZE - len;
		if (ethaddr_bytes <=0)
			break;
		for (k = 0; k< ethaddr_bytes; k++) {
			ppattern[offset + magicsync +
				(j * ETH_ALEN) + k] = macaddr[k];
1502
			set_bit(len++, (unsigned long *) pmask);
1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518
		}
	}
	return len - 1;
}

/* Setup magic packet patterns in the b44 WOL
 * pattern matching filter.
 */
static void b44_setup_pseudo_magicp(struct b44 *bp)
{

	u32 val;
	int plen0, plen1, plen2;
	u8 *pwol_pattern;
	u8 pwol_mask[B44_PMASK_SIZE];

1519
	pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1520
	if (!pwol_pattern)
1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563
		return;

	/* Ipv4 magic packet pattern - pattern 0.*/
	memset(pwol_mask, 0, B44_PMASK_SIZE);
	plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
				  B44_ETHIPV4UDP_HLEN);

   	bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
   	bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);

	/* Raw ethernet II magic packet pattern - pattern 1 */
	memset(pwol_pattern, 0, B44_PATTERN_SIZE);
	memset(pwol_mask, 0, B44_PMASK_SIZE);
	plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
				  ETH_HLEN);

   	bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
		       B44_PATTERN_BASE + B44_PATTERN_SIZE);
  	bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
		       B44_PMASK_BASE + B44_PMASK_SIZE);

	/* Ipv6 magic packet pattern - pattern 2 */
	memset(pwol_pattern, 0, B44_PATTERN_SIZE);
	memset(pwol_mask, 0, B44_PMASK_SIZE);
	plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
				  B44_ETHIPV6UDP_HLEN);

   	bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
		       B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
  	bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
		       B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);

	kfree(pwol_pattern);

	/* set these pattern's lengths: one less than each real length */
	val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
	bw32(bp, B44_WKUP_LEN, val);

	/* enable wakeup pattern matching */
	val = br32(bp, B44_DEVCTRL);
	bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);

}
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1564

1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579
#ifdef CONFIG_B44_PCI
static void b44_setup_wol_pci(struct b44 *bp)
{
	u16 val;

	if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
		bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
		pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
		pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
	}
}
#else
static inline void b44_setup_wol_pci(struct b44 *bp) { }
#endif /* CONFIG_B44_PCI */

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static void b44_setup_wol(struct b44 *bp)
{
	u32 val;

	bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);

	if (bp->flags & B44_FLAG_B0_ANDLATER) {

		bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);

		val = bp->dev->dev_addr[2] << 24 |
			bp->dev->dev_addr[3] << 16 |
			bp->dev->dev_addr[4] << 8 |
			bp->dev->dev_addr[5];
		bw32(bp, B44_ADDR_LO, val);

		val = bp->dev->dev_addr[0] << 8 |
			bp->dev->dev_addr[1];
		bw32(bp, B44_ADDR_HI, val);

		val = br32(bp, B44_DEVCTRL);
		bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);

1603 1604 1605
 	} else {
 		b44_setup_pseudo_magicp(bp);
 	}
1606
	b44_setup_wol_pci(bp);
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}

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static int b44_close(struct net_device *dev)
{
	struct b44 *bp = netdev_priv(dev);

	netif_stop_queue(dev);

1615
	napi_disable(&bp->napi);
1616

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	del_timer_sync(&bp->timer);

	spin_lock_irq(&bp->lock);

	b44_halt(bp);
	b44_free_rings(bp);
1623
	netif_carrier_off(dev);
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	spin_unlock_irq(&bp->lock);

	free_irq(dev->irq, dev);

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	if (bp->flags & B44_FLAG_WOL_ENABLE) {
1630
		b44_init_hw(bp, B44_PARTIAL_RESET);
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		b44_setup_wol(bp);
	}

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	b44_free_consistent(bp);

	return 0;
}

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static struct rtnl_link_stats64 *b44_get_stats64(struct net_device *dev,
					struct rtnl_link_stats64 *nstat)
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{
	struct b44 *bp = netdev_priv(dev);
	struct b44_hw_stats *hwstat = &bp->hw_stats;
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	unsigned int start;

	do {
		start = u64_stats_fetch_begin_bh(&hwstat->syncp);

		/* Convert HW stats into rtnl_link_stats64 stats. */
		nstat->rx_packets = hwstat->rx_pkts;
		nstat->tx_packets = hwstat->tx_pkts;
		nstat->rx_bytes   = hwstat->rx_octets;
		nstat->tx_bytes   = hwstat->tx_octets;
		nstat->tx_errors  = (hwstat->tx_jabber_pkts +
				     hwstat->tx_oversize_pkts +
				     hwstat->tx_underruns +
				     hwstat->tx_excessive_cols +
				     hwstat->tx_late_cols);
		nstat->multicast  = hwstat->tx_multicast_pkts;
		nstat->collisions = hwstat->tx_total_cols;

		nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
					   hwstat->rx_undersize);
		nstat->rx_over_errors   = hwstat->rx_missed_pkts;
		nstat->rx_frame_errors  = hwstat->rx_align_errs;
		nstat->rx_crc_errors    = hwstat->rx_crc_errs;
		nstat->rx_errors        = (hwstat->rx_jabber_pkts +
					   hwstat->rx_oversize_pkts +
					   hwstat->rx_missed_pkts +
					   hwstat->rx_crc_align_errs +
					   hwstat->rx_undersize +
					   hwstat->rx_crc_errs +
					   hwstat->rx_align_errs +
					   hwstat->rx_symbol_errs);

		nstat->tx_aborted_errors = hwstat->tx_underruns;
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#if 0
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		/* Carrier lost counter seems to be broken for some devices */
		nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
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#endif
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	} while (u64_stats_fetch_retry_bh(&hwstat->syncp, start));
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	return nstat;
}

static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
{
1688
	struct netdev_hw_addr *ha;
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	int i, num_ents;

1691
	num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
1692
	i = 0;
1693
	netdev_for_each_mc_addr(ha, dev) {
1694 1695
		if (i == num_ents)
			break;
1696
		__b44_cam_write(bp, ha->addr, i++ + 1);
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	}
	return i+1;
}

static void __b44_set_rx_mode(struct net_device *dev)
{
	struct b44 *bp = netdev_priv(dev);
	u32 val;

	val = br32(bp, B44_RXCONFIG);
	val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1708
	if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
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		val |= RXCONFIG_PROMISC;
		bw32(bp, B44_RXCONFIG, val);
	} else {
1712
		unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1713
		int i = 1;
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		__b44_set_mac_addr(bp);

1717
		if ((dev->flags & IFF_ALLMULTI) ||
1718
		    (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
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			val |= RXCONFIG_ALLMULTI;
		else
1721
			i = __b44_load_mcast(bp, dev);
1722

1723
		for (; i < 64; i++)
1724
			__b44_cam_write(bp, zero, i);
1725

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		bw32(bp, B44_RXCONFIG, val);
        	val = br32(bp, B44_CAM_CTRL);
	        bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
	}
}

static void b44_set_rx_mode(struct net_device *dev)
{
	struct b44 *bp = netdev_priv(dev);

	spin_lock_irq(&bp->lock);
	__b44_set_rx_mode(dev);
	spin_unlock_irq(&bp->lock);
}

static u32 b44_get_msglevel(struct net_device *dev)
{
	struct b44 *bp = netdev_priv(dev);
	return bp->msg_enable;
}

static void b44_set_msglevel(struct net_device *dev, u32 value)
{
	struct b44 *bp = netdev_priv(dev);
	bp->msg_enable = value;
}

static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
{
	struct b44 *bp = netdev_priv(dev);
1756
	struct ssb_bus *bus = bp->sdev->bus;
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1758 1759
	strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
	strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1760 1761
	switch (bus->bustype) {
	case SSB_BUSTYPE_PCI:
1762
		strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1763 1764
		break;
	case SSB_BUSTYPE_SSB:
1765
		strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
1766
		break;
1767 1768 1769 1770
	case SSB_BUSTYPE_PCMCIA:
	case SSB_BUSTYPE_SDIO:
		WARN_ON(1); /* A device with this bus does not exist. */
		break;
1771
	}
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}

static int b44_nway_reset(struct net_device *dev)
{
	struct b44 *bp = netdev_priv(dev);
	u32 bmcr;
	int r;

	spin_lock_irq(&bp->lock);
	b44_readphy(bp, MII_BMCR, &bmcr);
	b44_readphy(bp, MII_BMCR, &bmcr);
	r = -EINVAL;
	if (bmcr & BMCR_ANENABLE) {
		b44_writephy(bp, MII_BMCR,
			     bmcr | BMCR_ANRESTART);
		r = 0;
	}
	spin_unlock_irq(&bp->lock);

	return r;
}

static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct b44 *bp = netdev_priv(dev);

	cmd->supported = (SUPPORTED_Autoneg);
	cmd->supported |= (SUPPORTED_100baseT_Half |
			  SUPPORTED_100baseT_Full |
			  SUPPORTED_10baseT_Half |
			  SUPPORTED_10baseT_Full |
			  SUPPORTED_MII);

	cmd->advertising = 0;
	if (bp->flags & B44_FLAG_ADV_10HALF)
1807
		cmd->advertising |= ADVERTISED_10baseT_Half;
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	if (bp->flags & B44_FLAG_ADV_10FULL)
1809
		cmd->advertising |= ADVERTISED_10baseT_Full;
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	if (bp->flags & B44_FLAG_ADV_100HALF)
1811
		cmd->advertising |= ADVERTISED_100baseT_Half;
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	if (bp->flags & B44_FLAG_ADV_100FULL)
1813 1814
		cmd->advertising |= ADVERTISED_100baseT_Full;
	cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1815 1816
	ethtool_cmd_speed_set(cmd, ((bp->flags & B44_FLAG_100_BASE_T) ?
				    SPEED_100 : SPEED_10));
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	cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
		DUPLEX_FULL : DUPLEX_HALF;
	cmd->port = 0;
	cmd->phy_address = bp->phy_addr;
	cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
		XCVR_INTERNAL : XCVR_EXTERNAL;
	cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
		AUTONEG_DISABLE : AUTONEG_ENABLE;
1825 1826 1827
	if (cmd->autoneg == AUTONEG_ENABLE)
		cmd->advertising |= ADVERTISED_Autoneg;
	if (!netif_running(dev)){
1828
		ethtool_cmd_speed_set(cmd, 0);
1829 1830
		cmd->duplex = 0xff;
	}
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	cmd->maxtxpkt = 0;
	cmd->maxrxpkt = 0;
	return 0;
}

static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct b44 *bp = netdev_priv(dev);
1839
	u32 speed = ethtool_cmd_speed(cmd);
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	/* We do not support gigabit. */
	if (cmd->autoneg == AUTONEG_ENABLE) {
		if (cmd->advertising &
		    (ADVERTISED_1000baseT_Half |
		     ADVERTISED_1000baseT_Full))
			return -EINVAL;
1847 1848
	} else if ((speed != SPEED_100 &&
		    speed != SPEED_10) ||
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		   (cmd->duplex != DUPLEX_HALF &&
		    cmd->duplex != DUPLEX_FULL)) {
			return -EINVAL;
	}

	spin_lock_irq(&bp->lock);

	if (cmd->autoneg == AUTONEG_ENABLE) {
1857 1858 1859 1860
		bp->flags &= ~(B44_FLAG_FORCE_LINK |
			       B44_FLAG_100_BASE_T |
			       B44_FLAG_FULL_DUPLEX |
			       B44_FLAG_ADV_10HALF |
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			       B44_FLAG_ADV_10FULL |
			       B44_FLAG_ADV_100HALF |
			       B44_FLAG_ADV_100FULL);
1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878
		if (cmd->advertising == 0) {
			bp->flags |= (B44_FLAG_ADV_10HALF |
				      B44_FLAG_ADV_10FULL |
				      B44_FLAG_ADV_100HALF |
				      B44_FLAG_ADV_100FULL);
		} else {
			if (cmd->advertising & ADVERTISED_10baseT_Half)
				bp->flags |= B44_FLAG_ADV_10HALF;
			if (cmd->advertising & ADVERTISED_10baseT_Full)
				bp->flags |= B44_FLAG_ADV_10FULL;
			if (cmd->advertising & ADVERTISED_100baseT_Half)
				bp->flags |= B44_FLAG_ADV_100HALF;
			if (cmd->advertising & ADVERTISED_100baseT_Full)
				bp->flags |= B44_FLAG_ADV_100FULL;
		}
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	} else {
		bp->flags |= B44_FLAG_FORCE_LINK;
1881
		bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1882
		if (speed == SPEED_100)
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			bp->flags |= B44_FLAG_100_BASE_T;
		if (cmd->duplex == DUPLEX_FULL)
			bp->flags |= B44_FLAG_FULL_DUPLEX;
	}

1888 1889
	if (netif_running(dev))
		b44_setup_phy(bp);
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	spin_unlock_irq(&bp->lock);

	return 0;
}

static void b44_get_ringparam(struct net_device *dev,
			      struct ethtool_ringparam *ering)
{
	struct b44 *bp = netdev_priv(dev);

	ering->rx_max_pending = B44_RX_RING_SIZE - 1;
	ering->rx_pending = bp->rx_pending;

	/* XXX ethtool lacks a tx_max_pending, oops... */
}

static int b44_set_ringparam(struct net_device *dev,
			     struct ethtool_ringparam *ering)
{
	struct b44 *bp = netdev_priv(dev);

	if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
	    (ering->rx_mini_pending != 0) ||
	    (ering->rx_jumbo_pending != 0) ||
	    (ering->tx_pending > B44_TX_RING_SIZE - 1))
		return -EINVAL;

	spin_lock_irq(&bp->lock);

	bp->rx_pending = ering->rx_pending;
	bp->tx_pending = ering->tx_pending;

	b44_halt(bp);
	b44_init_rings(bp);
1925
	b44_init_hw(bp, B44_FULL_RESET);
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	netif_wake_queue(bp->dev);
	spin_unlock_irq(&bp->lock);

	b44_enable_ints(bp);
1930

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	return 0;
}

static void b44_get_pauseparam(struct net_device *dev,
				struct ethtool_pauseparam *epause)
{
	struct b44 *bp = netdev_priv(dev);

	epause->autoneg =
		(bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
	epause->rx_pause =
		(bp->flags & B44_FLAG_RX_PAUSE) != 0;
	epause->tx_pause =
		(bp->flags & B44_FLAG_TX_PAUSE) != 0;
}

static int b44_set_pauseparam(struct net_device *dev,
				struct ethtool_pauseparam *epause)
{
	struct b44 *bp = netdev_priv(dev);

	spin_lock_irq(&bp->lock);
	if (epause->autoneg)
		bp->flags |= B44_FLAG_PAUSE_AUTO;
	else
		bp->flags &= ~B44_FLAG_PAUSE_AUTO;
	if (epause->rx_pause)
		bp->flags |= B44_FLAG_RX_PAUSE;
	else
		bp->flags &= ~B44_FLAG_RX_PAUSE;
	if (epause->tx_pause)
		bp->flags |= B44_FLAG_TX_PAUSE;
	else
		bp->flags &= ~B44_FLAG_TX_PAUSE;
	if (bp->flags & B44_FLAG_PAUSE_AUTO) {
		b44_halt(bp);
		b44_init_rings(bp);
1968
		b44_init_hw(bp, B44_FULL_RESET);
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	} else {
		__b44_set_flow_ctrl(bp, bp->flags);
	}
	spin_unlock_irq(&bp->lock);

	b44_enable_ints(bp);
1975

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	return 0;
}

1979 1980 1981 1982 1983 1984 1985 1986 1987
static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
	switch(stringset) {
	case ETH_SS_STATS:
		memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
		break;
	}
}

1988
static int b44_get_sset_count(struct net_device *dev, int sset)
1989
{
1990 1991 1992 1993 1994 1995
	switch (sset) {
	case ETH_SS_STATS:
		return ARRAY_SIZE(b44_gstrings);
	default:
		return -EOPNOTSUPP;
	}
1996 1997 1998 1999 2000 2001
}

static void b44_get_ethtool_stats(struct net_device *dev,
				  struct ethtool_stats *stats, u64 *data)
{
	struct b44 *bp = netdev_priv(dev);
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	struct b44_hw_stats *hwstat = &bp->hw_stats;
	u64 *data_src, *data_dst;
	unsigned int start;
2005 2006 2007 2008
	u32 i;

	spin_lock_irq(&bp->lock);
	b44_stats_update(bp);
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	spin_unlock_irq(&bp->lock);
2010

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	do {
		data_src = &hwstat->tx_good_octets;
		data_dst = data;
		start = u64_stats_fetch_begin_bh(&hwstat->syncp);
2015

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		for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
			*data_dst++ = *data_src++;

	} while (u64_stats_fetch_retry_bh(&hwstat->syncp, start));
2020 2021
}

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2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047
static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct b44 *bp = netdev_priv(dev);

	wol->supported = WAKE_MAGIC;
	if (bp->flags & B44_FLAG_WOL_ENABLE)
		wol->wolopts = WAKE_MAGIC;
	else
		wol->wolopts = 0;
	memset(&wol->sopass, 0, sizeof(wol->sopass));
}

static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct b44 *bp = netdev_priv(dev);

	spin_lock_irq(&bp->lock);
	if (wol->wolopts & WAKE_MAGIC)
		bp->flags |= B44_FLAG_WOL_ENABLE;
	else
		bp->flags &= ~B44_FLAG_WOL_ENABLE;
	spin_unlock_irq(&bp->lock);

	return 0;
}

2048
static const struct ethtool_ops b44_ethtool_ops = {
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	.get_drvinfo		= b44_get_drvinfo,
	.get_settings		= b44_get_settings,
	.set_settings		= b44_set_settings,
	.nway_reset		= b44_nway_reset,
	.get_link		= ethtool_op_get_link,
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	.get_wol		= b44_get_wol,
	.set_wol		= b44_set_wol,
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	.get_ringparam		= b44_get_ringparam,
	.set_ringparam		= b44_set_ringparam,
	.get_pauseparam		= b44_get_pauseparam,
	.set_pauseparam		= b44_set_pauseparam,
	.get_msglevel		= b44_get_msglevel,
	.set_msglevel		= b44_set_msglevel,
2062
	.get_strings		= b44_get_strings,
2063
	.get_sset_count		= b44_get_sset_count,
2064
	.get_ethtool_stats	= b44_get_ethtool_stats,
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};

static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct mii_ioctl_data *data = if_mii(ifr);
	struct b44 *bp = netdev_priv(dev);
2071 2072 2073 2074
	int err = -EINVAL;

	if (!netif_running(dev))
		goto out;
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	spin_lock_irq(&bp->lock);
	err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
	spin_unlock_irq(&bp->lock);
2079
out:
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	return err;
}

2083
static int b44_get_invariants(struct b44 *bp)
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2084
{
2085 2086 2087
	struct ssb_device *sdev = bp->sdev;
	int err = 0;
	u8 *addr;
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2089
	bp->dma_offset = ssb_dma_translation(sdev);
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2091 2092
	if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
	    instance > 1) {
2093 2094
		addr = sdev->bus->sprom.et1mac;
		bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2095
	} else {
2096 2097
		addr = sdev->bus->sprom.et0mac;
		bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2098
	}
2099 2100 2101 2102 2103
	/* Some ROMs have buggy PHY addresses with the high
	 * bits set (sign extension?). Truncate them to a
	 * valid PHY address. */
	bp->phy_addr &= 0x1F;

2104
	memcpy(bp->dev->dev_addr, addr, 6);
2105 2106

	if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2107
		pr_err("Invalid MAC address found in EEPROM\n");
2108 2109 2110
		return -EINVAL;
	}

L
Linus Torvalds 已提交
2111 2112
	bp->imask = IMASK_DEF;

2113
	/* XXX - really required?
L
Linus Torvalds 已提交
2114
	   bp->flags |= B44_FLAG_BUGGY_TXPTR;
2115
	*/
G
Gary Zambrano 已提交
2116

2117 2118
	if (bp->sdev->id.revision >= 7)
		bp->flags |= B44_FLAG_B0_ANDLATER;
G
Gary Zambrano 已提交
2119

L
Linus Torvalds 已提交
2120 2121 2122
	return err;
}

2123 2124 2125 2126
static const struct net_device_ops b44_netdev_ops = {
	.ndo_open		= b44_open,
	.ndo_stop		= b44_close,
	.ndo_start_xmit		= b44_start_xmit,
K
Kevin Groeneveld 已提交
2127
	.ndo_get_stats64	= b44_get_stats64,
2128
	.ndo_set_rx_mode	= b44_set_rx_mode,
2129 2130 2131 2132 2133 2134 2135 2136 2137 2138
	.ndo_set_mac_address	= b44_set_mac_addr,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_do_ioctl		= b44_ioctl,
	.ndo_tx_timeout		= b44_tx_timeout,
	.ndo_change_mtu		= b44_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= b44_poll_controller,
#endif
};

2139
static int b44_init_one(struct ssb_device *sdev,
2140
			const struct ssb_device_id *ent)
L
Linus Torvalds 已提交
2141 2142 2143
{
	struct net_device *dev;
	struct b44 *bp;
2144
	int err;
L
Linus Torvalds 已提交
2145

2146 2147
	instance++;

2148
	pr_info_once("%s version %s\n", DRV_DESCRIPTION, DRV_MODULE_VERSION);
L
Linus Torvalds 已提交
2149 2150 2151 2152

	dev = alloc_etherdev(sizeof(*bp));
	if (!dev) {
		err = -ENOMEM;
2153
		goto out;
L
Linus Torvalds 已提交
2154 2155
	}

2156
	SET_NETDEV_DEV(dev, sdev->dev);
L
Linus Torvalds 已提交
2157 2158 2159 2160 2161

	/* No interesting netdevice features in this card... */
	dev->features |= 0;

	bp = netdev_priv(dev);
2162
	bp->sdev = sdev;
L
Linus Torvalds 已提交
2163
	bp->dev = dev;
2164
	bp->force_copybreak = 0;
2165 2166

	bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
L
Linus Torvalds 已提交
2167 2168 2169 2170 2171 2172

	spin_lock_init(&bp->lock);

	bp->rx_pending = B44_DEF_RX_RING_PENDING;
	bp->tx_pending = B44_DEF_TX_RING_PENDING;

2173
	dev->netdev_ops = &b44_netdev_ops;
2174
	netif_napi_add(dev, &bp->napi, b44_poll, 64);
L
Linus Torvalds 已提交
2175
	dev->watchdog_timeo = B44_TX_TIMEOUT;
2176
	dev->irq = sdev->irq;
L
Linus Torvalds 已提交
2177 2178
	SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);

2179 2180 2181 2182 2183 2184
	err = ssb_bus_powerup(sdev->bus, 0);
	if (err) {
		dev_err(sdev->dev,
			"Failed to powerup the bus\n");
		goto err_out_free_dev;
	}
2185 2186 2187

	if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
	    dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
2188
		dev_err(sdev->dev,
2189
			"Required 30BIT DMA mask unsupported by the system\n");
2190 2191
		goto err_out_powerdown;
	}
2192

L
Linus Torvalds 已提交
2193 2194
	err = b44_get_invariants(bp);
	if (err) {
2195
		dev_err(sdev->dev,
2196
			"Problem fetching invariants of chip, aborting\n");
2197
		goto err_out_powerdown;
L
Linus Torvalds 已提交
2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
	}

	bp->mii_if.dev = dev;
	bp->mii_if.mdio_read = b44_mii_read;
	bp->mii_if.mdio_write = b44_mii_write;
	bp->mii_if.phy_id = bp->phy_addr;
	bp->mii_if.phy_id_mask = 0x1f;
	bp->mii_if.reg_num_mask = 0x1f;

	/* By default, advertise all speed/duplex settings. */
	bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
		      B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);

	/* By default, auto-negotiate PAUSE. */
	bp->flags |= B44_FLAG_PAUSE_AUTO;

	err = register_netdev(dev);
	if (err) {
2216
		dev_err(sdev->dev, "Cannot register net device, aborting\n");
2217
		goto err_out_powerdown;
L
Linus Torvalds 已提交
2218 2219
	}

2220 2221
	netif_carrier_off(dev);

2222
	ssb_set_drvdata(sdev, dev);
L
Linus Torvalds 已提交
2223

2224
	/* Chip reset provides power to the b44 MAC & PCI cores, which
2225
	 * is necessary for MAC register access.
2226
	 */
2227
	b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2228

2229 2230 2231 2232
	/* do a phy reset to test if there is an active phy */
	if (b44_phy_reset(bp) < 0)
		bp->phy_addr = B44_PHY_ADDR_NO_PHY;

2233
	netdev_info(dev, "%s %pM\n", DRV_DESCRIPTION, dev->dev_addr);
L
Linus Torvalds 已提交
2234 2235 2236

	return 0;

2237 2238
err_out_powerdown:
	ssb_bus_may_powerdown(sdev->bus);
L
Linus Torvalds 已提交
2239 2240 2241 2242

err_out_free_dev:
	free_netdev(dev);

2243
out:
L
Linus Torvalds 已提交
2244 2245 2246
	return err;
}

2247
static void b44_remove_one(struct ssb_device *sdev)
L
Linus Torvalds 已提交
2248
{
2249
	struct net_device *dev = ssb_get_drvdata(sdev);
L
Linus Torvalds 已提交
2250

2251
	unregister_netdev(dev);
2252
	ssb_device_disable(sdev, 0);
2253
	ssb_bus_may_powerdown(sdev->bus);
2254
	free_netdev(dev);
2255
	ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2256
	ssb_set_drvdata(sdev, NULL);
L
Linus Torvalds 已提交
2257 2258
}

2259
static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
L
Linus Torvalds 已提交
2260
{
2261
	struct net_device *dev = ssb_get_drvdata(sdev);
L
Linus Torvalds 已提交
2262 2263
	struct b44 *bp = netdev_priv(dev);

2264 2265
	if (!netif_running(dev))
		return 0;
L
Linus Torvalds 已提交
2266 2267 2268

	del_timer_sync(&bp->timer);

2269
	spin_lock_irq(&bp->lock);
L
Linus Torvalds 已提交
2270 2271

	b44_halt(bp);
2272
	netif_carrier_off(bp->dev);
L
Linus Torvalds 已提交
2273 2274 2275 2276
	netif_device_detach(bp->dev);
	b44_free_rings(bp);

	spin_unlock_irq(&bp->lock);
2277 2278

	free_irq(dev->irq, dev);
G
Gary Zambrano 已提交
2279
	if (bp->flags & B44_FLAG_WOL_ENABLE) {
2280
		b44_init_hw(bp, B44_PARTIAL_RESET);
G
Gary Zambrano 已提交
2281 2282
		b44_setup_wol(bp);
	}
2283

2284
	ssb_pcihost_set_power_state(sdev, PCI_D3hot);
L
Linus Torvalds 已提交
2285 2286 2287
	return 0;
}

2288
static int b44_resume(struct ssb_device *sdev)
L
Linus Torvalds 已提交
2289
{
2290
	struct net_device *dev = ssb_get_drvdata(sdev);
L
Linus Torvalds 已提交
2291
	struct b44 *bp = netdev_priv(dev);
2292
	int rc = 0;
L
Linus Torvalds 已提交
2293

2294
	rc = ssb_bus_powerup(sdev->bus, 0);
2295
	if (rc) {
2296 2297
		dev_err(sdev->dev,
			"Failed to powerup the bus\n");
2298 2299 2300
		return rc;
	}

L
Linus Torvalds 已提交
2301 2302 2303
	if (!netif_running(dev))
		return 0;

2304 2305 2306 2307 2308 2309 2310 2311 2312 2313
	spin_lock_irq(&bp->lock);
	b44_init_rings(bp);
	b44_init_hw(bp, B44_FULL_RESET);
	spin_unlock_irq(&bp->lock);

	/*
	 * As a shared interrupt, the handler can be called immediately. To be
	 * able to check the interrupt status the hardware must already be
	 * powered back on (b44_init_hw).
	 */
2314 2315
	rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
	if (rc) {
2316
		netdev_err(dev, "request_irq failed\n");
2317 2318 2319 2320
		spin_lock_irq(&bp->lock);
		b44_halt(bp);
		b44_free_rings(bp);
		spin_unlock_irq(&bp->lock);
2321 2322
		return rc;
	}
2323

L
Linus Torvalds 已提交
2324 2325 2326
	netif_device_attach(bp->dev);

	b44_enable_ints(bp);
2327
	netif_wake_queue(dev);
2328 2329 2330

	mod_timer(&bp->timer, jiffies + 1);

L
Linus Torvalds 已提交
2331 2332 2333
	return 0;
}

2334
static struct ssb_driver b44_ssb_driver = {
L
Linus Torvalds 已提交
2335
	.name		= DRV_MODULE_NAME,
2336
	.id_table	= b44_ssb_tbl,
L
Linus Torvalds 已提交
2337
	.probe		= b44_init_one,
2338
	.remove		= b44_remove_one,
2339 2340
	.suspend	= b44_suspend,
	.resume		= b44_resume,
L
Linus Torvalds 已提交
2341 2342
};

2343
static inline int __init b44_pci_init(void)
2344 2345 2346 2347 2348 2349 2350 2351
{
	int err = 0;
#ifdef CONFIG_B44_PCI
	err = ssb_pcihost_register(&b44_pci_driver);
#endif
	return err;
}

2352
static inline void b44_pci_exit(void)
2353 2354 2355 2356 2357 2358
{
#ifdef CONFIG_B44_PCI
	ssb_pcihost_unregister(&b44_pci_driver);
#endif
}

L
Linus Torvalds 已提交
2359 2360
static int __init b44_init(void)
{
2361
	unsigned int dma_desc_align_size = dma_get_cache_alignment();
2362
	int err;
2363 2364

	/* Setup paramaters for syncing RX/TX DMA descriptors */
2365
	dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2366

2367 2368 2369 2370 2371 2372 2373
	err = b44_pci_init();
	if (err)
		return err;
	err = ssb_driver_register(&b44_ssb_driver);
	if (err)
		b44_pci_exit();
	return err;
L
Linus Torvalds 已提交
2374 2375 2376 2377
}

static void __exit b44_cleanup(void)
{
2378 2379
	ssb_driver_unregister(&b44_ssb_driver);
	b44_pci_exit();
L
Linus Torvalds 已提交
2380 2381 2382 2383 2384
}

module_init(b44_init);
module_exit(b44_cleanup);
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