zynq-7000.dtsi

/*
 *  Copyright (C) 2011 Xilinx
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
/include/ "skeleton.dtsi"

/ {
	compatible = "xlnx,zynq-7000";

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		intc: interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0xF8F01000 0x1000>,
			      <0xF8F00100 0x100>;
		};

		L2: cache-controller {
			compatible = "arm,pl310-cache";
			reg = <0xF8F02000 0x1000>;
			arm,data-latency = <2 3 2>;
			arm,tag-latency = <2 3 2>;
			cache-unified;
			cache-level = <2>;
		};

		uart0: uart@e0000000 {
			compatible = "xlnx,xuartps";
			reg = <0xE0000000 0x1000>;
			interrupts = <0 27 4>;
			clock = <50000000>;
		};

		uart1: uart@e0001000 {
			compatible = "xlnx,xuartps";
			reg = <0xE0001000 0x1000>;
			interrupts = <0 50 4>;
			clock = <50000000>;
		};
	};
};