xhci.h 64.6 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
/*
 * xHCI host controller driver
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __LINUX_XHCI_HCD_H
#define __LINUX_XHCI_HCD_H

#include <linux/usb.h>
27
#include <linux/timer.h>
28
#include <linux/kernel.h>
29
#include <linux/usb/hcd.h>
30 31 32

/* Code sharing between pci-quirks and xhci hcd */
#include	"xhci-ext-caps.h"
A
Andiry Xu 已提交
33
#include "pci-quirks.h"
34 35 36 37

/* xHCI PCI Configuration Registers */
#define XHCI_SBRN_OFFSET	(0x60)

38 39
/* Max number of USB devices for any host controller - limit in section 6.1 */
#define MAX_HC_SLOTS		256
S
Sarah Sharp 已提交
40 41
/* Section 5.3.3 - MaxPorts */
#define MAX_HC_PORTS		127
42

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
/*
 * xHCI register interface.
 * This corresponds to the eXtensible Host Controller Interface (xHCI)
 * Revision 0.95 specification
 */

/**
 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
 * @hc_capbase:		length of the capabilities register and HC version number
 * @hcs_params1:	HCSPARAMS1 - Structural Parameters 1
 * @hcs_params2:	HCSPARAMS2 - Structural Parameters 2
 * @hcs_params3:	HCSPARAMS3 - Structural Parameters 3
 * @hcc_params:		HCCPARAMS - Capability Parameters
 * @db_off:		DBOFF - Doorbell array offset
 * @run_regs_off:	RTSOFF - Runtime register space offset
 */
struct xhci_cap_regs {
M
Matt Evans 已提交
60 61 62 63 64 65 66
	__le32	hc_capbase;
	__le32	hcs_params1;
	__le32	hcs_params2;
	__le32	hcs_params3;
	__le32	hcc_params;
	__le32	db_off;
	__le32	run_regs_off;
67
	/* Reserved up to (CAPLENGTH - 0x1C) */
68
};
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

/* hc_capbase bitmasks */
/* bits 7:0 - how long is the Capabilities register */
#define HC_LENGTH(p)		XHCI_HC_LENGTH(p)
/* bits 31:16	*/
#define HC_VERSION(p)		(((p) >> 16) & 0xffff)

/* HCSPARAMS1 - hcs_params1 - bitmasks */
/* bits 0:7, Max Device Slots */
#define HCS_MAX_SLOTS(p)	(((p) >> 0) & 0xff)
#define HCS_SLOTS_MASK		0xff
/* bits 8:18, Max Interrupters */
#define HCS_MAX_INTRS(p)	(((p) >> 8) & 0x7ff)
/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
#define HCS_MAX_PORTS(p)	(((p) >> 24) & 0x7f)

/* HCSPARAMS2 - hcs_params2 - bitmasks */
/* bits 0:3, frames or uframes that SW needs to queue transactions
 * ahead of the HW to meet periodic deadlines */
#define HCS_IST(p)		(((p) >> 0) & 0xf)
/* bits 4:7, max number of Event Ring segments */
#define HCS_ERST_MAX(p)		(((p) >> 4) & 0xf)
/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
93
#define HCS_MAX_SCRATCHPAD(p)   (((p) >> 27) & 0x1f)
94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

/* HCSPARAMS3 - hcs_params3 - bitmasks */
/* bits 0:7, Max U1 to U0 latency for the roothub ports */
#define HCS_U1_LATENCY(p)	(((p) >> 0) & 0xff)
/* bits 16:31, Max U2 to U0 latency for the roothub ports */
#define HCS_U2_LATENCY(p)	(((p) >> 16) & 0xffff)

/* HCCPARAMS - hcc_params - bitmasks */
/* true: HC can use 64-bit address pointers */
#define HCC_64BIT_ADDR(p)	((p) & (1 << 0))
/* true: HC can do bandwidth negotiation */
#define HCC_BANDWIDTH_NEG(p)	((p) & (1 << 1))
/* true: HC uses 64-byte Device Context structures
 * FIXME 64-byte context structures aren't supported yet.
 */
#define HCC_64BYTE_CONTEXT(p)	((p) & (1 << 2))
/* true: HC has port power switches */
#define HCC_PPC(p)		((p) & (1 << 3))
/* true: HC has port indicators */
#define HCS_INDICATOR(p)	((p) & (1 << 4))
/* true: HC has Light HC Reset Capability */
#define HCC_LIGHT_RESET(p)	((p) & (1 << 5))
/* true: HC supports latency tolerance messaging */
#define HCC_LTC(p)		((p) & (1 << 6))
/* true: no secondary Stream ID Support */
#define HCC_NSS(p)		((p) & (1 << 7))
/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121
#define HCC_MAX_PSA(p)		(1 << ((((p) >> 12) & 0xf) + 1))
122 123 124 125 126 127 128 129 130 131 132 133 134
/* Extended Capabilities pointer from PCI base - section 5.3.6 */
#define HCC_EXT_CAPS(p)		XHCI_HCC_EXT_CAPS(p)

/* db_off bitmask - bits 0:1 reserved */
#define	DBOFF_MASK	(~0x3)

/* run_regs_off bitmask - bits 0:4 reserved */
#define	RTSOFF_MASK	(~0x1f)


/* Number of registers per port */
#define	NUM_PORT_REGS	4

135 136 137 138 139
#define PORTSC		0
#define PORTPMSC	1
#define PORTLI		2
#define PORTHLPMC	3

140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
/**
 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
 * @command:		USBCMD - xHC command register
 * @status:		USBSTS - xHC status register
 * @page_size:		This indicates the page size that the host controller
 * 			supports.  If bit n is set, the HC supports a page size
 * 			of 2^(n+12), up to a 128MB page size.
 * 			4K is the minimum page size.
 * @cmd_ring:		CRP - 64-bit Command Ring Pointer
 * @dcbaa_ptr:		DCBAAP - 64-bit Device Context Base Address Array Pointer
 * @config_reg:		CONFIG - Configure Register
 * @port_status_base:	PORTSCn - base address for Port Status and Control
 * 			Each port has a Port Status and Control register,
 * 			followed by a Port Power Management Status and Control
 * 			register, a Port Link Info register, and a reserved
 * 			register.
 * @port_power_base:	PORTPMSCn - base address for
 * 			Port Power Management Status and Control
 * @port_link_base:	PORTLIn - base address for Port Link Info (current
 * 			Link PM state and control) for USB 2.1 and USB 3.0
 * 			devices.
 */
struct xhci_op_regs {
M
Matt Evans 已提交
163 164 165 166 167 168 169
	__le32	command;
	__le32	status;
	__le32	page_size;
	__le32	reserved1;
	__le32	reserved2;
	__le32	dev_notification;
	__le64	cmd_ring;
170
	/* rsvd: offset 0x20-2F */
M
Matt Evans 已提交
171 172 173
	__le32	reserved3[4];
	__le64	dcbaa_ptr;
	__le32	config_reg;
174
	/* rsvd: offset 0x3C-3FF */
M
Matt Evans 已提交
175
	__le32	reserved4[241];
176
	/* port 1 registers, which serve as a base address for other ports */
M
Matt Evans 已提交
177 178 179 180
	__le32	port_status_base;
	__le32	port_power_base;
	__le32	port_link_base;
	__le32	reserved5;
181
	/* registers for ports 2-255 */
M
Matt Evans 已提交
182
	__le32	reserved6[NUM_PORT_REGS*254];
183
};
184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199

/* USBCMD - USB command - command bitmasks */
/* start/stop HC execution - do not write unless HC is halted*/
#define CMD_RUN		XHCI_CMD_RUN
/* Reset HC - resets internal HC state machine and all registers (except
 * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
 * The xHCI driver must reinitialize the xHC after setting this bit.
 */
#define CMD_RESET	(1 << 1)
/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
#define CMD_EIE		XHCI_CMD_EIE
/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
#define CMD_HSEIE	XHCI_CMD_HSEIE
/* bits 4:6 are reserved (and should be preserved on writes). */
/* light reset (port status stays unchanged) - reset completed when this is 0 */
#define CMD_LRESET	(1 << 7)
200
/* host controller save/restore state. */
201 202 203 204 205 206 207 208 209 210 211 212
#define CMD_CSS		(1 << 8)
#define CMD_CRS		(1 << 9)
/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
#define CMD_EWE		XHCI_CMD_EWE
/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
 * '0' means the xHC can power it off if all ports are in the disconnect,
 * disabled, or powered-off state.
 */
#define CMD_PM_INDEX	(1 << 11)
/* bits 12:31 are reserved (and should be preserved on writes). */

213
/* IMAN - Interrupt Management Register */
214 215
#define IMAN_IE		(1 << 1)
#define IMAN_IP		(1 << 0)
216

217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244
/* USBSTS - USB status - status bitmasks */
/* HC not running - set to 1 when run/stop bit is cleared. */
#define STS_HALT	XHCI_STS_HALT
/* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
#define STS_FATAL	(1 << 2)
/* event interrupt - clear this prior to clearing any IP flags in IR set*/
#define STS_EINT	(1 << 3)
/* port change detect */
#define STS_PORT	(1 << 4)
/* bits 5:7 reserved and zeroed */
/* save state status - '1' means xHC is saving state */
#define STS_SAVE	(1 << 8)
/* restore state status - '1' means xHC is restoring state */
#define STS_RESTORE	(1 << 9)
/* true: save or restore error */
#define STS_SRE		(1 << 10)
/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
#define STS_CNR		XHCI_STS_CNR
/* true: internal Host Controller Error - SW needs to reset and reinitialize */
#define STS_HCE		(1 << 12)
/* bits 13:31 reserved and should be preserved */

/*
 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
 * Generate a device notification event when the HC sees a transaction with a
 * notification type that matches a bit set in this bit field.
 */
#define	DEV_NOTE_MASK		(0xffff)
245
#define ENABLE_DEV_NOTE(x)	(1 << (x))
246 247 248 249 250
/* Most of the device notification types should only be used for debug.
 * SW does need to pay attention to function wake notifications.
 */
#define	DEV_NOTE_FWAKE		ENABLE_DEV_NOTE(1)

251 252 253 254 255 256 257 258 259 260
/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
/* bit 0 is the command ring cycle state */
/* stop ring operation after completion of the currently executing command */
#define CMD_RING_PAUSE		(1 << 1)
/* stop ring immediately - abort the currently executing command */
#define CMD_RING_ABORT		(1 << 2)
/* true: command ring is running */
#define CMD_RING_RUNNING	(1 << 3)
/* bits 4:5 reserved and should be preserved */
/* Command Ring pointer - bit mask for the lower 32 bits. */
261
#define CMD_RING_RSVD_BITS	(0x3f)
262

263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281
/* CONFIG - Configure Register - config_reg bitmasks */
/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
#define MAX_DEVS(p)	((p) & 0xff)
/* bits 8:31 - reserved and should be preserved */

/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
/* true: device connected */
#define PORT_CONNECT	(1 << 0)
/* true: port enabled */
#define PORT_PE		(1 << 1)
/* bit 2 reserved and zeroed */
/* true: port has an over-current condition */
#define PORT_OC		(1 << 3)
/* true: port reset signaling asserted */
#define PORT_RESET	(1 << 4)
/* Port Link State - bits 5:8
 * A read gives the current link PM state of the port,
 * a write with Link State Write Strobe set sets the link state.
 */
282 283
#define PORT_PLS_MASK	(0xf << 5)
#define XDEV_U0		(0x0 << 5)
A
Andiry Xu 已提交
284
#define XDEV_U2		(0x2 << 5)
285 286
#define XDEV_U3		(0x3 << 5)
#define XDEV_RESUME	(0xf << 5)
287 288 289 290 291 292 293 294 295 296
/* true: port has power (see HCC_PPC) */
#define PORT_POWER	(1 << 9)
/* bits 10:13 indicate device speed:
 * 0 - undefined speed - port hasn't be initialized by a reset yet
 * 1 - full speed
 * 2 - low speed
 * 3 - high speed
 * 4 - super speed
 * 5-15 reserved
 */
297 298 299 300 301
#define DEV_SPEED_MASK		(0xf << 10)
#define	XDEV_FS			(0x1 << 10)
#define	XDEV_LS			(0x2 << 10)
#define	XDEV_HS			(0x3 << 10)
#define	XDEV_SS			(0x4 << 10)
302
#define DEV_UNDEFSPEED(p)	(((p) & DEV_SPEED_MASK) == (0x0<<10))
303 304 305 306 307 308 309 310 311
#define DEV_FULLSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_FS)
#define DEV_LOWSPEED(p)		(((p) & DEV_SPEED_MASK) == XDEV_LS)
#define DEV_HIGHSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_HS)
#define DEV_SUPERSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_SS)
/* Bits 20:23 in the Slot Context are the speed for the device */
#define	SLOT_SPEED_FS		(XDEV_FS << 10)
#define	SLOT_SPEED_LS		(XDEV_LS << 10)
#define	SLOT_SPEED_HS		(XDEV_HS << 10)
#define	SLOT_SPEED_SS		(XDEV_SS << 10)
312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348
/* Port Indicator Control */
#define PORT_LED_OFF	(0 << 14)
#define PORT_LED_AMBER	(1 << 14)
#define PORT_LED_GREEN	(2 << 14)
#define PORT_LED_MASK	(3 << 14)
/* Port Link State Write Strobe - set this when changing link state */
#define PORT_LINK_STROBE	(1 << 16)
/* true: connect status change */
#define PORT_CSC	(1 << 17)
/* true: port enable change */
#define PORT_PEC	(1 << 18)
/* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
 * into an enabled state, and the device into the default state.  A "warm" reset
 * also resets the link, forcing the device through the link training sequence.
 * SW can also look at the Port Reset register to see when warm reset is done.
 */
#define PORT_WRC	(1 << 19)
/* true: over-current change */
#define PORT_OCC	(1 << 20)
/* true: reset change - 1 to 0 transition of PORT_RESET */
#define PORT_RC		(1 << 21)
/* port link status change - set on some port link state transitions:
 *  Transition				Reason
 *  ------------------------------------------------------------------------------
 *  - U3 to Resume			Wakeup signaling from a device
 *  - Resume to Recovery to U0		USB 3.0 device resume
 *  - Resume to U0			USB 2.0 device resume
 *  - U3 to Recovery to U0		Software resume of USB 3.0 device complete
 *  - U3 to U0				Software resume of USB 2.0 device complete
 *  - U2 to U0				L1 resume of USB 2.1 device complete
 *  - U0 to U0 (???)			L1 entry rejection by USB 2.1 device
 *  - U0 to disabled			L1 entry error with USB 2.1 device
 *  - Any state to inactive		Error on USB 3.0 port
 */
#define PORT_PLC	(1 << 22)
/* port configure error change - port failed to configure its link partner */
#define PORT_CEC	(1 << 23)
349 350 351 352 353
/* Cold Attach Status - xHC can set this bit to report device attached during
 * Sx state. Warm port reset should be perfomed to clear this bit and move port
 * to connected state.
 */
#define PORT_CAS	(1 << 24)
354 355 356 357 358 359 360 361 362 363 364 365
/* wake on connect (enable) */
#define PORT_WKCONN_E	(1 << 25)
/* wake on disconnect (enable) */
#define PORT_WKDISC_E	(1 << 26)
/* wake on over-current (enable) */
#define PORT_WKOC_E	(1 << 27)
/* bits 28:29 reserved */
/* true: device is removable - for USB 3.0 roothub emulation */
#define PORT_DEV_REMOVE	(1 << 30)
/* Initiate a warm port reset - complete when PORT_WRC is '1' */
#define PORT_WR		(1 << 31)

366 367 368
/* We mark duplicate entries with -1 */
#define DUPLICATE_ENTRY ((u8)(-1))

369 370 371 372 373
/* Port Power Management Status and Control - port_power_base bitmasks */
/* Inactivity timer value for transitions into U1, in microseconds.
 * Timeout can be up to 127us.  0xFF means an infinite timeout.
 */
#define PORT_U1_TIMEOUT(p)	((p) & 0xff)
374
#define PORT_U1_TIMEOUT_MASK	0xff
375 376
/* Inactivity timer value for transitions into U2 */
#define PORT_U2_TIMEOUT(p)	(((p) & 0xff) << 8)
377
#define PORT_U2_TIMEOUT_MASK	(0xff << 8)
378 379
/* Bits 24:31 for port testing */

380
/* USB2 Protocol PORTSPMSC */
A
Andiry Xu 已提交
381 382 383 384
#define	PORT_L1S_MASK		7
#define	PORT_L1S_SUCCESS	1
#define	PORT_RWE		(1 << 3)
#define	PORT_HIRD(p)		(((p) & 0xf) << 4)
A
Andiry Xu 已提交
385
#define	PORT_HIRD_MASK		(0xf << 4)
386
#define	PORT_L1DS_MASK		(0xff << 8)
A
Andiry Xu 已提交
387
#define	PORT_L1DS(p)		(((p) & 0xff) << 8)
A
Andiry Xu 已提交
388
#define	PORT_HLE		(1 << 16)
389

390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410

/* USB2 Protocol PORTHLPMC */
#define PORT_HIRDM(p)((p) & 3)
#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
#define PORT_BESLD(p)(((p) & 0xf) << 10)

/* use 512 microseconds as USB2 LPM L1 default timeout. */
#define XHCI_L1_TIMEOUT		512

/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
 * by other operating systems.
 *
 * XHCI 1.0 errata 8/14/12 Table 13 notes:
 * "Software should choose xHC BESL/BESLD field values that do not violate a
 * device's resume latency requirements,
 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
 * or not program values < '4' if BLC = '0' and a BESL device is attached.
 */
#define XHCI_DEFAULT_BESL	4

411
/**
412
 * struct xhci_intr_reg - Interrupt Register Set
413 414 415 416 417 418 419 420 421 422 423 424 425 426 427
 * @irq_pending:	IMAN - Interrupt Management Register.  Used to enable
 *			interrupts and check for pending interrupts.
 * @irq_control:	IMOD - Interrupt Moderation Register.
 * 			Used to throttle interrupts.
 * @erst_size:		Number of segments in the Event Ring Segment Table (ERST).
 * @erst_base:		ERST base address.
 * @erst_dequeue:	Event ring dequeue pointer.
 *
 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
 * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
 * multiple segments of the same size.  The HC places events on the ring and
 * "updates the Cycle bit in the TRBs to indicate to software the current
 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
 * updates the dequeue pointer.
 */
428
struct xhci_intr_reg {
M
Matt Evans 已提交
429 430 431 432 433 434
	__le32	irq_pending;
	__le32	irq_control;
	__le32	erst_size;
	__le32	rsvd;
	__le64	erst_base;
	__le64	erst_dequeue;
435
};
436

437
/* irq_pending bitmasks */
438
#define	ER_IRQ_PENDING(p)	((p) & 0x1)
439
/* bits 2:31 need to be preserved */
440
/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
441 442 443 444 445 446 447 448 449 450 451 452 453 454
#define	ER_IRQ_CLEAR(p)		((p) & 0xfffffffe)
#define	ER_IRQ_ENABLE(p)	((ER_IRQ_CLEAR(p)) | 0x2)
#define	ER_IRQ_DISABLE(p)	((ER_IRQ_CLEAR(p)) & ~(0x2))

/* irq_control bitmasks */
/* Minimum interval between interrupts (in 250ns intervals).  The interval
 * between interrupts will be longer if there are no events on the event ring.
 * Default is 4000 (1 ms).
 */
#define ER_IRQ_INTERVAL_MASK	(0xffff)
/* Counter used to count down the time to the next interrupt - HW use only */
#define ER_IRQ_COUNTER_MASK	(0xffff << 16)

/* erst_size bitmasks */
455
/* Preserve bits 16:31 of erst_size */
456 457 458 459 460 461 462 463 464 465 466
#define	ERST_SIZE_MASK		(0xffff << 16)

/* erst_dequeue bitmasks */
/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
 * where the current dequeue pointer lies.  This is an optional HW hint.
 */
#define ERST_DESI_MASK		(0x7)
/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
 * a work queue (or delayed service routine)?
 */
#define ERST_EHB		(1 << 3)
467
#define ERST_PTR_MASK		(0xf)
468 469 470 471 472 473 474 475 476 477 478

/**
 * struct xhci_run_regs
 * @microframe_index:
 * 		MFINDEX - current microframe number
 *
 * Section 5.5 Host Controller Runtime Registers:
 * "Software should read and write these registers using only Dword (32 bit)
 * or larger accesses"
 */
struct xhci_run_regs {
M
Matt Evans 已提交
479 480
	__le32			microframe_index;
	__le32			rsvd[7];
481 482
	struct xhci_intr_reg	ir_set[128];
};
483

484 485 486
/**
 * struct doorbell_array
 *
487 488 489 490
 * Bits  0 -  7: Endpoint target
 * Bits  8 - 15: RsvdZ
 * Bits 16 - 31: Stream ID
 *
491 492 493
 * Section 5.6
 */
struct xhci_doorbell_array {
M
Matt Evans 已提交
494
	__le32	doorbell[256];
495
};
496

497 498
#define DB_VALUE(ep, stream)	((((ep) + 1) & 0xff) | ((stream) << 16))
#define DB_VALUE_HOST		0x00000000
499

500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517
/**
 * struct xhci_protocol_caps
 * @revision:		major revision, minor revision, capability ID,
 *			and next capability pointer.
 * @name_string:	Four ASCII characters to say which spec this xHC
 *			follows, typically "USB ".
 * @port_info:		Port offset, count, and protocol-defined information.
 */
struct xhci_protocol_caps {
	u32	revision;
	u32	name_string;
	u32	port_info;
};

#define	XHCI_EXT_PORT_MAJOR(x)	(((x) >> 24) & 0xff)
#define	XHCI_EXT_PORT_OFF(x)	((x) & 0xff)
#define	XHCI_EXT_PORT_COUNT(x)	(((x) >> 8) & 0xff)

518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538
/**
 * struct xhci_container_ctx
 * @type: Type of context.  Used to calculated offsets to contained contexts.
 * @size: Size of the context data
 * @bytes: The raw context data given to HW
 * @dma: dma address of the bytes
 *
 * Represents either a Device or Input context.  Holds a pointer to the raw
 * memory used for the context (bytes) and dma address of it (dma).
 */
struct xhci_container_ctx {
	unsigned type;
#define XHCI_CTX_TYPE_DEVICE  0x1
#define XHCI_CTX_TYPE_INPUT   0x2

	int size;

	u8 *bytes;
	dma_addr_t dma;
};

539 540 541 542 543 544 545 546 547 548 549 550
/**
 * struct xhci_slot_ctx
 * @dev_info:	Route string, device speed, hub info, and last valid endpoint
 * @dev_info2:	Max exit latency for device number, root hub port number
 * @tt_info:	tt_info is used to construct split transaction tokens
 * @dev_state:	slot state and device address
 *
 * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
 * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 * reserved at the end of the slot context for HC internal use.
 */
struct xhci_slot_ctx {
M
Matt Evans 已提交
551 552 553 554
	__le32	dev_info;
	__le32	dev_info2;
	__le32	tt_info;
	__le32	dev_state;
555
	/* offset 0x10 to 0x1f reserved for HC internal use */
M
Matt Evans 已提交
556
	__le32	reserved[4];
557
};
558 559 560 561 562 563 564 565 566 567 568 569

/* dev_info bitmasks */
/* Route String - 0:19 */
#define ROUTE_STRING_MASK	(0xfffff)
/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
#define DEV_SPEED	(0xf << 20)
/* bit 24 reserved */
/* Is this LS/FS device connected through a HS hub? - bit 25 */
#define DEV_MTT		(0x1 << 25)
/* Set if the device is a hub - bit 26 */
#define DEV_HUB		(0x1 << 26)
/* Index of the last valid endpoint context in this device context - 27:31 */
570 571 572 573 574
#define LAST_CTX_MASK	(0x1f << 27)
#define LAST_CTX(p)	((p) << 27)
#define LAST_CTX_TO_EP_NUM(p)	(((p) >> 27) - 1)
#define SLOT_FLAG	(1 << 0)
#define EP0_FLAG	(1 << 1)
575 576 577 578 579

/* dev_info2 bitmasks */
/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
#define MAX_EXIT	(0xffff)
/* Root hub port number that is needed to access the USB device */
580
#define ROOT_HUB_PORT(p)	(((p) & 0xff) << 16)
581
#define DEVINFO_TO_ROOT_HUB_PORT(p)	(((p) >> 16) & 0xff)
S
Sarah Sharp 已提交
582 583
/* Maximum number of ports under a hub device */
#define XHCI_MAX_PORTS(p)	(((p) & 0xff) << 24)
584 585 586 587 588 589 590 591 592 593 594 595 596

/* tt_info bitmasks */
/*
 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
 * The Slot ID of the hub that isolates the high speed signaling from
 * this low or full-speed device.  '0' if attached to root hub port.
 */
#define TT_SLOT		(0xff)
/*
 * The number of the downstream facing port of the high-speed hub
 * '0' if the device is not low or full speed.
 */
#define TT_PORT		(0xff << 8)
S
Sarah Sharp 已提交
597
#define TT_THINK_TIME(p)	(((p) & 0x3) << 16)
598 599 600

/* dev_state bitmasks */
/* USB device address - assigned by the HC */
601
#define DEV_ADDR_MASK	(0xff)
602 603 604
/* bits 8:26 reserved */
/* Slot state */
#define SLOT_STATE	(0x1f << 27)
605
#define GET_SLOT_STATE(p)	(((p) & (0x1f << 27)) >> 27)
606

607 608 609 610 611
#define SLOT_STATE_DISABLED	0
#define SLOT_STATE_ENABLED	SLOT_STATE_DISABLED
#define SLOT_STATE_DEFAULT	1
#define SLOT_STATE_ADDRESSED	2
#define SLOT_STATE_CONFIGURED	3
612 613 614 615 616 617 618

/**
 * struct xhci_ep_ctx
 * @ep_info:	endpoint state, streams, mult, and interval information.
 * @ep_info2:	information on endpoint type, max packet size, max burst size,
 * 		error count, and whether the HC will force an event for all
 * 		transactions.
619 620 621 622 623 624 625
 * @deq:	64-bit ring dequeue pointer address.  If the endpoint only
 * 		defines one stream, this points to the endpoint transfer ring.
 * 		Otherwise, it points to a stream context array, which has a
 * 		ring pointer for each flow.
 * @tx_info:
 * 		Average TRB lengths for the endpoint ring and
 * 		max payload within an Endpoint Service Interval Time (ESIT).
626 627 628 629 630 631
 *
 * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
 * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 * reserved at the end of the endpoint context for HC internal use.
 */
struct xhci_ep_ctx {
M
Matt Evans 已提交
632 633 634 635
	__le32	ep_info;
	__le32	ep_info2;
	__le64	deq;
	__le32	tx_info;
636
	/* offset 0x14 - 0x1f reserved for HC internal use */
M
Matt Evans 已提交
637
	__le32	reserved[3];
638
};
639 640 641 642 643 644 645 646 647 648 649

/* ep_info bitmasks */
/*
 * Endpoint State - bits 0:2
 * 0 - disabled
 * 1 - running
 * 2 - halted due to halt condition - ok to manipulate endpoint ring
 * 3 - stopped
 * 4 - TRB error
 * 5-7 - reserved
 */
650 651 652 653 654 655
#define EP_STATE_MASK		(0xf)
#define EP_STATE_DISABLED	0
#define EP_STATE_RUNNING	1
#define EP_STATE_HALTED		2
#define EP_STATE_STOPPED	3
#define EP_STATE_ERROR		4
656
/* Mult - Max number of burtst within an interval, in EP companion desc. */
657
#define EP_MULT(p)		(((p) & 0x3) << 8)
658
#define CTX_TO_EP_MULT(p)	(((p) >> 8) & 0x3)
659 660 661
/* bits 10:14 are Max Primary Streams */
/* bit 15 is Linear Stream Array */
/* Interval - period between requests to an endpoint - 125u increments. */
662
#define EP_INTERVAL(p)		(((p) & 0xff) << 16)
663
#define EP_INTERVAL_TO_UFRAMES(p)		(1 << (((p) >> 16) & 0xff))
664
#define CTX_TO_EP_INTERVAL(p)	(((p) >> 16) & 0xff)
665 666 667 668
#define EP_MAXPSTREAMS_MASK	(0x1f << 10)
#define EP_MAXPSTREAMS(p)	(((p) << 10) & EP_MAXPSTREAMS_MASK)
/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
#define	EP_HAS_LSA		(1 << 15)
669 670 671 672 673 674 675 676

/* ep_info2 bitmasks */
/*
 * Force Event - generate transfer events for all TRBs for this endpoint
 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
 */
#define	FORCE_EVENT	(0x1)
#define ERROR_COUNT(p)	(((p) & 0x3) << 1)
677
#define CTX_TO_EP_TYPE(p)	(((p) >> 3) & 0x7)
678 679 680 681 682 683 684 685 686 687 688
#define EP_TYPE(p)	((p) << 3)
#define ISOC_OUT_EP	1
#define BULK_OUT_EP	2
#define INT_OUT_EP	3
#define CTRL_EP		4
#define ISOC_IN_EP	5
#define BULK_IN_EP	6
#define INT_IN_EP	7
/* bit 6 reserved */
/* bit 7 is Host Initiate Disable - for disabling stream selection */
#define MAX_BURST(p)	(((p)&0xff) << 8)
689
#define CTX_TO_MAX_BURST(p)	(((p) >> 8) & 0xff)
690
#define MAX_PACKET(p)	(((p)&0xffff) << 16)
691 692
#define MAX_PACKET_MASK		(0xffff << 16)
#define MAX_PACKET_DECODED(p)	(((p) >> 16) & 0xffff)
693

A
Andiry Xu 已提交
694 695 696 697 698
/* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
 * USB2.0 spec 9.6.6.
 */
#define GET_MAX_PACKET(p)	((p) & 0x7ff)

699 700 701
/* tx_info bitmasks */
#define AVG_TRB_LENGTH_FOR_EP(p)	((p) & 0xffff)
#define MAX_ESIT_PAYLOAD_FOR_EP(p)	(((p) & 0xffff) << 16)
702
#define CTX_TO_MAX_ESIT_PAYLOAD(p)	(((p) >> 16) & 0xffff)
703

704 705
/* deq bitmasks */
#define EP_CTX_CYCLE_MASK		(1 << 0)
706
#define SCTX_DEQ_MASK			(~0xfL)
707

708 709

/**
710 711
 * struct xhci_input_control_context
 * Input control context; see section 6.2.5.
712 713 714 715
 *
 * @drop_context:	set the bit of the endpoint context you want to disable
 * @add_context:	set the bit of the endpoint context you want to enable
 */
716
struct xhci_input_control_ctx {
M
Matt Evans 已提交
717 718 719
	__le32	drop_flags;
	__le32	add_flags;
	__le32	rsvd2[6];
720
};
721

722 723 724 725 726
#define	EP_IS_ADDED(ctrl_ctx, i) \
	(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
#define	EP_IS_DROPPED(ctrl_ctx, i)       \
	(le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))

727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742
/* Represents everything that is needed to issue a command on the command ring.
 * It's useful to pre-allocate these for commands that cannot fail due to
 * out-of-memory errors, like freeing streams.
 */
struct xhci_command {
	/* Input context for changing device state */
	struct xhci_container_ctx	*in_ctx;
	u32				status;
	/* If completion is null, no one is waiting on this command
	 * and the structure can be freed after the command completes.
	 */
	struct completion		*completion;
	union xhci_trb			*command_trb;
	struct list_head		cmd_list;
};

743 744 745 746 747
/* drop context bitmasks */
#define	DROP_EP(x)	(0x1 << x)
/* add context bitmasks */
#define	ADD_EP(x)	(0x1 << x)

748 749
struct xhci_stream_ctx {
	/* 64-bit stream ring address, cycle state, and stream type */
M
Matt Evans 已提交
750
	__le64	stream_ring;
751
	/* offset 0x14 - 0x1f reserved for HC internal use */
M
Matt Evans 已提交
752
	__le32	reserved[2];
753 754 755
};

/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
X
Xenia Ragiadakou 已提交
756
#define	SCT_FOR_CTX(p)		(((p) & 0x7) << 1)
757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787
/* Secondary stream array type, dequeue pointer is to a transfer ring */
#define	SCT_SEC_TR		0
/* Primary stream array type, dequeue pointer is to a transfer ring */
#define	SCT_PRI_TR		1
/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
#define SCT_SSA_8		2
#define SCT_SSA_16		3
#define SCT_SSA_32		4
#define SCT_SSA_64		5
#define SCT_SSA_128		6
#define SCT_SSA_256		7

/* Assume no secondary streams for now */
struct xhci_stream_info {
	struct xhci_ring		**stream_rings;
	/* Number of streams, including stream 0 (which drivers can't use) */
	unsigned int			num_streams;
	/* The stream context array may be bigger than
	 * the number of streams the driver asked for
	 */
	struct xhci_stream_ctx		*stream_ctx_array;
	unsigned int			num_stream_ctxs;
	dma_addr_t			ctx_array_dma;
	/* For mapping physical TRB addresses to segments in stream rings */
	struct radix_tree_root		trb_address_map;
	struct xhci_command		*free_streams_command;
};

#define	SMALL_STREAM_ARRAY_SIZE		256
#define	MEDIUM_STREAM_ARRAY_SIZE	1024

788 789 790 791 792 793 794
/* Some Intel xHCI host controllers need software to keep track of the bus
 * bandwidth.  Keep track of endpoint info here.  Each root port is allocated
 * the full bus bandwidth.  We must also treat TTs (including each port under a
 * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
 * (DMI) also limits the total bandwidth (across all domains) that can be used.
 */
struct xhci_bw_info {
795
	/* ep_interval is zero-based */
796
	unsigned int		ep_interval;
797
	/* mult and num_packets are one-based */
798 799 800 801 802 803 804
	unsigned int		mult;
	unsigned int		num_packets;
	unsigned int		max_packet_size;
	unsigned int		max_esit_payload;
	unsigned int		type;
};

805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846
/* "Block" sizes in bytes the hardware uses for different device speeds.
 * The logic in this part of the hardware limits the number of bits the hardware
 * can use, so must represent bandwidth in a less precise manner to mimic what
 * the scheduler hardware computes.
 */
#define	FS_BLOCK	1
#define	HS_BLOCK	4
#define	SS_BLOCK	16
#define	DMI_BLOCK	32

/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
 * with each byte transferred.  SuperSpeed devices have an initial overhead to
 * set up bursts.  These are in blocks, see above.  LS overhead has already been
 * translated into FS blocks.
 */
#define DMI_OVERHEAD 8
#define DMI_OVERHEAD_BURST 4
#define SS_OVERHEAD 8
#define SS_OVERHEAD_BURST 32
#define HS_OVERHEAD 26
#define FS_OVERHEAD 20
#define LS_OVERHEAD 128
/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
 * of overhead associated with split transfers crossing microframe boundaries.
 * 31 blocks is pure protocol overhead.
 */
#define TT_HS_OVERHEAD (31 + 94)
#define TT_DMI_OVERHEAD (25 + 12)

/* Bandwidth limits in blocks */
#define FS_BW_LIMIT		1285
#define TT_BW_LIMIT		1320
#define HS_BW_LIMIT		1607
#define SS_BW_LIMIT_IN		3906
#define DMI_BW_LIMIT_IN		3906
#define SS_BW_LIMIT_OUT		3906
#define DMI_BW_LIMIT_OUT	3906

/* Percentage of bus bandwidth reserved for non-periodic transfers */
#define FS_BW_RESERVED		10
#define HS_BW_RESERVED		20
S
Sarah Sharp 已提交
847
#define SS_BW_RESERVED		10
848

849 850
struct xhci_virt_ep {
	struct xhci_ring		*ring;
851 852
	/* Related to endpoints that are configured to use stream IDs only */
	struct xhci_stream_info		*stream_info;
853 854 855 856 857 858
	/* Temporary storage in case the configure endpoint command fails and we
	 * have to restore the device state to the previous state
	 */
	struct xhci_ring		*new_ring;
	unsigned int			ep_state;
#define SET_DEQ_PENDING		(1 << 0)
859 860
#define EP_HALTED		(1 << 1)	/* For stall handling */
#define EP_HALT_PENDING		(1 << 2)	/* For URB cancellation */
861 862 863 864 865
/* Transitioning the endpoint to using streams, don't enqueue URBs */
#define EP_GETTING_STREAMS	(1 << 3)
#define EP_HAS_STREAMS		(1 << 4)
/* Transitioning the endpoint to not using streams, don't enqueue URBs */
#define EP_GETTING_NO_STREAMS	(1 << 5)
866 867 868 869 870
	/* ----  Related to URB cancellation ---- */
	struct list_head	cancelled_td_list;
	/* The TRB that was last reported in a stopped endpoint ring */
	union xhci_trb		*stopped_trb;
	struct xhci_td		*stopped_td;
871
	unsigned int		stopped_stream;
872 873 874 875
	/* Watchdog timer for stop endpoint command to cancel URBs */
	struct timer_list	stop_cmd_timer;
	int			stop_cmds_pending;
	struct xhci_hcd		*xhci;
876 877 878 879 880 881
	/* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
	 * command.  We'll need to update the ring's dequeue segment and dequeue
	 * pointer after the command completes.
	 */
	struct xhci_segment	*queued_deq_seg;
	union xhci_trb		*queued_deq_ptr;
882 883 884 885 886 887 888 889
	/*
	 * Sometimes the xHC can not process isochronous endpoint ring quickly
	 * enough, and it will miss some isoc tds on the ring and generate
	 * a Missed Service Error Event.
	 * Set skip flag when receive a Missed Service Error Event and
	 * process the missed tds on the endpoint ring.
	 */
	bool			skip;
890
	/* Bandwidth checking storage */
891
	struct xhci_bw_info	bw_info;
892
	struct list_head	bw_endpoint_list;
893 894
};

895 896 897 898 899 900 901 902
enum xhci_overhead_type {
	LS_OVERHEAD_TYPE = 0,
	FS_OVERHEAD_TYPE,
	HS_OVERHEAD_TYPE,
};

struct xhci_interval_bw {
	unsigned int		num_packets;
903 904 905 906
	/* Sorted by max packet size.
	 * Head of the list is the greatest max packet size.
	 */
	struct list_head	endpoints;
907 908 909 910 911 912 913 914 915
	/* How many endpoints of each speed are present. */
	unsigned int		overhead[3];
};

#define	XHCI_MAX_INTERVAL	16

struct xhci_interval_bw_table {
	unsigned int		interval0_esit_payload;
	struct xhci_interval_bw	interval_bw[XHCI_MAX_INTERVAL];
916 917
	/* Includes reserved bandwidth for async endpoints */
	unsigned int		bw_used;
S
Sarah Sharp 已提交
918 919
	unsigned int		ss_bw_in;
	unsigned int		ss_bw_out;
920 921 922
};


923
struct xhci_virt_device {
924
	struct usb_device		*udev;
925 926 927 928 929 930 931 932
	/*
	 * Commands to the hardware are passed an "input context" that
	 * tells the hardware what to change in its data structures.
	 * The hardware will return changes in an "output context" that
	 * software must allocate for the hardware.  We need to keep
	 * track of input and output contexts separately because
	 * these commands might fail and we don't trust the hardware.
	 */
933
	struct xhci_container_ctx       *out_ctx;
934
	/* Used for addressing devices and configuration changes */
935
	struct xhci_container_ctx       *in_ctx;
936 937 938 939
	/* Rings saved to ensure old alt settings can be re-instated */
	struct xhci_ring		**ring_cache;
	int				num_rings_cached;
#define	XHCI_MAX_RINGS_CACHED	31
940
	struct xhci_virt_ep		eps[31];
941
	struct completion		cmd_completion;
942 943
	/* Status of the last command issued for this device */
	u32				cmd_status;
944
	struct list_head		cmd_list;
945
	u8				fake_port;
946
	u8				real_port;
947 948
	struct xhci_interval_bw_table	*bw_table;
	struct xhci_tt_bw_info		*tt_info;
949 950
	/* The current max exit latency for the enabled USB3 link states. */
	u16				current_mel;
951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972
};

/*
 * For each roothub, keep track of the bandwidth information for each periodic
 * interval.
 *
 * If a high speed hub is attached to the roothub, each TT associated with that
 * hub is a separate bandwidth domain.  The interval information for the
 * endpoints on the devices under that TT will appear in the TT structure.
 */
struct xhci_root_port_bw_info {
	struct list_head		tts;
	unsigned int			num_active_tts;
	struct xhci_interval_bw_table	bw_table;
};

struct xhci_tt_bw_info {
	struct list_head		tt_list;
	int				slot_id;
	int				ttport;
	struct xhci_interval_bw_table	bw_table;
	int				active_eps;
973 974 975
};


976 977 978 979 980 981
/**
 * struct xhci_device_context_array
 * @dev_context_ptr	array of 64-bit DMA addresses for device contexts
 */
struct xhci_device_context_array {
	/* 64-bit device addresses; we only write 32-bit addresses */
M
Matt Evans 已提交
982
	__le64			dev_context_ptrs[MAX_HC_SLOTS];
983 984
	/* private xHCD pointers */
	dma_addr_t	dma;
985
};
986 987 988 989 990 991 992
/* TODO: write function to set the 64-bit device DMA address */
/*
 * TODO: change this to be dynamically sized at HC mem init time since the HC
 * might not be able to handle the maximum number of devices possible.
 */


993 994
struct xhci_transfer_event {
	/* 64-bit buffer address, or immediate data */
M
Matt Evans 已提交
995 996
	__le64	buffer;
	__le32	transfer_len;
997
	/* This field is interpreted differently based on the type of TRB */
M
Matt Evans 已提交
998
	__le32	flags;
999
};
1000

1001 1002 1003 1004
/* Transfer event TRB length bit mask */
/* bits 0:23 */
#define	EVENT_TRB_LEN(p)		((p) & 0xffffff)

1005 1006 1007
/** Transfer Event bit fields **/
#define	TRB_TO_EP_ID(p)	(((p) >> 16) & 0x1f)

1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
/* Completion Code - only applicable for some types of TRBs */
#define	COMP_CODE_MASK		(0xff << 24)
#define GET_COMP_CODE(p)	(((p) & COMP_CODE_MASK) >> 24)
#define COMP_SUCCESS	1
/* Data Buffer Error */
#define COMP_DB_ERR	2
/* Babble Detected Error */
#define COMP_BABBLE	3
/* USB Transaction Error */
#define COMP_TX_ERR	4
/* TRB Error - some TRB field is invalid */
#define COMP_TRB_ERR	5
/* Stall Error - USB device is stalled */
#define COMP_STALL	6
/* Resource Error - HC doesn't have memory for that device configuration */
#define COMP_ENOMEM	7
/* Bandwidth Error - not enough room in schedule for this dev config */
#define COMP_BW_ERR	8
/* No Slots Available Error - HC ran out of device slots */
#define COMP_ENOSLOTS	9
/* Invalid Stream Type Error */
#define COMP_STREAM_ERR	10
/* Slot Not Enabled Error - doorbell rung for disabled device slot */
#define COMP_EBADSLT	11
/* Endpoint Not Enabled Error */
#define COMP_EBADEP	12
/* Short Packet */
#define COMP_SHORT_TX	13
/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
#define COMP_UNDERRUN	14
/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
#define COMP_OVERRUN	15
/* Virtual Function Event Ring Full Error */
#define COMP_VF_FULL	16
/* Parameter Error - Context parameter is invalid */
#define COMP_EINVAL	17
/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
#define COMP_BW_OVER	18
/* Context State Error - illegal context state transition requested */
#define COMP_CTX_STATE	19
/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
#define COMP_PING_ERR	20
/* Event Ring is full */
#define COMP_ER_FULL	21
A
Alex He 已提交
1052 1053
/* Incompatible Device Error */
#define COMP_DEV_ERR	22
1054 1055 1056 1057 1058 1059 1060 1061
/* Missed Service Error - HC couldn't service an isoc ep within interval */
#define COMP_MISSED_INT	23
/* Successfully stopped command ring */
#define COMP_CMD_STOP	24
/* Successfully aborted current command and stopped command ring */
#define COMP_CMD_ABORT	25
/* Stopped - transfer was terminated by a stop endpoint command */
#define COMP_STOP	26
L
Lucas De Marchi 已提交
1062
/* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1063 1064 1065
#define COMP_STOP_INVAL	27
/* Control Abort Error - Debug Capability - control pipe aborted */
#define COMP_DBG_ABORT	28
1066 1067 1068
/* Max Exit Latency Too Large Error */
#define COMP_MEL_ERR	29
/* TRB type 30 reserved */
1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
#define COMP_BUFF_OVER	31
/* Event Lost Error - xHC has an "internal event overrun condition" */
#define COMP_ISSUES	32
/* Undefined Error - reported when other error codes don't apply */
#define COMP_UNKNOWN	33
/* Invalid Stream ID Error */
#define COMP_STRID_ERR	34
/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
#define COMP_2ND_BW_ERR	35
/* Split Transaction Error */
#define	COMP_SPLIT_ERR	36

struct xhci_link_trb {
	/* 64-bit segment pointer*/
M
Matt Evans 已提交
1084 1085 1086
	__le64 segment_ptr;
	__le32 intr_target;
	__le32 control;
1087
};
1088 1089 1090 1091

/* control bitfields */
#define LINK_TOGGLE	(0x1<<1)

1092 1093 1094
/* Command completion event TRB */
struct xhci_event_cmd {
	/* Pointer to command TRB, or the value passed by the event data trb */
M
Matt Evans 已提交
1095 1096 1097
	__le64 cmd_trb;
	__le32 status;
	__le32 flags;
1098
};
1099

1100
/* flags bitmasks */
1101 1102 1103 1104 1105 1106 1107 1108

/* Address device - disable SetAddress */
#define TRB_BSR		(1<<9)
enum xhci_setup_dev {
	SETUP_CONTEXT_ONLY,
	SETUP_CONTEXT_ADDRESS,
};

1109 1110 1111 1112
/* bits 16:23 are the virtual function ID */
/* bits 24:31 are the slot ID */
#define TRB_TO_SLOT_ID(p)	(((p) & (0xff<<24)) >> 24)
#define SLOT_ID_FOR_TRB(p)	(((p) & 0xff) << 24)
1113

1114 1115 1116 1117
/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
#define TRB_TO_EP_INDEX(p)		((((p) & (0x1f << 16)) >> 16) - 1)
#define	EP_ID_FOR_TRB(p)		((((p) + 1) & 0x1f) << 16)

1118 1119 1120 1121
#define SUSPEND_PORT_FOR_TRB(p)		(((p) & 1) << 23)
#define TRB_TO_SUSPEND_PORT(p)		(((p) & (1 << 23)) >> 23)
#define LAST_EP_INDEX			30

1122
/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1123 1124
#define TRB_TO_STREAM_ID(p)		((((p) & (0xffff << 16)) >> 16))
#define STREAM_ID_FOR_TRB(p)		((((p)) & 0xffff) << 16)
1125
#define SCT_FOR_TRB(p)			(((p) << 1) & 0x7)
1126

1127

S
Sarah Sharp 已提交
1128 1129 1130 1131
/* Port Status Change Event TRB fields */
/* Port ID - bits 31:24 */
#define GET_PORT_ID(p)		(((p) & (0xff << 24)) >> 24)

1132 1133 1134 1135 1136 1137
/* Normal TRB fields */
/* transfer_len bitmasks - bits 0:16 */
#define	TRB_LEN(p)		((p) & 0x1ffff)
/* Interrupter Target - which MSI-X vector to target the completion event at */
#define TRB_INTR_TARGET(p)	(((p) & 0x3ff) << 22)
#define GET_INTR_TARGET(p)	(((p) >> 22) & 0x3ff)
1138
#define TRB_TBC(p)		(((p) & 0x3) << 7)
1139
#define TRB_TLBPC(p)		(((p) & 0xf) << 16)
1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158

/* Cycle bit - indicates TRB ownership by HC or HCD */
#define TRB_CYCLE		(1<<0)
/*
 * Force next event data TRB to be evaluated before task switch.
 * Used to pass OS data back after a TD completes.
 */
#define TRB_ENT			(1<<1)
/* Interrupt on short packet */
#define TRB_ISP			(1<<2)
/* Set PCIe no snoop attribute */
#define TRB_NO_SNOOP		(1<<3)
/* Chain multiple TRBs into a TD */
#define TRB_CHAIN		(1<<4)
/* Interrupt on completion */
#define TRB_IOC			(1<<5)
/* The buffer pointer contains immediate data */
#define TRB_IDT			(1<<6)

1159 1160
/* Block Event Interrupt */
#define	TRB_BEI			(1<<9)
1161 1162 1163

/* Control transfer TRB specific fields */
#define TRB_DIR_IN		(1<<16)
1164 1165 1166
#define	TRB_TX_TYPE(p)		((p) << 16)
#define	TRB_DATA_OUT		2
#define	TRB_DATA_IN		3
1167

1168 1169 1170
/* Isochronous TRB specific fields */
#define TRB_SIA			(1<<31)

1171
struct xhci_generic_trb {
M
Matt Evans 已提交
1172
	__le32 field[4];
1173
};
1174 1175 1176 1177 1178 1179 1180 1181

union xhci_trb {
	struct xhci_link_trb		link;
	struct xhci_transfer_event	trans_event;
	struct xhci_event_cmd		event_cmd;
	struct xhci_generic_trb		generic;
};

1182 1183 1184
/* TRB bit mask */
#define	TRB_TYPE_BITMASK	(0xfc00)
#define TRB_TYPE(p)		((p) << 10)
1185
#define TRB_FIELD_TO_TYPE(p)	(((p) & TRB_TYPE_BITMASK) >> 10)
1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212
/* TRB type IDs */
/* bulk, interrupt, isoc scatter/gather, and control data stage */
#define TRB_NORMAL		1
/* setup stage for control transfers */
#define TRB_SETUP		2
/* data stage for control transfers */
#define TRB_DATA		3
/* status stage for control transfers */
#define TRB_STATUS		4
/* isoc transfers */
#define TRB_ISOC		5
/* TRB for linking ring segments */
#define TRB_LINK		6
#define TRB_EVENT_DATA		7
/* Transfer Ring No-op (not for the command ring) */
#define TRB_TR_NOOP		8
/* Command TRBs */
/* Enable Slot Command */
#define TRB_ENABLE_SLOT		9
/* Disable Slot Command */
#define TRB_DISABLE_SLOT	10
/* Address Device Command */
#define TRB_ADDR_DEV		11
/* Configure Endpoint Command */
#define TRB_CONFIG_EP		12
/* Evaluate Context Command */
#define TRB_EVAL_CONTEXT	13
1213 1214
/* Reset Endpoint Command */
#define TRB_RESET_EP		14
1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252
/* Stop Transfer Ring Command */
#define TRB_STOP_RING		15
/* Set Transfer Ring Dequeue Pointer Command */
#define TRB_SET_DEQ		16
/* Reset Device Command */
#define TRB_RESET_DEV		17
/* Force Event Command (opt) */
#define TRB_FORCE_EVENT		18
/* Negotiate Bandwidth Command (opt) */
#define TRB_NEG_BANDWIDTH	19
/* Set Latency Tolerance Value Command (opt) */
#define TRB_SET_LT		20
/* Get port bandwidth Command */
#define TRB_GET_BW		21
/* Force Header Command - generate a transaction or link management packet */
#define TRB_FORCE_HEADER	22
/* No-op Command - not for transfer rings */
#define TRB_CMD_NOOP		23
/* TRB IDs 24-31 reserved */
/* Event TRBS */
/* Transfer Event */
#define TRB_TRANSFER		32
/* Command Completion Event */
#define TRB_COMPLETION		33
/* Port Status Change Event */
#define TRB_PORT_STATUS		34
/* Bandwidth Request Event (opt) */
#define TRB_BANDWIDTH_EVENT	35
/* Doorbell Event (opt) */
#define TRB_DOORBELL		36
/* Host Controller Event */
#define TRB_HC_EVENT		37
/* Device Notification Event - device sent function wake notification */
#define TRB_DEV_NOTE		38
/* MFINDEX Wrap Event - microframe counter wrapped */
#define TRB_MFINDEX_WRAP	39
/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */

1253 1254 1255 1256 1257
/* Nec vendor-specific command completion event. */
#define	TRB_NEC_CMD_COMP	48
/* Get NEC firmware revision. */
#define	TRB_NEC_GET_FW		49

1258 1259 1260 1261 1262 1263 1264
#define TRB_TYPE_LINK(x)	(((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
/* Above, but for __le32 types -- can avoid work by swapping constants: */
#define TRB_TYPE_LINK_LE32(x)	(((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
				 cpu_to_le32(TRB_TYPE(TRB_LINK)))
#define TRB_TYPE_NOOP_LE32(x)	(((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
				 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))

1265 1266 1267
#define NEC_FW_MINOR(p)		(((p) >> 0) & 0xff)
#define NEC_FW_MAJOR(p)		(((p) >> 8) & 0xff)

1268 1269 1270 1271 1272
/*
 * TRBS_PER_SEGMENT must be a multiple of 4,
 * since the command ring is 64-byte aligned.
 * It must also be greater than 16.
 */
1273
#define TRBS_PER_SEGMENT	64
1274 1275
/* Allow two commands + a link TRB, along with any reserved command TRBs */
#define MAX_RSVD_CMD_TRBS	(TRBS_PER_SEGMENT - 3)
1276 1277
#define TRB_SEGMENT_SIZE	(TRBS_PER_SEGMENT*16)
#define TRB_SEGMENT_SHIFT	(ilog2(TRB_SEGMENT_SIZE))
S
Sarah Sharp 已提交
1278 1279 1280
/* TRB buffer pointers can't cross 64KB boundaries */
#define TRB_MAX_BUFF_SHIFT		16
#define TRB_MAX_BUFF_SIZE	(1 << TRB_MAX_BUFF_SHIFT)
1281 1282 1283 1284 1285 1286

struct xhci_segment {
	union xhci_trb		*trbs;
	/* private to HCD */
	struct xhci_segment	*next;
	dma_addr_t		dma;
1287
};
1288

1289 1290 1291 1292 1293 1294 1295 1296 1297
struct xhci_td {
	struct list_head	td_list;
	struct list_head	cancelled_td_list;
	struct urb		*urb;
	struct xhci_segment	*start_seg;
	union xhci_trb		*first_trb;
	union xhci_trb		*last_trb;
};

1298 1299 1300
/* xHCI command default timeout value */
#define XHCI_CMD_DEFAULT_TIMEOUT	(5 * HZ)

1301 1302 1303 1304 1305 1306 1307
/* command descriptor */
struct xhci_cd {
	struct list_head	cancel_cmd_list;
	struct xhci_command	*command;
	union xhci_trb		*cmd_trb;
};

1308 1309 1310 1311 1312 1313
struct xhci_dequeue_state {
	struct xhci_segment *new_deq_seg;
	union xhci_trb *new_deq_ptr;
	int new_cycle_state;
};

A
Andiry Xu 已提交
1314 1315 1316 1317 1318 1319 1320 1321 1322 1323
enum xhci_ring_type {
	TYPE_CTRL = 0,
	TYPE_ISOC,
	TYPE_BULK,
	TYPE_INTR,
	TYPE_STREAM,
	TYPE_COMMAND,
	TYPE_EVENT,
};

1324 1325
struct xhci_ring {
	struct xhci_segment	*first_seg;
1326
	struct xhci_segment	*last_seg;
1327
	union  xhci_trb		*enqueue;
1328 1329
	struct xhci_segment	*enq_seg;
	unsigned int		enq_updates;
1330
	union  xhci_trb		*dequeue;
1331 1332
	struct xhci_segment	*deq_seg;
	unsigned int		deq_updates;
1333
	struct list_head	td_list;
1334 1335 1336 1337 1338 1339
	/*
	 * Write the cycle state into the TRB cycle field to give ownership of
	 * the TRB to the host controller (if we are the producer), or to check
	 * if we own the TRB (if we are the consumer).  See section 4.9.1.
	 */
	u32			cycle_state;
1340
	unsigned int		stream_id;
1341
	unsigned int		num_segs;
1342 1343
	unsigned int		num_trbs_free;
	unsigned int		num_trbs_free_temp;
A
Andiry Xu 已提交
1344
	enum xhci_ring_type	type;
1345
	bool			last_td_was_short;
G
Gerd Hoffmann 已提交
1346
	struct radix_tree_root	*trb_address_map;
1347 1348 1349 1350
};

struct xhci_erst_entry {
	/* 64-bit event ring segment address */
M
Matt Evans 已提交
1351 1352
	__le64	seg_addr;
	__le32	seg_size;
1353
	/* Set to zero */
M
Matt Evans 已提交
1354
	__le32	rsvd;
1355
};
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365

struct xhci_erst {
	struct xhci_erst_entry	*entries;
	unsigned int		num_entries;
	/* xhci->event_ring keeps track of segment dma addresses */
	dma_addr_t		erst_dma_addr;
	/* Num entries the ERST can contain */
	unsigned int		erst_size;
};

1366 1367 1368 1369 1370 1371 1372
struct xhci_scratchpad {
	u64 *sp_array;
	dma_addr_t sp_dma;
	void **sp_buffers;
	dma_addr_t *sp_dma_buffers;
};

1373 1374 1375 1376 1377 1378
struct urb_priv {
	int	length;
	int	td_cnt;
	struct	xhci_td	*td[0];
};

1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
/*
 * Each segment table entry is 4*32bits long.  1K seems like an ok size:
 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
 * meaning 64 ring segments.
 * Initial allocated size of the ERST, in number of entries */
#define	ERST_NUM_SEGS	1
/* Initial allocated size of the ERST, in number of entries */
#define	ERST_SIZE	64
/* Initial number of event segment rings allocated */
#define	ERST_ENTRIES	1
1389 1390
/* Poll every 60 seconds */
#define	POLL_TIMEOUT	60
1391 1392
/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
#define XHCI_STOP_EP_CMD_TIMEOUT	5
1393 1394
/* XXX: Make these module parameters */

1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405
struct s3_save {
	u32	command;
	u32	dev_nt;
	u64	dcbaa_ptr;
	u32	config_reg;
	u32	irq_pending;
	u32	irq_control;
	u32	erst_size;
	u64	erst_base;
	u64	erst_dequeue;
};
1406

A
Andiry Xu 已提交
1407 1408 1409 1410 1411 1412
/* Use for lpm */
struct dev_info {
	u32			dev_id;
	struct	list_head	list;
};

1413 1414 1415 1416 1417 1418 1419 1420
struct xhci_bus_state {
	unsigned long		bus_suspended;
	unsigned long		next_statechange;

	/* Port suspend arrays are indexed by the portnum of the fake roothub */
	/* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
	u32			port_c_suspend;
	u32			suspended_ports;
1421
	u32			port_remote_wakeup;
1422
	unsigned long		resume_done[USB_MAXCHILDREN];
1423 1424
	/* which ports have started to resume */
	unsigned long		resuming_ports;
1425 1426 1427
	/* Which ports are waiting on RExit to U0 transition. */
	unsigned long		rexit_ports;
	struct completion	rexit_done[USB_MAXCHILDREN];
1428 1429
};

1430 1431 1432 1433 1434 1435 1436

/*
 * It can take up to 20 ms to transition from RExit to U0 on the
 * Intel Lynx Point LP xHCI host.
 */
#define	XHCI_MAX_REXIT_TIMEOUT	(20 * 1000)

1437 1438
static inline unsigned int hcd_index(struct usb_hcd *hcd)
{
1439 1440 1441 1442
	if (hcd->speed == HCD_USB3)
		return 0;
	else
		return 1;
1443 1444
}

S
Sarah Sharp 已提交
1445
/* There is one xhci_hcd structure per controller */
1446
struct xhci_hcd {
1447
	struct usb_hcd *main_hcd;
1448
	struct usb_hcd *shared_hcd;
1449 1450 1451 1452
	/* glue to PCI and HCD framework */
	struct xhci_cap_regs __iomem *cap_regs;
	struct xhci_op_regs __iomem *op_regs;
	struct xhci_run_regs __iomem *run_regs;
1453
	struct xhci_doorbell_array __iomem *dba;
1454
	/* Our HCD's current interrupter register set */
1455
	struct	xhci_intr_reg __iomem *ir_set;
1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473

	/* Cached register copies of read-only HC data */
	__u32		hcs_params1;
	__u32		hcs_params2;
	__u32		hcs_params3;
	__u32		hcc_params;

	spinlock_t	lock;

	/* packed release number */
	u8		sbrn;
	u16		hci_version;
	u8		max_slots;
	u8		max_interrupters;
	u8		max_ports;
	u8		isoc_threshold;
	int		event_ring_max;
	int		addr_64;
1474
	/* 4KB min, 128MB max */
1475
	int		page_size;
1476 1477
	/* Valid values are 12 to 20, inclusive */
	int		page_shift;
D
Dong Nguyen 已提交
1478
	/* msi-x vectors */
1479 1480
	int		msix_count;
	struct msix_entry	*msix_entries;
1481
	/* data structures */
1482
	struct xhci_device_context_array *dcbaa;
1483
	struct xhci_ring	*cmd_ring;
E
Elric Fu 已提交
1484 1485 1486 1487
	unsigned int            cmd_ring_state;
#define CMD_RING_STATE_RUNNING         (1 << 0)
#define CMD_RING_STATE_ABORTED         (1 << 1)
#define CMD_RING_STATE_STOPPED         (1 << 2)
1488
	struct list_head        cancel_cmd_list;
1489
	unsigned int		cmd_ring_reserved_trbs;
1490 1491
	struct xhci_ring	*event_ring;
	struct xhci_erst	erst;
1492 1493
	/* Scratchpad */
	struct xhci_scratchpad  *scratchpad;
A
Andiry Xu 已提交
1494 1495
	/* Store LPM test failed devices' information */
	struct list_head	lpm_failed_devs;
1496

1497 1498 1499
	/* slot enabling and address device helpers */
	struct completion	addr_dev;
	int slot_id;
1500 1501
	/* For USB 3.0 LPM enable/disable. */
	struct xhci_command		*lpm_command;
1502 1503
	/* Internal mirror of the HW's dcbaa */
	struct xhci_virt_device	*devs[MAX_HC_SLOTS];
1504 1505
	/* For keeping track of bandwidth domains per roothub. */
	struct xhci_root_port_bw_info	*rh_bw;
1506 1507 1508 1509

	/* DMA pools */
	struct dma_pool	*device_pool;
	struct dma_pool	*segment_pool;
1510 1511
	struct dma_pool	*small_streams_pool;
	struct dma_pool	*medium_streams_pool;
1512

1513 1514
	/* Host controller watchdog timer structures */
	unsigned int		xhc_state;
1515 1516

	u32			command;
1517
	struct s3_save		s3;
1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530
/* Host controller is dying - not responding to commands. "I'm not dead yet!"
 *
 * xHC interrupts have been disabled and a watchdog timer will (or has already)
 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
 * that sees this status (other than the timer that set it) should stop touching
 * hardware immediately.  Interrupt handlers should return immediately when
 * they see this status (any time they drop and re-acquire xhci->lock).
 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
 * putting the TD on the canceled list, etc.
 *
 * There are no reports of xHCI host controllers that display this issue.
 */
#define XHCI_STATE_DYING	(1 << 0)
1531
#define XHCI_STATE_HALTED	(1 << 1)
1532 1533
	/* Statistics */
	int			error_bitmask;
1534 1535
	unsigned int		quirks;
#define	XHCI_LINK_TRB_QUIRK	(1 << 0)
1536
#define XHCI_RESET_EP_QUIRK	(1 << 1)
1537
#define XHCI_NEC_HOST		(1 << 2)
A
Andiry Xu 已提交
1538
#define XHCI_AMD_PLL_FIX	(1 << 3)
1539
#define XHCI_SPURIOUS_SUCCESS	(1 << 4)
1540 1541 1542 1543 1544 1545 1546 1547 1548 1549
/*
 * Certain Intel host controllers have a limit to the number of endpoint
 * contexts they can handle.  Ideally, they would signal that they can't handle
 * anymore endpoint contexts by returning a Resource Error for the Configure
 * Endpoint command, but they don't.  Instead they expect software to keep track
 * of the number of active endpoints for them, across configure endpoint
 * commands, reset device commands, disable slot commands, and address device
 * commands.
 */
#define XHCI_EP_LIMIT_QUIRK	(1 << 5)
1550
#define XHCI_BROKEN_MSI		(1 << 6)
1551
#define XHCI_RESET_ON_RESUME	(1 << 7)
1552
#define	XHCI_SW_BW_CHECKING	(1 << 8)
1553
#define XHCI_AMD_0x96_HOST	(1 << 9)
1554
#define XHCI_TRUST_TX_LENGTH	(1 << 10)
1555
#define XHCI_LPM_SUPPORT	(1 << 11)
1556
#define XHCI_INTEL_HOST		(1 << 12)
1557
#define XHCI_SPURIOUS_REBOOT	(1 << 13)
1558
#define XHCI_COMP_MODE_QUIRK	(1 << 14)
1559
#define XHCI_AVOID_BEI		(1 << 15)
1560
#define XHCI_PLAT		(1 << 16)
1561
#define XHCI_SLOW_SUSPEND	(1 << 17)
1562
#define XHCI_SPURIOUS_WAKEUP	(1 << 18)
1563 1564
	unsigned int		num_active_eps;
	unsigned int		limit_active_eps;
1565 1566
	/* There are two roothubs to keep track of bus suspend info for */
	struct xhci_bus_state   bus_state[2];
1567 1568 1569
	/* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
	u8			*port_array;
	/* Array of pointers to USB 3.0 PORTSC registers */
M
Matt Evans 已提交
1570
	__le32 __iomem		**usb3_ports;
1571 1572
	unsigned int		num_usb3_ports;
	/* Array of pointers to USB 2.0 PORTSC registers */
M
Matt Evans 已提交
1573
	__le32 __iomem		**usb2_ports;
1574
	unsigned int		num_usb2_ports;
A
Andiry Xu 已提交
1575 1576 1577 1578
	/* support xHCI 0.96 spec USB2 software LPM */
	unsigned		sw_lpm_support:1;
	/* support xHCI 1.0 spec USB2 hardware LPM */
	unsigned		hw_lpm_support:1;
1579 1580 1581
	/* cached usb2 extened protocol capabilites */
	u32                     *ext_caps;
	unsigned int            num_ext_caps;
1582 1583 1584 1585 1586
	/* Compliance Mode Recovery Data */
	struct timer_list	comp_mode_recovery_timer;
	u32			port_status_u0;
/* Compliance Mode Timer Triggered every 2 seconds */
#define COMP_MODE_RCVRY_MSECS 2000
1587 1588 1589 1590 1591
};

/* convert between an HCD pointer and the corresponding EHCI_HCD */
static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
{
1592
	return *((struct xhci_hcd **) (hcd->hcd_priv));
1593 1594 1595 1596
}

static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
{
1597
	return xhci->main_hcd;
1598 1599 1600
}

#define xhci_dbg(xhci, fmt, args...) \
1601
	dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1602 1603 1604 1605
#define xhci_err(xhci, fmt, args...) \
	dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
#define xhci_warn(xhci, fmt, args...) \
	dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1606 1607
#define xhci_warn_ratelimited(xhci, fmt, args...) \
	dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1608

1609 1610 1611 1612 1613 1614 1615 1616 1617
/*
 * Registers should always be accessed with double word or quad word accesses.
 *
 * Some xHCI implementations may support 64-bit address pointers.  Registers
 * with 64-bit address pointers should be written to with dword accesses by
 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
 * xHCI implementations that do not support 64-bit address pointers will ignore
 * the high dword, and write order is irrelevant.
 */
1618 1619 1620 1621 1622 1623 1624 1625
static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
		__le64 __iomem *regs)
{
	__u32 __iomem *ptr = (__u32 __iomem *) regs;
	u64 val_lo = readl(ptr);
	u64 val_hi = readl(ptr + 1);
	return val_lo + (val_hi << 32);
}
1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636
static inline void xhci_write_64(struct xhci_hcd *xhci,
				 const u64 val, __le64 __iomem *regs)
{
	__u32 __iomem *ptr = (__u32 __iomem *) regs;
	u32 val_lo = lower_32_bits(val);
	u32 val_hi = upper_32_bits(val);

	writel(val_lo, ptr);
	writel(val_hi, ptr + 1);
}

1637 1638
static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
{
1639
	return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1640 1641
}

1642
/* xHCI debugging */
1643
void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1644
void xhci_print_registers(struct xhci_hcd *xhci);
1645 1646
void xhci_dbg_regs(struct xhci_hcd *xhci);
void xhci_print_run_regs(struct xhci_hcd *xhci);
1647 1648
void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1649
void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1650 1651 1652
void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1653
void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1654
void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1655
char *xhci_get_slot_state(struct xhci_hcd *xhci,
1656
		struct xhci_container_ctx *ctx);
1657 1658 1659
void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
		unsigned int slot_id, unsigned int ep_index,
		struct xhci_virt_ep *ep);
1660 1661
void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
			const char *fmt, ...);
1662

1663
/* xHCI memory management */
1664 1665
void xhci_mem_cleanup(struct xhci_hcd *xhci);
int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1666 1667 1668
void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1669 1670
void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
		struct usb_device *udev);
1671
unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1672
unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1673
unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1674 1675
unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1676
void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1677 1678 1679 1680 1681 1682 1683 1684 1685
void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
		struct xhci_bw_info *ep_bw,
		struct xhci_interval_bw_table *bw_table,
		struct usb_device *udev,
		struct xhci_virt_ep *virt_ep,
		struct xhci_tt_bw_info *tt_info);
void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		int old_active_eps);
1686 1687 1688 1689 1690
void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
void xhci_update_bw_info(struct xhci_hcd *xhci,
		struct xhci_container_ctx *in_ctx,
		struct xhci_input_control_ctx *ctrl_ctx,
		struct xhci_virt_device *virt_dev);
1691
void xhci_endpoint_copy(struct xhci_hcd *xhci,
1692 1693 1694 1695 1696 1697
		struct xhci_container_ctx *in_ctx,
		struct xhci_container_ctx *out_ctx,
		unsigned int ep_index);
void xhci_slot_copy(struct xhci_hcd *xhci,
		struct xhci_container_ctx *in_ctx,
		struct xhci_container_ctx *out_ctx);
1698 1699 1700
int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
		struct usb_device *udev, struct usb_host_endpoint *ep,
		gfp_t mem_flags);
1701
void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
A
Andiry Xu 已提交
1702 1703
int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
				unsigned int num_trbs, gfp_t flags);
1704 1705 1706
void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		unsigned int ep_index);
1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717
struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
		unsigned int num_stream_ctxs,
		unsigned int num_streams, gfp_t flags);
void xhci_free_stream_info(struct xhci_hcd *xhci,
		struct xhci_stream_info *stream_info);
void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
		struct xhci_ep_ctx *ep_ctx,
		struct xhci_stream_info *stream_info);
void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
		struct xhci_ep_ctx *ep_ctx,
		struct xhci_virt_ep *ep);
1718 1719
void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
	struct xhci_virt_device *virt_dev, bool drop_control_ep);
1720 1721 1722 1723 1724 1725 1726
struct xhci_ring *xhci_dma_to_transfer_ring(
		struct xhci_virt_ep *ep,
		u64 address);
struct xhci_ring *xhci_stream_id_to_ring(
		struct xhci_virt_device *dev,
		unsigned int ep_index,
		unsigned int stream_id);
1727
struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1728 1729
		bool allocate_in_ctx, bool allocate_completion,
		gfp_t mem_flags);
1730
void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1731 1732
void xhci_free_command(struct xhci_hcd *xhci,
		struct xhci_command *command);
1733 1734 1735 1736 1737

#ifdef CONFIG_PCI
/* xHCI PCI glue */
int xhci_register_pci(void);
void xhci_unregister_pci(void);
1738 1739 1740
#else
static inline int xhci_register_pci(void) { return 0; }
static inline void xhci_unregister_pci(void) {}
1741 1742
#endif

1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753
#if defined(CONFIG_USB_XHCI_PLATFORM) \
	|| defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
int xhci_register_plat(void);
void xhci_unregister_plat(void);
#else
static inline int xhci_register_plat(void)
{ return 0; }
static inline void xhci_unregister_plat(void)
{  }
#endif

1754
/* xHCI host controller glue */
1755
typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1756
int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1757
		u32 mask, u32 done, int usec);
1758
void xhci_quiesce(struct xhci_hcd *xhci);
1759 1760 1761 1762 1763 1764
int xhci_halt(struct xhci_hcd *xhci);
int xhci_reset(struct xhci_hcd *xhci);
int xhci_init(struct usb_hcd *hcd);
int xhci_run(struct usb_hcd *hcd);
void xhci_stop(struct usb_hcd *hcd);
void xhci_shutdown(struct usb_hcd *hcd);
1765
int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1766 1767

#ifdef	CONFIG_PM
1768 1769
int xhci_suspend(struct xhci_hcd *xhci);
int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1770 1771 1772 1773 1774
#else
#define	xhci_suspend	NULL
#define	xhci_resume	NULL
#endif

1775
int xhci_get_frame(struct usb_hcd *hcd);
1776
irqreturn_t xhci_irq(struct usb_hcd *hcd);
1777
irqreturn_t xhci_msi_irq(int irq, void *hcd);
1778 1779
int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1780 1781 1782 1783
int xhci_alloc_tt_info(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		struct usb_device *hdev,
		struct usb_tt *tt, gfp_t mem_flags);
1784 1785 1786 1787 1788 1789
int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
		struct usb_host_endpoint **eps, unsigned int num_eps,
		unsigned int num_streams, gfp_t mem_flags);
int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
		struct usb_host_endpoint **eps, unsigned int num_eps,
		gfp_t mem_flags);
1790
int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1791
int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev);
A
Andiry Xu 已提交
1792
int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
A
Andiry Xu 已提交
1793 1794
int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
				struct usb_device *udev, int enable);
S
Sarah Sharp 已提交
1795 1796
int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
			struct usb_tt *tt, gfp_t mem_flags);
1797 1798
int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1799 1800
int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1801
void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1802
int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1803 1804
int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1805 1806

/* xHCI ring, segment, TRB, and TD functions */
1807
dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1808 1809 1810
struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
		union xhci_trb *start_trb, union xhci_trb *end_trb,
		dma_addr_t suspect_dma);
1811
int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1812 1813 1814
void xhci_ring_cmd_db(struct xhci_hcd *xhci);
int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1815
		u32 slot_id, enum xhci_setup_dev);
1816 1817
int xhci_queue_vendor_command(struct xhci_hcd *xhci,
		u32 field1, u32 field2, u32 field3, u32 field4);
1818
int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1819
		unsigned int ep_index, int suspend);
1820 1821 1822 1823
int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
		int slot_id, unsigned int ep_index);
int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
		int slot_id, unsigned int ep_index);
1824 1825
int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
		int slot_id, unsigned int ep_index);
1826 1827
int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
		struct urb *urb, int slot_id, unsigned int ep_index);
1828
int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1829
		u32 slot_id, bool command_must_succeed);
1830
int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1831
		u32 slot_id, bool command_must_succeed);
1832 1833
int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
		unsigned int ep_index);
1834
int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1835 1836
void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
		unsigned int slot_id, unsigned int ep_index,
1837 1838
		unsigned int stream_id, struct xhci_td *cur_td,
		struct xhci_dequeue_state *state);
1839
void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1840
		unsigned int slot_id, unsigned int ep_index,
1841
		unsigned int stream_id,
1842
		struct xhci_dequeue_state *deq_state);
1843
void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1844
		struct usb_device *udev, unsigned int ep_index);
1845 1846 1847
void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
		unsigned int slot_id, unsigned int ep_index,
		struct xhci_dequeue_state *deq_state);
1848
void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1849 1850
int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
		union xhci_trb *cmd_trb);
1851 1852
void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
		unsigned int ep_index, unsigned int stream_id);
1853
union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring);
1854

S
Sarah Sharp 已提交
1855
/* xHCI roothub code */
A
Andiry Xu 已提交
1856 1857
void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
				int port_id, u32 link_state);
1858 1859 1860 1861
int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
			struct usb_device *udev, enum usb3_link_state state);
int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
			struct usb_device *udev, enum usb3_link_state state);
A
Andiry Xu 已提交
1862 1863
void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
				int port_id, u32 port_bit);
S
Sarah Sharp 已提交
1864 1865 1866
int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
		char *buf, u16 wLength);
int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1867
int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1868 1869

#ifdef CONFIG_PM
1870 1871
int xhci_bus_suspend(struct usb_hcd *hcd);
int xhci_bus_resume(struct usb_hcd *hcd);
1872 1873 1874 1875 1876
#else
#define	xhci_bus_suspend	NULL
#define	xhci_bus_resume		NULL
#endif	/* CONFIG_PM */

1877
u32 xhci_port_state_to_neutral(u32 state);
1878 1879
int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
		u16 port);
1880
void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
S
Sarah Sharp 已提交
1881

1882 1883 1884 1885 1886
/* xHCI contexts */
struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);

1887 1888 1889
/* xHCI quirks */
bool xhci_compliance_mode_recovery_timer_quirk_check(void);

1890
#endif /* __LINUX_XHCI_HCD_H */