trans.c 74.6 KB
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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
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 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
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 * in the file called COPYING.
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 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
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 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
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#include <linux/pci.h>
#include <linux/pci-aspm.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/sched.h>
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#include <linux/bitops.h>
#include <linux/gfp.h>
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#include <linux/vmalloc.h>
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#include "iwl-drv.h"
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#include "iwl-trans.h"
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#include "iwl-csr.h"
#include "iwl-prph.h"
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#include "iwl-scd.h"
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#include "iwl-agn-hw.h"
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#include "iwl-fw-error-dump.h"
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#include "internal.h"
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#include "iwl-fh.h"
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/* extended range in FW SRAM */
#define IWL_FW_MEM_EXTENDED_START	0x40000
#define IWL_FW_MEM_EXTENDED_END		0x57FFF

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static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (!trans_pcie->fw_mon_page)
		return;

	dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
		       trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
	__free_pages(trans_pcie->fw_mon_page,
		     get_order(trans_pcie->fw_mon_size));
	trans_pcie->fw_mon_page = NULL;
	trans_pcie->fw_mon_phys = 0;
	trans_pcie->fw_mon_size = 0;
}

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static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
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{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	struct page *page = NULL;
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	dma_addr_t phys;
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	u32 size = 0;
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	u8 power;

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	if (!max_power) {
		/* default max_power is maximum */
		max_power = 26;
	} else {
		max_power += 11;
	}

	if (WARN(max_power > 26,
		 "External buffer size for monitor is too big %d, check the FW TLV\n",
		 max_power))
		return;

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	if (trans_pcie->fw_mon_page) {
		dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
					   trans_pcie->fw_mon_size,
					   DMA_FROM_DEVICE);
		return;
	}

	phys = 0;
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	for (power = max_power; power >= 11; power--) {
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		int order;

		size = BIT(power);
		order = get_order(size);
		page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
				   order);
		if (!page)
			continue;

		phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
				    DMA_FROM_DEVICE);
		if (dma_mapping_error(trans->dev, phys)) {
			__free_pages(page, order);
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			page = NULL;
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			continue;
		}
		IWL_INFO(trans,
			 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
			 size, order);
		break;
	}

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	if (WARN_ON_ONCE(!page))
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		return;

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	if (power != max_power)
		IWL_ERR(trans,
			"Sorry - debug buffer is only %luK while you requested %luK\n",
			(unsigned long)BIT(power - 10),
			(unsigned long)BIT(max_power - 10));

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	trans_pcie->fw_mon_page = page;
	trans_pcie->fw_mon_phys = phys;
	trans_pcie->fw_mon_size = size;
}

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static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
{
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
		    ((reg & 0x0000ffff) | (2 << 28)));
	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
}

static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
{
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
		    ((reg & 0x0000ffff) | (3 << 28)));
}

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static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
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{
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	if (trans->cfg->apmg_not_supported)
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		return;

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	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
	else
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
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}

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/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041

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static void iwl_pcie_apm_config(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	u16 lctl;
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	u16 cap;
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	/*
	 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
	 * Check if BIOS (or OS) enabled L1-ASPM on this device.
	 * If so (likely), disable L0S, so device moves directly L0->L1;
	 *    costs negligible amount of power savings.
	 * If not (unlikely), enable L0S, so there is at least some
	 *    power savings, even without L1.
	 */
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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	if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
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		iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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	else
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		iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
	trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
	dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
		 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
		 trans->ltr_enabled ? "En" : "Dis");
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}

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/*
 * Start up NIC's basic functionality after it has been reset
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 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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 * NOTE:  This does not load uCode nor start the embedded processor
 */
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static int iwl_pcie_apm_init(struct iwl_trans *trans)
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{
	int ret = 0;
	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");

	/*
	 * Use "set_bit" below rather than "write", to preserve any hardware
	 * bits already set by default after reset.
	 */

	/* Disable L0S exit timer (platform NMI Work/Around) */
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	if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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	/*
	 * Disable L0s without affecting L1;
	 *  don't wait for ICH L0s (ICH bug W/A)
	 */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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	/* Set FH wait threshold to maximum (HW error during stress W/A) */
	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);

	/*
	 * Enable HAP INTA (interrupt from management bus) to
	 * wake device's PCI Express link L1a -> L0s
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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	iwl_pcie_apm_config(trans);
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	/* Configure analog phase-lock-loop before activating to D0A */
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	if (trans->cfg->base_params->pll_cfg_val)
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		iwl_set_bit(trans, CSR_ANA_PLL_CFG,
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			    trans->cfg->base_params->pll_cfg_val);
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	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is supported, e.g. iwl_write_prph()
	 * and accesses to uCode SRAM.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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	if (ret < 0) {
		IWL_DEBUG_INFO(trans, "Failed to init the card\n");
		goto out;
	}

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	if (trans->cfg->host_interrupt_operation_mode) {
		/*
		 * This is a bit of an abuse - This is needed for 7260 / 3160
		 * only check host_interrupt_operation_mode even if this is
		 * not related to host_interrupt_operation_mode.
		 *
		 * Enable the oscillator to count wake up time for L1 exit. This
		 * consumes slightly more power (100uA) - but allows to be sure
		 * that we wake up from L1 on time.
		 *
		 * This looks weird: read twice the same register, discard the
		 * value, set a bit, and yet again, read that same register
		 * just to discard the value. But that's the way the hardware
		 * seems to like it.
		 */
		iwl_read_prph(trans, OSC_CLK);
		iwl_read_prph(trans, OSC_CLK);
		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
		iwl_read_prph(trans, OSC_CLK);
		iwl_read_prph(trans, OSC_CLK);
	}

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	/*
	 * Enable DMA clock and wait for it to stabilize.
	 *
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	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
	 * bits do not disable clocks.  This preserves any hardware
	 * bits already set by default in "CLK_CTRL_REG" after reset.
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	 */
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	if (!trans->cfg->apmg_not_supported) {
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		iwl_write_prph(trans, APMG_CLK_EN_REG,
			       APMG_CLK_VAL_DMA_CLK_RQT);
		udelay(20);

		/* Disable L1-Active */
		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);

		/* Clear the interrupt in APMG if the NIC is in RFKILL */
		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
			       APMG_RTC_INT_STT_RFKILL);
	}
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	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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out:
	return ret;
}

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/*
 * Enable LP XTAL to avoid HW bug where device may consume much power if
 * FW is not loaded after device reset. LP XTAL is disabled by default
 * after device HW reset. Do it only if XTAL is fed by internal source.
 * Configure device's "persistence" mode to avoid resetting XTAL again when
 * SHRD_HW_RST occurs in S3.
 */
static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
{
	int ret;
	u32 apmg_gp1_reg;
	u32 apmg_xtal_cfg_reg;
	u32 dl_cfg_reg;

	/* Force XTAL ON */
	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
				 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);

	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is possible.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   25000);
	if (WARN_ON(ret < 0)) {
		IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
		/* Release XTAL ON request */
		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
					   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
		return;
	}

	/*
	 * Clear "disable persistence" to avoid LP XTAL resetting when
	 * SHRD_HW_RST is applied in S3.
	 */
	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);

	/*
	 * Force APMG XTAL to be active to prevent its disabling by HW
	 * caused by APMG idle state.
	 */
	apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
						    SHR_APMG_XTAL_CFG_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
				 apmg_xtal_cfg_reg |
				 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);

	/*
	 * Reset entire device again - do controller reset (results in
	 * SHRD_HW_RST). Turn MAC off before proceeding.
	 */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/* Enable LP XTAL by indirect access through CSR */
	apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
				 SHR_APMG_GP1_WF_XTAL_LP_EN |
				 SHR_APMG_GP1_CHICKEN_BIT_SELECT);

	/* Clear delay line clock power up */
	dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
				 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);

	/*
	 * Enable persistence mode to avoid LP XTAL resetting when
	 * SHRD_HW_RST is applied in S3.
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
		    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/* Activates XTAL resources monitor */
	__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
				 CSR_MONITOR_XTAL_RESOURCES);

	/* Release XTAL ON request */
	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
	udelay(10);

	/* Release APMG XTAL */
	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
				 apmg_xtal_cfg_reg &
				 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
}

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static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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{
	int ret = 0;

	/* stop device's busmaster DMA activity */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);

	ret = iwl_poll_bit(trans, CSR_RESET,
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			   CSR_RESET_REG_FLAG_MASTER_DISABLED,
			   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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	if (ret < 0)
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		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");

	IWL_DEBUG_INFO(trans, "stop master\n");

	return ret;
}

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static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
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{
	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");

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	if (op_mode_leave) {
		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
			iwl_pcie_apm_init(trans);

		/* inform ME that we are leaving */
		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
					  APMG_PCIDEV_STT_VAL_WAKE_ME);
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		else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
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			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
				    CSR_HW_IF_CONFIG_REG_PREPARE |
				    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
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			mdelay(1);
			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
		}
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		mdelay(5);
	}

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	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
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	/* Stop device's DMA activity */
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	iwl_pcie_apm_stop_master(trans);
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	if (trans->cfg->lp_xtal_workaround) {
		iwl_pcie_apm_lp_xtal_enable(trans);
		return;
	}

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	/* Reset the entire device */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
}

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static int iwl_pcie_nic_init(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	/* nic_init */
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	spin_lock(&trans_pcie->irq_lock);
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	iwl_pcie_apm_init(trans);
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	spin_unlock(&trans_pcie->irq_lock);
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	iwl_pcie_set_pwr(trans, false);
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	iwl_op_mode_nic_config(trans->op_mode);
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	/* Allocate the RX queue, or reset if it is already allocated */
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	iwl_pcie_rx_init(trans);
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	/* Allocate or reset and init all Tx and Command queues */
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	if (iwl_pcie_tx_init(trans))
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		return -ENOMEM;

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	if (trans->cfg->base_params->shadow_reg_enable) {
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		/* enable shadow regs in HW */
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		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
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		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
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	}

	return 0;
}

#define HW_READY_TIMEOUT (50)

/* Note: returns poll_bit return value, which is >= 0 if success */
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static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
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{
	int ret;

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	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
555
		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
556 557

	/* See if we got it */
558
	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
559 560 561
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   HW_READY_TIMEOUT);
562

563 564 565
	if (ret >= 0)
		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);

566
	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
567 568 569 570
	return ret;
}

/* Note: returns standard 0/-ERROR code */
571
static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
572 573
{
	int ret;
574
	int t = 0;
575
	int iter;
576

577
	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
578

579
	ret = iwl_pcie_set_hw_ready(trans);
580
	/* If the card is ready, exit 0 */
581 582 583
	if (ret >= 0)
		return 0;

584 585 586 587
	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
	msleep(1);

588 589 590 591 592 593 594
	for (iter = 0; iter < 10; iter++) {
		/* If HW is not ready, prepare the conditions to check again */
		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
			    CSR_HW_IF_CONFIG_REG_PREPARE);

		do {
			ret = iwl_pcie_set_hw_ready(trans);
595 596
			if (ret >= 0)
				return 0;
597

598 599 600 601 602
			usleep_range(200, 1000);
			t += 200;
		} while (t < 150000);
		msleep(25);
	}
603

604
	IWL_ERR(trans, "Couldn't prepare the card\n");
605 606 607 608

	return ret;
}

609 610 611
/*
 * ucode
 */
612
static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
J
Johannes Berg 已提交
613
				   dma_addr_t phy_addr, u32 byte_cnt)
614
{
615
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
616 617
	int ret;

618
	trans_pcie->ucode_write_complete = false;
619 620

	iwl_write_direct32(trans,
621 622
			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
623 624

	iwl_write_direct32(trans,
625 626
			   FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
			   dst_addr);
627 628

	iwl_write_direct32(trans,
J
Johannes Berg 已提交
629 630
			   FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
			   phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
631 632

	iwl_write_direct32(trans,
633 634 635
			   FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
			   (iwl_get_dma_hi_addr(phy_addr)
				<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
636 637

	iwl_write_direct32(trans,
638 639 640 641
			   FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
			   FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
642 643

	iwl_write_direct32(trans,
644 645 646 647
			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
648

649 650
	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
				 trans_pcie->ucode_write_complete, 5 * HZ);
651
	if (!ret) {
J
Johannes Berg 已提交
652
		IWL_ERR(trans, "Failed to load firmware chunk!\n");
653 654 655 656 657 658
		return -ETIMEDOUT;
	}

	return 0;
}

659
static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
J
Johannes Berg 已提交
660
			    const struct fw_desc *section)
661
{
J
Johannes Berg 已提交
662 663
	u8 *v_addr;
	dma_addr_t p_addr;
664
	u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
665 666
	int ret = 0;

J
Johannes Berg 已提交
667 668 669
	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
		     section_num);

670 671 672 673 674 675 676 677 678 679
	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
				    GFP_KERNEL | __GFP_NOWARN);
	if (!v_addr) {
		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
		chunk_sz = PAGE_SIZE;
		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
					    &p_addr, GFP_KERNEL);
		if (!v_addr)
			return -ENOMEM;
	}
J
Johannes Berg 已提交
680

681
	for (offset = 0; offset < section->len; offset += chunk_sz) {
682 683
		u32 copy_size, dst_addr;
		bool extended_addr = false;
J
Johannes Berg 已提交
684

685
		copy_size = min_t(u32, chunk_sz, section->len - offset);
686 687 688 689 690 691 692 693 694
		dst_addr = section->offset + offset;

		if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
		    dst_addr <= IWL_FW_MEM_EXTENDED_END)
			extended_addr = true;

		if (extended_addr)
			iwl_set_bits_prph(trans, LMPM_CHICK,
					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
695

J
Johannes Berg 已提交
696
		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
697 698 699 700 701 702 703
		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
						   copy_size);

		if (extended_addr)
			iwl_clear_bits_prph(trans, LMPM_CHICK,
					    LMPM_CHICK_EXTENDED_ADDR_SPACE);

J
Johannes Berg 已提交
704 705 706 707 708
		if (ret) {
			IWL_ERR(trans,
				"Could not load the [%d] uCode section\n",
				section_num);
			break;
D
David Spinadel 已提交
709
		}
J
Johannes Berg 已提交
710 711
	}

712
	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
J
Johannes Berg 已提交
713 714 715
	return ret;
}

716 717 718 719 720 721 722 723 724
/*
 * Driver Takes the ownership on secure machine before FW load
 * and prevent race with the BT load.
 * W/A for ROM bug. (should be remove in the next Si step)
 */
static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
{
	u32 val, loop = 1000;

725 726 727 728 729
	/*
	 * Check the RSA semaphore is accessible.
	 * If the HW isn't locked and the rsa semaphore isn't accessible,
	 * we are in trouble.
	 */
730 731
	val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
	if (val & (BIT(1) | BIT(17))) {
732 733
		IWL_INFO(trans,
			 "can't access the RSA semaphore it is write protected\n");
734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756
		return 0;
	}

	/* take ownership on the AUX IF */
	iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
	iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);

	do {
		iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
		val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
		if (val == 0x1) {
			iwl_write_prph(trans, RSA_ENABLE, 0);
			return 0;
		}

		udelay(10);
		loop--;
	} while (loop > 0);

	IWL_ERR(trans, "Failed to take ownership on secure machine\n");
	return -EIO;
}

757 758 759 760
static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
					   const struct fw_img *image,
					   int cpu,
					   int *first_ucode_section)
761 762
{
	int shift_param;
763 764
	int i, ret = 0, sec_num = 0x1;
	u32 val, last_read_idx = 0;
765 766 767

	if (cpu == 1) {
		shift_param = 0;
768
		*first_ucode_section = 0;
769 770
	} else {
		shift_param = 16;
771
		(*first_ucode_section)++;
772 773
	}

774 775 776
	for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
		last_read_idx = i;

777 778 779 780 781 782
		/*
		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
		 * CPU1 to CPU2.
		 * PAGING_SEPARATOR_SECTION delimiter - separate between
		 * CPU2 non paged to CPU2 paging sec.
		 */
783
		if (!image->sec[i].data ||
784 785
		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
786 787 788
			IWL_DEBUG_FW(trans,
				     "Break since Data not valid or Empty section, sec = %d\n",
				     i);
789
			break;
790 791
		}

792 793 794
		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
		if (ret)
			return ret;
795 796 797 798 799 800

		/* Notify the ucode of the loaded section number and status */
		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
		val = val | (sec_num << shift_param);
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
		sec_num = (sec_num << 1) | 0x1;
801 802
	}

803 804
	*first_ucode_section = last_read_idx;

805 806 807 808 809
	if (cpu == 1)
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
	else
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);

810 811
	return 0;
}
812

813 814
static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
				      const struct fw_img *image,
815 816
				      int cpu,
				      int *first_ucode_section)
817 818 819
{
	int shift_param;
	int i, ret = 0;
820
	u32 last_read_idx = 0;
821 822 823

	if (cpu == 1) {
		shift_param = 0;
824
		*first_ucode_section = 0;
825 826
	} else {
		shift_param = 16;
827
		(*first_ucode_section)++;
828 829
	}

830 831 832
	for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
		last_read_idx = i;

833 834 835 836 837 838
		/*
		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
		 * CPU1 to CPU2.
		 * PAGING_SEPARATOR_SECTION delimiter - separate between
		 * CPU2 non paged to CPU2 paging sec.
		 */
839
		if (!image->sec[i].data ||
840 841
		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
842 843 844
			IWL_DEBUG_FW(trans,
				     "Break since Data not valid or Empty section, sec = %d\n",
				     i);
845
			break;
846 847
		}

848 849 850
		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
		if (ret)
			return ret;
851 852
	}

853 854 855 856 857 858 859 860
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		iwl_set_bits_prph(trans,
				  CSR_UCODE_LOAD_STATUS_ADDR,
				  (LMPM_CPU_UCODE_LOADING_COMPLETED |
				   LMPM_CPU_HDRS_LOADING_COMPLETED |
				   LMPM_CPU_UCODE_LOADING_STARTED) <<
					shift_param);

861 862
	*first_ucode_section = last_read_idx;

863 864 865
	return 0;
}

866 867 868 869 870 871 872 873 874 875 876 877 878 879 880
static void iwl_pcie_apply_destination(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
	int i;

	if (dest->version)
		IWL_ERR(trans,
			"DBG DEST version is %d - expect issues\n",
			dest->version);

	IWL_INFO(trans, "Applying debug destination %s\n",
		 get_fw_dbg_mode_string(dest->monitor_mode));

	if (dest->monitor_mode == EXTERNAL_MODE)
881
		iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907
	else
		IWL_WARN(trans, "PCI should have external buffer debug\n");

	for (i = 0; i < trans->dbg_dest_reg_num; i++) {
		u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
		u32 val = le32_to_cpu(dest->reg_ops[i].val);

		switch (dest->reg_ops[i].op) {
		case CSR_ASSIGN:
			iwl_write32(trans, addr, val);
			break;
		case CSR_SETBIT:
			iwl_set_bit(trans, addr, BIT(val));
			break;
		case CSR_CLEARBIT:
			iwl_clear_bit(trans, addr, BIT(val));
			break;
		case PRPH_ASSIGN:
			iwl_write_prph(trans, addr, val);
			break;
		case PRPH_SETBIT:
			iwl_set_bits_prph(trans, addr, BIT(val));
			break;
		case PRPH_CLEARBIT:
			iwl_clear_bits_prph(trans, addr, BIT(val));
			break;
908 909 910 911 912 913 914 915
		case PRPH_BLOCKBIT:
			if (iwl_read_prph(trans, addr) & BIT(val)) {
				IWL_ERR(trans,
					"BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
					val, addr);
				goto monitor;
			}
			break;
916 917 918 919 920 921 922
		default:
			IWL_ERR(trans, "FW debug - unknown OP %d\n",
				dest->reg_ops[i].op);
			break;
		}
	}

923
monitor:
924 925 926 927 928 929 930 931 932
	if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
			       trans_pcie->fw_mon_phys >> dest->base_shift);
		iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
			       (trans_pcie->fw_mon_phys +
				trans_pcie->fw_mon_size) >> dest->end_shift);
	}
}

933
static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
934
				const struct fw_img *image)
935
{
936
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
937
	int ret = 0;
938
	int first_ucode_section;
939

940
	IWL_DEBUG_FW(trans, "working with %s CPU\n",
941 942
		     image->is_dual_cpus ? "Dual" : "Single");

943 944 945 946
	/* load to FW the binary non secured sections of CPU1 */
	ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
	if (ret)
		return ret;
947 948

	if (image->is_dual_cpus) {
949 950 951 952
		/* set CPU2 header address */
		iwl_write_prph(trans,
			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
953

954
		/* load to FW the binary sections of CPU2 */
955 956
		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
						 &first_ucode_section);
957 958
		if (ret)
			return ret;
959
	}
960

961 962 963
	/* supported for 7000 only for the moment */
	if (iwlwifi_mod_params.fw_monitor &&
	    trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
964
		iwl_pcie_alloc_fw_monitor(trans, 0);
965 966 967 968 969 970 971 972

		if (trans_pcie->fw_mon_size) {
			iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
				       trans_pcie->fw_mon_phys >> 4);
			iwl_write_prph(trans, MON_BUFF_END_ADDR,
				       (trans_pcie->fw_mon_phys +
					trans_pcie->fw_mon_size) >> 4);
		}
973 974
	} else if (trans->dbg_dest_tlv) {
		iwl_pcie_apply_destination(trans);
975 976
	}

977
	/* release CPU reset */
978
	iwl_write32(trans, CSR_RESET, 0);
979

980 981
	return 0;
}
982

983 984
static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
					  const struct fw_img *image)
985 986 987 988 989 990 991
{
	int ret = 0;
	int first_ucode_section;

	IWL_DEBUG_FW(trans, "working with %s CPU\n",
		     image->is_dual_cpus ? "Dual" : "Single");

992 993 994
	if (trans->dbg_dest_tlv)
		iwl_pcie_apply_destination(trans);

995 996 997 998 999
	/* TODO: remove in the next Si step */
	ret = iwl_pcie_rsa_race_bug_wa(trans);
	if (ret)
		return ret;

1000 1001 1002 1003 1004
	/* configure the ucode to be ready to get the secured image */
	/* release CPU reset */
	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);

	/* load to FW the binary Secured sections of CPU1 */
1005 1006
	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
					      &first_ucode_section);
1007 1008 1009 1010
	if (ret)
		return ret;

	/* load to FW the binary sections of CPU2 */
1011 1012
	return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
					       &first_ucode_section);
1013 1014
}

1015
static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1016
				   const struct fw_img *fw, bool run_in_rfkill)
1017
{
1018
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1019
	bool hw_rfkill;
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030
	int ret;

	mutex_lock(&trans_pcie->mutex);

	/* Someone called stop_device, don't try to start_fw */
	if (trans_pcie->is_down) {
		IWL_WARN(trans,
			 "Can't start_fw since the HW hasn't been started\n");
		ret = EIO;
		goto out;
	}
1031

1032
	/* This may fail if AMT took ownership of the device */
1033
	if (iwl_pcie_prepare_card_hw(trans)) {
1034
		IWL_WARN(trans, "Exit HW not ready\n");
1035 1036
		ret = -EIO;
		goto out;
1037 1038
	}

1039 1040
	iwl_enable_rfkill_int(trans);

1041
	/* If platform's RF_KILL switch is NOT set to KILL */
1042
	hw_rfkill = iwl_is_rfkill_set(trans);
1043
	if (hw_rfkill)
1044
		set_bit(STATUS_RFKILL, &trans->status);
1045
	else
1046
		clear_bit(STATUS_RFKILL, &trans->status);
1047
	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1048 1049 1050 1051
	if (hw_rfkill && !run_in_rfkill) {
		ret = -ERFKILL;
		goto out;
	}
1052

1053
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1054

1055
	ret = iwl_pcie_nic_init(trans);
1056
	if (ret) {
1057
		IWL_ERR(trans, "Unable to init nic\n");
1058
		goto out;
1059 1060 1061
	}

	/* make sure rfkill handshake bits are cleared */
1062 1063
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1064 1065 1066
		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);

	/* clear (again), then enable host interrupts */
1067
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1068
	iwl_enable_interrupts(trans);
1069 1070

	/* really make sure rfkill handshake bits are cleared */
1071 1072
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1073

1074
	/* Load the given image to the HW */
1075
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1076
		ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1077
	else
1078 1079 1080 1081 1082
		ret = iwl_pcie_load_given_ucode(trans, fw);

out:
	mutex_unlock(&trans_pcie->mutex);
	return ret;
1083 1084
}

1085
static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1086
{
1087
	iwl_pcie_reset_ict(trans);
1088
	iwl_pcie_tx_start(trans, scd_addr);
1089 1090
}

1091
static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1092
{
1093
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1094 1095
	bool hw_rfkill, was_hw_rfkill;

1096 1097 1098 1099 1100 1101 1102
	lockdep_assert_held(&trans_pcie->mutex);

	if (trans_pcie->is_down)
		return;

	trans_pcie->is_down = true;

1103
	was_hw_rfkill = iwl_is_rfkill_set(trans);
1104

1105
	/* tell the device to stop sending interrupts */
1106
	spin_lock(&trans_pcie->irq_lock);
1107
	iwl_disable_interrupts(trans);
1108
	spin_unlock(&trans_pcie->irq_lock);
1109

1110
	/* device going down, Stop using ICT table */
1111
	iwl_pcie_disable_ict(trans);
1112 1113 1114 1115 1116 1117 1118 1119

	/*
	 * If a HW restart happens during firmware loading,
	 * then the firmware loading might call this function
	 * and later it might be called again due to the
	 * restart. So don't process again if the device is
	 * already dead.
	 */
1120 1121
	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
		IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1122
		iwl_pcie_tx_stop(trans);
1123
		iwl_pcie_rx_stop(trans);
1124

1125
		/* Power-down device's busmaster DMA clocks */
1126
		if (!trans->cfg->apmg_not_supported) {
1127 1128 1129 1130
			iwl_write_prph(trans, APMG_CLK_DIS_REG,
				       APMG_CLK_VAL_DMA_CLK_RQT);
			udelay(5);
		}
1131 1132 1133
	}

	/* Make sure (redundant) we've released our request to stay awake */
1134
	iwl_clear_bit(trans, CSR_GP_CNTRL,
1135
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1136 1137

	/* Stop the device, and put it in low power state */
1138
	iwl_pcie_apm_stop(trans, false);
1139

1140 1141 1142 1143 1144 1145 1146 1147 1148 1149
	/* stop and reset the on-board processor */
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
	udelay(20);

	/*
	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
	 * This is a bug in certain verions of the hardware.
	 * Certain devices also keep sending HW RF kill interrupt all
	 * the time, unless the interrupt is ACKed even if the interrupt
	 * should be masked. Re-ACK all the interrupts here.
1150
	 */
1151
	spin_lock(&trans_pcie->irq_lock);
1152
	iwl_disable_interrupts(trans);
1153
	spin_unlock(&trans_pcie->irq_lock);
1154

D
Don Fry 已提交
1155 1156

	/* clear all status bits */
1157 1158 1159 1160
	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
	clear_bit(STATUS_INT_ENABLED, &trans->status);
	clear_bit(STATUS_TPOWER_PMI, &trans->status);
	clear_bit(STATUS_RFKILL, &trans->status);
1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172

	/*
	 * Even if we stop the HW, we still want the RF kill
	 * interrupt
	 */
	iwl_enable_rfkill_int(trans);

	/*
	 * Check again since the RF kill state may have changed while
	 * all the interrupts were disabled, in this case we couldn't
	 * receive the RF kill interrupt and update the state in the
	 * op_mode.
1173 1174 1175 1176 1177 1178
	 * Don't call the op_mode if the rkfill state hasn't changed.
	 * This allows the op_mode to call stop_device from the rfkill
	 * notification without endless recursion. Under very rare
	 * circumstances, we might have a small recursion if the rfkill
	 * state changed exactly now while we were called from stop_device.
	 * This is very unlikely but can happen and is supported.
1179 1180 1181
	 */
	hw_rfkill = iwl_is_rfkill_set(trans);
	if (hw_rfkill)
1182
		set_bit(STATUS_RFKILL, &trans->status);
1183
	else
1184
		clear_bit(STATUS_RFKILL, &trans->status);
1185
	if (hw_rfkill != was_hw_rfkill)
1186
		iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1187 1188 1189

	/* re-take ownership to prevent other users from stealing the deivce */
	iwl_pcie_prepare_card_hw(trans);
1190 1191
}

1192 1193 1194 1195 1196 1197 1198 1199 1200
static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	mutex_lock(&trans_pcie->mutex);
	_iwl_trans_pcie_stop_device(trans, low_power);
	mutex_unlock(&trans_pcie->mutex);
}

1201 1202
void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
{
1203 1204 1205 1206 1207
	struct iwl_trans_pcie __maybe_unused *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	lockdep_assert_held(&trans_pcie->mutex);

1208
	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1209
		_iwl_trans_pcie_stop_device(trans, true);
1210 1211
}

1212
static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1213
{
1214 1215
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

1216 1217 1218 1219 1220 1221
	if (trans->wowlan_d0i3) {
		/* Enable persistence mode to avoid reset */
		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
			    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
	}

1222
	iwl_disable_interrupts(trans);
1223 1224 1225 1226 1227 1228 1229 1230

	/*
	 * in testing mode, the host stays awake and the
	 * hardware won't be reset (not even partially)
	 */
	if (test)
		return;

1231 1232
	iwl_pcie_disable_ict(trans);

1233 1234
	synchronize_irq(trans_pcie->pci_dev->irq);

1235 1236
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1237 1238 1239
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

1240 1241 1242 1243 1244 1245 1246 1247
	if (!trans->wowlan_d0i3) {
		/*
		 * reset TX queues -- some of their registers reset during S3
		 * so if we don't reset everything here the D3 image would try
		 * to execute some invalid memory upon resume
		 */
		iwl_trans_pcie_tx_reset(trans);
	}
1248 1249 1250 1251 1252

	iwl_pcie_set_pwr(trans, true);
}

static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1253 1254
				    enum iwl_d3_status *status,
				    bool test)
1255 1256 1257 1258
{
	u32 val;
	int ret;

1259 1260 1261 1262 1263 1264
	if (test) {
		iwl_enable_interrupts(trans);
		*status = IWL_D3_STATUS_ALIVE;
		return 0;
	}

1265 1266 1267 1268 1269 1270 1271 1272 1273 1274
	/*
	 * Also enables interrupts - none will happen as the device doesn't
	 * know we're waking it up, only when the opmode actually tells it
	 * after this call.
	 */
	iwl_pcie_reset_ict(trans);

	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

1275 1276 1277
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		udelay(2);

1278 1279 1280 1281
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   25000);
1282
	if (ret < 0) {
1283 1284 1285 1286
		IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
		return ret;
	}

1287 1288
	iwl_pcie_set_pwr(trans, false);

1289 1290 1291 1292 1293
	if (trans->wowlan_d0i3) {
		iwl_clear_bit(trans, CSR_GP_CNTRL,
			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	} else {
		iwl_trans_pcie_tx_reset(trans);
1294

1295 1296 1297 1298 1299 1300
		ret = iwl_pcie_rx_init(trans);
		if (ret) {
			IWL_ERR(trans,
				"Failed to resume the device (RX reset)\n");
			return ret;
		}
1301 1302
	}

1303 1304 1305 1306 1307 1308
	val = iwl_read32(trans, CSR_RESET);
	if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
		*status = IWL_D3_STATUS_RESET;
	else
		*status = IWL_D3_STATUS_ALIVE;

1309
	return 0;
1310 1311
}

1312
static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1313
{
1314
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1315
	bool hw_rfkill;
J
Johannes Berg 已提交
1316
	int err;
1317

1318 1319
	lockdep_assert_held(&trans_pcie->mutex);

1320
	err = iwl_pcie_prepare_card_hw(trans);
1321
	if (err) {
1322
		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
J
Johannes Berg 已提交
1323
		return err;
1324
	}
1325

1326
	/* Reset the entire device */
1327
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1328 1329 1330

	usleep_range(10, 15);

1331
	iwl_pcie_apm_init(trans);
1332

1333 1334 1335
	/* From now on, the op_mode will be kept updated about RF kill state */
	iwl_enable_rfkill_int(trans);

1336 1337 1338
	/* Set is_down to false here so that...*/
	trans_pcie->is_down = false;

1339
	hw_rfkill = iwl_is_rfkill_set(trans);
1340
	if (hw_rfkill)
1341
		set_bit(STATUS_RFKILL, &trans->status);
1342
	else
1343
		clear_bit(STATUS_RFKILL, &trans->status);
1344
	/* ... rfkill can call stop_device and set it false if needed */
1345
	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1346

J
Johannes Berg 已提交
1347
	return 0;
1348 1349
}

1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361
static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int ret;

	mutex_lock(&trans_pcie->mutex);
	ret = _iwl_trans_pcie_start_hw(trans, low_power);
	mutex_unlock(&trans_pcie->mutex);

	return ret;
}

1362
static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1363
{
1364
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1365

1366 1367
	mutex_lock(&trans_pcie->mutex);

1368
	/* disable interrupts - don't enable HW RF kill interrupt */
1369
	spin_lock(&trans_pcie->irq_lock);
1370
	iwl_disable_interrupts(trans);
1371
	spin_unlock(&trans_pcie->irq_lock);
1372

1373
	iwl_pcie_apm_stop(trans, true);
1374

1375
	spin_lock(&trans_pcie->irq_lock);
1376
	iwl_disable_interrupts(trans);
1377
	spin_unlock(&trans_pcie->irq_lock);
1378

E
Emmanuel Grumbach 已提交
1379
	iwl_pcie_disable_ict(trans);
1380

1381
	mutex_unlock(&trans_pcie->mutex);
1382 1383

	synchronize_irq(trans_pcie->pci_dev->irq);
1384 1385
}

1386 1387
static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
{
1388
	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1389 1390 1391 1392
}

static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
{
1393
	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1394 1395 1396 1397
}

static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
{
1398
	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1399 1400
}

1401 1402
static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
{
A
Amnon Paz 已提交
1403 1404
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
			       ((reg & 0x000FFFFF) | (3 << 24)));
1405 1406 1407 1408 1409 1410 1411
	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
}

static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
				      u32 val)
{
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
A
Amnon Paz 已提交
1412
			       ((addr & 0x000FFFFF) | (3 << 24)));
1413 1414 1415
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
}

1416 1417 1418 1419 1420 1421
static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
{
	WARN_ON(1);
	return 0;
}

1422
static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1423
				     const struct iwl_trans_config *trans_cfg)
1424 1425 1426 1427
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1428
	trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1429
	trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1430 1431 1432 1433 1434 1435 1436
	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
		trans_pcie->n_no_reclaim_cmds = 0;
	else
		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
	if (trans_pcie->n_no_reclaim_cmds)
		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1437

1438 1439 1440
	trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
	trans_pcie->rx_page_order =
		iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1441

1442
	trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1443
	trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1444
	trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1445

1446 1447 1448
	trans->command_groups = trans_cfg->command_groups;
	trans->command_groups_size = trans_cfg->command_groups_size;

1449 1450 1451
	/* init ref_count to 1 (should be cleared when ucode is loaded) */
	trans_pcie->ref_count = 1;

1452 1453 1454 1455 1456
	/* Initialize NAPI here - it should be before registering to mac80211
	 * in the opmode but after the HW struct is allocated.
	 * As this function may be called again in some corner cases don't
	 * do anything if NAPI was already initialized.
	 */
1457
	if (!trans_pcie->napi.poll) {
1458
		init_dummy_netdev(&trans_pcie->napi_dev);
1459 1460
		netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi,
			       iwl_pcie_dummy_napi_poll, 64);
1461
	}
1462 1463
}

1464
void iwl_trans_pcie_free(struct iwl_trans *trans)
1465
{
1466
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1467

1468 1469
	synchronize_irq(trans_pcie->pci_dev->irq);

1470
	iwl_pcie_tx_free(trans);
1471
	iwl_pcie_rx_free(trans);
1472

J
Johannes Berg 已提交
1473 1474
	free_irq(trans_pcie->pci_dev->irq, trans);
	iwl_pcie_free_ict(trans);
1475 1476

	pci_disable_msi(trans_pcie->pci_dev);
1477
	iounmap(trans_pcie->hw_base);
1478 1479 1480
	pci_release_regions(trans_pcie->pci_dev);
	pci_disable_device(trans_pcie->pci_dev);

1481 1482 1483
	if (trans_pcie->napi.poll)
		netif_napi_del(&trans_pcie->napi);

1484 1485
	iwl_pcie_free_fw_monitor(trans);

1486
	iwl_trans_free(trans);
1487 1488
}

D
Don Fry 已提交
1489 1490 1491
static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
{
	if (state)
1492
		set_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
1493
	else
1494
		clear_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
1495 1496
}

1497 1498
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
						unsigned long *flags)
1499 1500
{
	int ret;
1501 1502 1503
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1504

1505
	if (trans_pcie->cmd_hold_nic_awake)
1506 1507
		goto out;

1508
	/* this bit wakes up the NIC */
1509 1510
	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
				 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1511 1512
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		udelay(2);
1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543

	/*
	 * These bits say the device is running, and should keep running for
	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	 * but they do not indicate that embedded SRAM is restored yet;
	 * 3945 and 4965 have volatile SRAM, and must save/restore contents
	 * to/from host DRAM when sleeping/waking for power-saving.
	 * Each direction takes approximately 1/4 millisecond; with this
	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	 * series of register accesses are expected (e.g. reading Event Log),
	 * to keep device from sleeping.
	 *
	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	 * SRAM is okay/restored.  We don't check that here because this call
	 * is just for hardware register access; but GP1 MAC_SLEEP check is a
	 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	 *
	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
	 * and do not save/restore SRAM when power cycling.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
			   (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
			    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	if (unlikely(ret < 0)) {
		iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
		if (!silent) {
			u32 val = iwl_read32(trans, CSR_GP_CNTRL);
			WARN_ONCE(1,
				  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
				  val);
1544
			spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1545 1546 1547 1548
			return false;
		}
	}

1549
out:
1550 1551 1552 1553
	/*
	 * Fool sparse by faking we release the lock - sparse will
	 * track nic_access anyway.
	 */
1554
	__release(&trans_pcie->reg_lock);
1555 1556 1557
	return true;
}

1558 1559
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
					      unsigned long *flags)
1560
{
1561
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1562

1563
	lockdep_assert_held(&trans_pcie->reg_lock);
1564 1565 1566 1567 1568

	/*
	 * Fool sparse by faking we acquiring the lock - sparse will
	 * track nic_access anyway.
	 */
1569
	__acquire(&trans_pcie->reg_lock);
1570

1571
	if (trans_pcie->cmd_hold_nic_awake)
1572 1573
		goto out;

1574 1575
	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1576 1577 1578 1579 1580 1581 1582
	/*
	 * Above we read the CSR_GP_CNTRL register, which will flush
	 * any previous writes, but we need the write that clears the
	 * MAC_ACCESS_REQ bit to be performed before any other writes
	 * scheduled on different CPUs (after we drop reg_lock).
	 */
	mmiowb();
1583
out:
1584
	spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1585 1586
}

1587 1588 1589 1590 1591 1592 1593
static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
				   void *buf, int dwords)
{
	unsigned long flags;
	int offs, ret = 0;
	u32 *vals = buf;

1594
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1595 1596 1597
		iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
		for (offs = 0; offs < dwords; offs++)
			vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1598
		iwl_trans_release_nic_access(trans, &flags);
1599 1600 1601 1602 1603 1604 1605
	} else {
		ret = -EBUSY;
	}
	return ret;
}

static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1606
				    const void *buf, int dwords)
1607 1608 1609
{
	unsigned long flags;
	int offs, ret = 0;
1610
	const u32 *vals = buf;
1611

1612
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1613 1614
		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
		for (offs = 0; offs < dwords; offs++)
E
Emmanuel Grumbach 已提交
1615 1616
			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
				    vals ? vals[offs] : 0);
1617
		iwl_trans_release_nic_access(trans, &flags);
1618 1619 1620 1621 1622
	} else {
		ret = -EBUSY;
	}
	return ret;
}
1623

1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677
static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
					    unsigned long txqs,
					    bool freeze)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int queue;

	for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
		struct iwl_txq *txq = &trans_pcie->txq[queue];
		unsigned long now;

		spin_lock_bh(&txq->lock);

		now = jiffies;

		if (txq->frozen == freeze)
			goto next_queue;

		IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
				    freeze ? "Freezing" : "Waking", queue);

		txq->frozen = freeze;

		if (txq->q.read_ptr == txq->q.write_ptr)
			goto next_queue;

		if (freeze) {
			if (unlikely(time_after(now,
						txq->stuck_timer.expires))) {
				/*
				 * The timer should have fired, maybe it is
				 * spinning right now on the lock.
				 */
				goto next_queue;
			}
			/* remember how long until the timer fires */
			txq->frozen_expiry_remainder =
				txq->stuck_timer.expires - now;
			del_timer(&txq->stuck_timer);
			goto next_queue;
		}

		/*
		 * Wake a non-empty queue -> arm timer with the
		 * remainder before it froze
		 */
		mod_timer(&txq->stuck_timer,
			  now + txq->frozen_expiry_remainder);

next_queue:
		spin_unlock_bh(&txq->lock);
	}
}

1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704
static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int i;

	for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
		struct iwl_txq *txq = &trans_pcie->txq[i];

		if (i == trans_pcie->cmd_queue)
			continue;

		spin_lock_bh(&txq->lock);

		if (!block && !(WARN_ON_ONCE(!txq->block))) {
			txq->block--;
			if (!txq->block) {
				iwl_write32(trans, HBUS_TARG_WRPTR,
					    txq->q.write_ptr | (i << 8));
			}
		} else if (block) {
			txq->block++;
		}

		spin_unlock_bh(&txq->lock);
	}
}

1705 1706
#define IWL_FLUSH_WAIT_MS	2000

1707
static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1708
{
1709
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1710
	struct iwl_txq *txq;
1711 1712 1713
	struct iwl_queue *q;
	int cnt;
	unsigned long now = jiffies;
1714 1715
	u32 scd_sram_addr;
	u8 buf[16];
1716 1717 1718
	int ret = 0;

	/* waiting for all the tx frames complete might take a while */
1719
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1720 1721
		u8 wr_ptr;

W
Wey-Yi Guy 已提交
1722
		if (cnt == trans_pcie->cmd_queue)
1723
			continue;
1724 1725 1726 1727
		if (!test_bit(cnt, trans_pcie->queue_used))
			continue;
		if (!(BIT(cnt) & txq_bm))
			continue;
1728 1729

		IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1730
		txq = &trans_pcie->txq[cnt];
1731
		q = &txq->q;
1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742
		wr_ptr = ACCESS_ONCE(q->write_ptr);

		while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
		       !time_after(jiffies,
				   now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
			u8 write_ptr = ACCESS_ONCE(q->write_ptr);

			if (WARN_ONCE(wr_ptr != write_ptr,
				      "WR pointer moved while flushing %d -> %d\n",
				      wr_ptr, write_ptr))
				return -ETIMEDOUT;
1743
			msleep(1);
1744
		}
1745 1746

		if (q->read_ptr != q->write_ptr) {
1747 1748
			IWL_ERR(trans,
				"fail to flush all tx fifo queues Q %d\n", cnt);
1749 1750 1751
			ret = -ETIMEDOUT;
			break;
		}
1752
		IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1753
	}
1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786

	if (!ret)
		return 0;

	IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
		txq->q.read_ptr, txq->q.write_ptr);

	scd_sram_addr = trans_pcie->scd_base_addr +
			SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
	iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));

	iwl_print_hex_error(trans, buf, sizeof(buf));

	for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
		IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
			iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));

	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
		u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
		u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
		bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
		u32 tbl_dw =
			iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
					     SCD_TRANS_TBL_OFFSET_QUEUE(cnt));

		if (cnt & 0x1)
			tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
		else
			tbl_dw = tbl_dw & 0x0000FFFF;

		IWL_ERR(trans,
			"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
			cnt, active ? "" : "in", fifo, tbl_dw,
1787 1788
			iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
				(TFD_QUEUE_SIZE_MAX - 1),
1789 1790 1791
			iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
	}

1792 1793 1794
	return ret;
}

1795 1796 1797
static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
					 u32 mask, u32 value)
{
1798
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1799 1800
	unsigned long flags;

1801
	spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1802
	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1803
	spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1804 1805
}

1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837
void iwl_trans_pcie_ref(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	unsigned long flags;

	if (iwlwifi_mod_params.d0i3_disable)
		return;

	spin_lock_irqsave(&trans_pcie->ref_lock, flags);
	IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
	trans_pcie->ref_count++;
	spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
}

void iwl_trans_pcie_unref(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	unsigned long flags;

	if (iwlwifi_mod_params.d0i3_disable)
		return;

	spin_lock_irqsave(&trans_pcie->ref_lock, flags);
	IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
	if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
		spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
		return;
	}
	trans_pcie->ref_count--;
	spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
}

1838 1839
static const char *get_csr_string(int cmd)
{
J
Johannes Berg 已提交
1840
#define IWL_CMD(x) case x: return #x
1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863
	switch (cmd) {
	IWL_CMD(CSR_HW_IF_CONFIG_REG);
	IWL_CMD(CSR_INT_COALESCING);
	IWL_CMD(CSR_INT);
	IWL_CMD(CSR_INT_MASK);
	IWL_CMD(CSR_FH_INT_STATUS);
	IWL_CMD(CSR_GPIO_IN);
	IWL_CMD(CSR_RESET);
	IWL_CMD(CSR_GP_CNTRL);
	IWL_CMD(CSR_HW_REV);
	IWL_CMD(CSR_EEPROM_REG);
	IWL_CMD(CSR_EEPROM_GP);
	IWL_CMD(CSR_OTP_GP_REG);
	IWL_CMD(CSR_GIO_REG);
	IWL_CMD(CSR_GP_UCODE_REG);
	IWL_CMD(CSR_GP_DRIVER_REG);
	IWL_CMD(CSR_UCODE_DRV_GP1);
	IWL_CMD(CSR_UCODE_DRV_GP2);
	IWL_CMD(CSR_LED_REG);
	IWL_CMD(CSR_DRAM_INT_TBL_REG);
	IWL_CMD(CSR_GIO_CHICKEN_BITS);
	IWL_CMD(CSR_ANA_PLL_CFG);
	IWL_CMD(CSR_HW_REV_WA_REG);
1864
	IWL_CMD(CSR_MONITOR_STATUS_REG);
1865 1866 1867 1868
	IWL_CMD(CSR_DBG_HPET_MEM_REG);
	default:
		return "UNKNOWN";
	}
J
Johannes Berg 已提交
1869
#undef IWL_CMD
1870 1871
}

1872
void iwl_pcie_dump_csr(struct iwl_trans *trans)
1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896
{
	int i;
	static const u32 csr_tbl[] = {
		CSR_HW_IF_CONFIG_REG,
		CSR_INT_COALESCING,
		CSR_INT,
		CSR_INT_MASK,
		CSR_FH_INT_STATUS,
		CSR_GPIO_IN,
		CSR_RESET,
		CSR_GP_CNTRL,
		CSR_HW_REV,
		CSR_EEPROM_REG,
		CSR_EEPROM_GP,
		CSR_OTP_GP_REG,
		CSR_GIO_REG,
		CSR_GP_UCODE_REG,
		CSR_GP_DRIVER_REG,
		CSR_UCODE_DRV_GP1,
		CSR_UCODE_DRV_GP2,
		CSR_LED_REG,
		CSR_DRAM_INT_TBL_REG,
		CSR_GIO_CHICKEN_BITS,
		CSR_ANA_PLL_CFG,
1897
		CSR_MONITOR_STATUS_REG,
1898 1899 1900 1901 1902 1903 1904 1905 1906
		CSR_HW_REV_WA_REG,
		CSR_DBG_HPET_MEM_REG
	};
	IWL_ERR(trans, "CSR values:\n");
	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
		"CSR_INT_PERIODIC_REG)\n");
	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
		IWL_ERR(trans, "  %25s: 0X%08x\n",
			get_csr_string(csr_tbl[i]),
1907
			iwl_read32(trans, csr_tbl[i]));
1908 1909 1910
	}
}

1911 1912 1913
#ifdef CONFIG_IWLWIFI_DEBUGFS
/* create and remove of files */
#define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
1914
	if (!debugfs_create_file(#name, mode, parent, trans,		\
1915
				 &iwl_dbgfs_##name##_ops))		\
1916
		goto err;						\
1917 1918 1919 1920 1921 1922
} while (0)

/* file operation */
#define DEBUGFS_READ_FILE_OPS(name)					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.read = iwl_dbgfs_##name##_read,				\
1923
	.open = simple_open,						\
1924 1925 1926
	.llseek = generic_file_llseek,					\
};

1927 1928 1929
#define DEBUGFS_WRITE_FILE_OPS(name)                                    \
static const struct file_operations iwl_dbgfs_##name##_ops = {          \
	.write = iwl_dbgfs_##name##_write,                              \
1930
	.open = simple_open,						\
1931 1932 1933
	.llseek = generic_file_llseek,					\
};

1934 1935 1936 1937
#define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.write = iwl_dbgfs_##name##_write,				\
	.read = iwl_dbgfs_##name##_read,				\
1938
	.open = simple_open,						\
1939 1940 1941 1942
	.llseek = generic_file_llseek,					\
};

static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1943 1944
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
1945
{
1946
	struct iwl_trans *trans = file->private_data;
1947
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1948
	struct iwl_txq *txq;
1949 1950 1951 1952 1953
	struct iwl_queue *q;
	char *buf;
	int pos = 0;
	int cnt;
	int ret;
1954 1955
	size_t bufsz;

1956
	bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1957

J
Johannes Berg 已提交
1958
	if (!trans_pcie->txq)
1959
		return -EAGAIN;
J
Johannes Berg 已提交
1960

1961 1962 1963 1964
	buf = kzalloc(bufsz, GFP_KERNEL);
	if (!buf)
		return -ENOMEM;

1965
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1966
		txq = &trans_pcie->txq[cnt];
1967 1968
		q = &txq->q;
		pos += scnprintf(buf + pos, bufsz - pos,
1969
				"hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1970
				cnt, q->read_ptr, q->write_ptr,
1971
				!!test_bit(cnt, trans_pcie->queue_used),
1972
				 !!test_bit(cnt, trans_pcie->queue_stopped),
1973
				 txq->need_update, txq->frozen,
1974
				 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1975 1976 1977 1978 1979 1980 1981
	}
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1982 1983 1984
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
{
1985
	struct iwl_trans *trans = file->private_data;
1986
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1987
	struct iwl_rxq *rxq = &trans_pcie->rxq;
1988 1989 1990 1991 1992 1993 1994 1995
	char buf[256];
	int pos = 0;
	const size_t bufsz = sizeof(buf);

	pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
						rxq->read);
	pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
						rxq->write);
1996 1997 1998 1999
	pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
						rxq->write_actual);
	pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
						rxq->need_update);
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
	pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
						rxq->free_count);
	if (rxq->rb_stts) {
		pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
			 le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
	} else {
		pos += scnprintf(buf + pos, bufsz - pos,
					"closed_rb_num: Not Allocated\n");
	}
	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}

2012 2013
static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
					char __user *user_buf,
2014 2015
					size_t count, loff_t *ppos)
{
2016
	struct iwl_trans *trans = file->private_data;
2017
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2018 2019 2020 2021 2022 2023 2024 2025
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	int pos = 0;
	char *buf;
	int bufsz = 24 * 64; /* 24 items * 64 char per item */
	ssize_t ret;

	buf = kzalloc(bufsz, GFP_KERNEL);
J
Johannes Berg 已提交
2026
	if (!buf)
2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074
		return -ENOMEM;

	pos += scnprintf(buf + pos, bufsz - pos,
			"Interrupt Statistics Report:\n");

	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
		isr_stats->hw);
	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
		isr_stats->sw);
	if (isr_stats->sw || isr_stats->hw) {
		pos += scnprintf(buf + pos, bufsz - pos,
			"\tLast Restarting Code:  0x%X\n",
			isr_stats->err_code);
	}
#ifdef CONFIG_IWLWIFI_DEBUG
	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
		isr_stats->sch);
	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
		isr_stats->alive);
#endif
	pos += scnprintf(buf + pos, bufsz - pos,
		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);

	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
		isr_stats->ctkill);

	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
		isr_stats->wakeup);

	pos += scnprintf(buf + pos, bufsz - pos,
		"Rx command responses:\t\t %u\n", isr_stats->rx);

	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
		isr_stats->tx);

	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
		isr_stats->unhandled);

	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
					 const char __user *user_buf,
					 size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;
2075
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	char buf[8];
	int buf_size;
	u32 reset_flag;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%x", &reset_flag) != 1)
		return -EFAULT;
	if (reset_flag == 0)
		memset(isr_stats, 0, sizeof(*isr_stats));

	return count;
}

2094
static ssize_t iwl_dbgfs_csr_write(struct file *file,
2095 2096
				   const char __user *user_buf,
				   size_t count, loff_t *ppos)
2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109
{
	struct iwl_trans *trans = file->private_data;
	char buf[8];
	int buf_size;
	int csr;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%d", &csr) != 1)
		return -EFAULT;

2110
	iwl_pcie_dump_csr(trans);
2111 2112 2113 2114 2115

	return count;
}

static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2116 2117
				     char __user *user_buf,
				     size_t count, loff_t *ppos)
2118 2119
{
	struct iwl_trans *trans = file->private_data;
2120
	char *buf = NULL;
2121
	ssize_t ret;
2122

2123 2124 2125 2126 2127 2128 2129
	ret = iwl_dump_fh(trans, &buf);
	if (ret < 0)
		return ret;
	if (!buf)
		return -EINVAL;
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
	kfree(buf);
2130 2131 2132
	return ret;
}

2133
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2134
DEBUGFS_READ_FILE_OPS(fh_reg);
2135 2136
DEBUGFS_READ_FILE_OPS(rx_queue);
DEBUGFS_READ_FILE_OPS(tx_queue);
2137
DEBUGFS_WRITE_FILE_OPS(csr);
2138

2139 2140
/* Create the debugfs files and directories */
int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2141
{
2142 2143
	struct dentry *dir = trans->dbgfs_dir;

2144 2145
	DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
	DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2146
	DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2147 2148
	DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
	DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2149
	return 0;
2150 2151 2152 2153

err:
	IWL_ERR(trans, "failed to create the trans debugfs entry\n");
	return -ENOMEM;
2154
}
2155
#endif /*CONFIG_IWLWIFI_DEBUGFS */
2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167

static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
{
	u32 cmdlen = 0;
	int i;

	for (i = 0; i < IWL_NUM_OF_TBS; i++)
		cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);

	return cmdlen;
}

2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208
static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
				   struct iwl_fw_error_dump_data **data,
				   int allocated_rb_nums)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
	struct iwl_rxq *rxq = &trans_pcie->rxq;
	u32 i, r, j, rb_len = 0;

	spin_lock(&rxq->lock);

	r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;

	for (i = rxq->read, j = 0;
	     i != r && j < allocated_rb_nums;
	     i = (i + 1) & RX_QUEUE_MASK, j++) {
		struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
		struct iwl_fw_error_dump_rb *rb;

		dma_unmap_page(trans->dev, rxb->page_dma, max_len,
			       DMA_FROM_DEVICE);

		rb_len += sizeof(**data) + sizeof(*rb) + max_len;

		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
		(*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
		rb = (void *)(*data)->data;
		rb->index = cpu_to_le32(i);
		memcpy(rb->data, page_address(rxb->page), max_len);
		/* remap the page for the free benefit */
		rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
						     max_len,
						     DMA_FROM_DEVICE);

		*data = iwl_fw_error_next_data(*data);
	}

	spin_unlock(&rxq->lock);

	return rb_len;
}
2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229
#define IWL_CSR_TO_DUMP (0x250)

static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
				   struct iwl_fw_error_dump_data **data)
{
	u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
	__le32 *val;
	int i;

	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
	(*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
	val = (void *)(*data)->data;

	for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));

	*data = iwl_fw_error_next_data(*data);

	return csr_len;
}

2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254
static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
				       struct iwl_fw_error_dump_data **data)
{
	u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
	unsigned long flags;
	__le32 *val;
	int i;

	if (!iwl_trans_grab_nic_access(trans, false, &flags))
		return 0;

	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
	(*data)->len = cpu_to_le32(fh_regs_len);
	val = (void *)(*data)->data;

	for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));

	iwl_trans_release_nic_access(trans, &flags);

	*data = iwl_fw_error_next_data(*data);

	return sizeof(**data) + fh_regs_len;
}

2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267
static u32
iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
				 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
				 u32 monitor_len)
{
	u32 buf_size_in_dwords = (monitor_len >> 2);
	u32 *buffer = (u32 *)fw_mon_data->data;
	unsigned long flags;
	u32 i;

	if (!iwl_trans_grab_nic_access(trans, false, &flags))
		return 0;

2268
	iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2269
	for (i = 0; i < buf_size_in_dwords; i++)
2270 2271 2272
		buffer[i] = iwl_read_prph_no_grab(trans,
				MON_DMARB_RD_DATA_ADDR);
	iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2273 2274 2275 2276 2277 2278

	iwl_trans_release_nic_access(trans, &flags);

	return monitor_len;
}

2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359
static u32
iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
			    struct iwl_fw_error_dump_data **data,
			    u32 monitor_len)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	u32 len = 0;

	if ((trans_pcie->fw_mon_page &&
	     trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
	    trans->dbg_dest_tlv) {
		struct iwl_fw_error_dump_fw_mon *fw_mon_data;
		u32 base, write_ptr, wrap_cnt;

		/* If there was a dest TLV - use the values from there */
		if (trans->dbg_dest_tlv) {
			write_ptr =
				le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
			wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
			base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
		} else {
			base = MON_BUFF_BASE_ADDR;
			write_ptr = MON_BUFF_WRPTR;
			wrap_cnt = MON_BUFF_CYCLE_CNT;
		}

		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
		fw_mon_data = (void *)(*data)->data;
		fw_mon_data->fw_mon_wr_ptr =
			cpu_to_le32(iwl_read_prph(trans, write_ptr));
		fw_mon_data->fw_mon_cycle_cnt =
			cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
		fw_mon_data->fw_mon_base_ptr =
			cpu_to_le32(iwl_read_prph(trans, base));

		len += sizeof(**data) + sizeof(*fw_mon_data);
		if (trans_pcie->fw_mon_page) {
			/*
			 * The firmware is now asserted, it won't write anything
			 * to the buffer. CPU can take ownership to fetch the
			 * data. The buffer will be handed back to the device
			 * before the firmware will be restarted.
			 */
			dma_sync_single_for_cpu(trans->dev,
						trans_pcie->fw_mon_phys,
						trans_pcie->fw_mon_size,
						DMA_FROM_DEVICE);
			memcpy(fw_mon_data->data,
			       page_address(trans_pcie->fw_mon_page),
			       trans_pcie->fw_mon_size);

			monitor_len = trans_pcie->fw_mon_size;
		} else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
			/*
			 * Update pointers to reflect actual values after
			 * shifting
			 */
			base = iwl_read_prph(trans, base) <<
			       trans->dbg_dest_tlv->base_shift;
			iwl_trans_read_mem(trans, base, fw_mon_data->data,
					   monitor_len / sizeof(u32));
		} else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
			monitor_len =
				iwl_trans_pci_dump_marbh_monitor(trans,
								 fw_mon_data,
								 monitor_len);
		} else {
			/* Didn't match anything - output no monitor data */
			monitor_len = 0;
		}

		len += monitor_len;
		(*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
	}

	return len;
}

static struct iwl_trans_dump_data
*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
			  struct iwl_fw_dbg_trigger_tlv *trigger)
2360 2361 2362 2363 2364
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	struct iwl_fw_error_dump_data *data;
	struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
	struct iwl_fw_error_dump_txcmd *txcmd;
2365
	struct iwl_trans_dump_data *dump_data;
2366
	u32 len, num_rbs;
2367
	u32 monitor_len;
2368
	int i, ptr;
2369
	bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status);
2370

2371 2372 2373 2374 2375
	/* transport dump header */
	len = sizeof(*dump_data);

	/* host commands */
	len += sizeof(*data) +
2376 2377
		cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);

2378
	/* FW monitor */
2379
	if (trans_pcie->fw_mon_page) {
2380
		len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394
		       trans_pcie->fw_mon_size;
		monitor_len = trans_pcie->fw_mon_size;
	} else if (trans->dbg_dest_tlv) {
		u32 base, end;

		base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
		end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);

		base = iwl_read_prph(trans, base) <<
		       trans->dbg_dest_tlv->base_shift;
		end = iwl_read_prph(trans, end) <<
		      trans->dbg_dest_tlv->end_shift;

		/* Make "end" point to the actual end */
2395 2396
		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
		    trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2397 2398 2399 2400 2401 2402 2403
			end += (1 << trans->dbg_dest_tlv->end_shift);
		monitor_len = end - base;
		len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
		       monitor_len;
	} else {
		monitor_len = 0;
	}
2404

2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433
	if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
		dump_data = vzalloc(len);
		if (!dump_data)
			return NULL;

		data = (void *)dump_data->data;
		len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
		dump_data->len = len;

		return dump_data;
	}

	/* CSR registers */
	len += sizeof(*data) + IWL_CSR_TO_DUMP;

	/* FH registers */
	len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);

	if (dump_rbs) {
		/* RBs */
		num_rbs = le16_to_cpu(ACCESS_ONCE(
				      trans_pcie->rxq.rb_stts->closed_rb_num))
				      & 0x0FFF;
		num_rbs = (num_rbs - trans_pcie->rxq.read) & RX_QUEUE_MASK;
		len += num_rbs * (sizeof(*data) +
				  sizeof(struct iwl_fw_error_dump_rb) +
				  (PAGE_SIZE << trans_pcie->rx_page_order));
	}

2434 2435 2436
	dump_data = vzalloc(len);
	if (!dump_data)
		return NULL;
2437 2438

	len = 0;
2439
	data = (void *)dump_data->data;
2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463
	data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
	txcmd = (void *)data->data;
	spin_lock_bh(&cmdq->lock);
	ptr = cmdq->q.write_ptr;
	for (i = 0; i < cmdq->q.n_window; i++) {
		u8 idx = get_cmd_index(&cmdq->q, ptr);
		u32 caplen, cmdlen;

		cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
		caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);

		if (cmdlen) {
			len += sizeof(*txcmd) + caplen;
			txcmd->cmdlen = cpu_to_le32(cmdlen);
			txcmd->caplen = cpu_to_le32(caplen);
			memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
			txcmd = (void *)((u8 *)txcmd->data + caplen);
		}

		ptr = iwl_queue_dec_wrap(ptr);
	}
	spin_unlock_bh(&cmdq->lock);

	data->len = cpu_to_le32(len);
2464
	len += sizeof(*data);
2465 2466
	data = iwl_fw_error_next_data(data);

2467
	len += iwl_trans_pcie_dump_csr(trans, &data);
2468
	len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2469 2470
	if (dump_rbs)
		len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2471

2472
	len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2473

2474 2475 2476
	dump_data->len = len;

	return dump_data;
2477
}
2478

2479
static const struct iwl_trans_ops trans_ops_pcie = {
2480
	.start_hw = iwl_trans_pcie_start_hw,
2481
	.op_mode_leave = iwl_trans_pcie_op_mode_leave,
2482
	.fw_alive = iwl_trans_pcie_fw_alive,
2483
	.start_fw = iwl_trans_pcie_start_fw,
2484
	.stop_device = iwl_trans_pcie_stop_device,
2485

2486 2487
	.d3_suspend = iwl_trans_pcie_d3_suspend,
	.d3_resume = iwl_trans_pcie_d3_resume,
2488

2489
	.send_cmd = iwl_trans_pcie_send_hcmd,
2490

2491
	.tx = iwl_trans_pcie_tx,
2492
	.reclaim = iwl_trans_pcie_reclaim,
2493

2494
	.txq_disable = iwl_trans_pcie_txq_disable,
2495
	.txq_enable = iwl_trans_pcie_txq_enable,
2496

2497
	.wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2498
	.freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2499
	.block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2500

2501 2502 2503
	.write8 = iwl_trans_pcie_write8,
	.write32 = iwl_trans_pcie_write32,
	.read32 = iwl_trans_pcie_read32,
2504 2505
	.read_prph = iwl_trans_pcie_read_prph,
	.write_prph = iwl_trans_pcie_write_prph,
2506 2507
	.read_mem = iwl_trans_pcie_read_mem,
	.write_mem = iwl_trans_pcie_write_mem,
2508
	.configure = iwl_trans_pcie_configure,
D
Don Fry 已提交
2509
	.set_pmi = iwl_trans_pcie_set_pmi,
2510
	.grab_nic_access = iwl_trans_pcie_grab_nic_access,
2511 2512
	.release_nic_access = iwl_trans_pcie_release_nic_access,
	.set_bits_mask = iwl_trans_pcie_set_bits_mask,
2513

2514 2515 2516
	.ref = iwl_trans_pcie_ref,
	.unref = iwl_trans_pcie_unref,

2517
	.dump_data = iwl_trans_pcie_dump_data,
2518
};
2519

2520
struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2521 2522
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg)
2523 2524 2525 2526
{
	struct iwl_trans_pcie *trans_pcie;
	struct iwl_trans *trans;
	u16 pci_cmd;
2527
	int ret;
2528

2529 2530 2531 2532
	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
				&pdev->dev, cfg, &trans_ops_pcie, 0);
	if (!trans)
		return ERR_PTR(-ENOMEM);
2533

J
Johannes Berg 已提交
2534 2535
	trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;

2536 2537 2538
	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->trans = trans;
J
Johannes Berg 已提交
2539
	spin_lock_init(&trans_pcie->irq_lock);
2540
	spin_lock_init(&trans_pcie->reg_lock);
J
Johannes Berg 已提交
2541
	spin_lock_init(&trans_pcie->ref_lock);
2542
	mutex_init(&trans_pcie->mutex);
2543
	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2544

2545 2546
	ret = pci_enable_device(pdev);
	if (ret)
J
Johannes Berg 已提交
2547 2548
		goto out_no_pci;

2549 2550 2551 2552 2553 2554 2555 2556 2557 2558
	if (!cfg->base_params->pcie_l1_allowed) {
		/*
		 * W/A - seems to solve weird behavior. We need to remove this
		 * if we don't want to stay in L1 all the time. This wastes a
		 * lot of power.
		 */
		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
				       PCIE_LINK_STATE_L1 |
				       PCIE_LINK_STATE_CLKPM);
	}
2559 2560 2561

	pci_set_master(pdev);

2562 2563 2564 2565 2566 2567 2568
	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
	if (!ret)
		ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
	if (ret) {
		ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (!ret)
			ret = pci_set_consistent_dma_mask(pdev,
2569
							  DMA_BIT_MASK(32));
2570
		/* both attempts failed: */
2571
		if (ret) {
2572
			dev_err(&pdev->dev, "No suitable DMA available\n");
2573 2574 2575 2576
			goto out_pci_disable_device;
		}
	}

2577 2578
	ret = pci_request_regions(pdev, DRV_NAME);
	if (ret) {
2579
		dev_err(&pdev->dev, "pci_request_regions failed\n");
2580 2581 2582
		goto out_pci_disable_device;
	}

2583
	trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2584
	if (!trans_pcie->hw_base) {
2585
		dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2586
		ret = -ENODEV;
2587 2588 2589 2590 2591 2592 2593
		goto out_pci_release_regions;
	}

	/* We disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state */
	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);

2594 2595 2596 2597
	trans->dev = &pdev->dev;
	trans_pcie->pci_dev = pdev;
	iwl_disable_interrupts(trans);

2598 2599 2600
	ret = pci_enable_msi(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
2601 2602 2603 2604 2605 2606 2607
		/* enable rfkill interrupt: hw bug w/a */
		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
		}
	}
2608

2609
	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2610 2611 2612 2613 2614 2615
	/*
	 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
	 * changed, and now the revision step also includes bit 0-1 (no more
	 * "dash" value). To keep hw_rev backwards compatible - we'll store it
	 * in the old format.
	 */
2616 2617 2618
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
		unsigned long flags;

2619
		trans->hw_rev = (trans->hw_rev & 0xfff0) |
2620
				(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2621

2622 2623 2624 2625 2626 2627
		ret = iwl_pcie_prepare_card_hw(trans);
		if (ret) {
			IWL_WARN(trans, "Exit HW not ready\n");
			goto out_pci_disable_msi;
		}

2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647
		/*
		 * in-order to recognize C step driver should read chip version
		 * id located at the AUX bus MISC address space.
		 */
		iwl_set_bit(trans, CSR_GP_CNTRL,
			    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
		udelay(2);

		ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
				   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
				   25000);
		if (ret < 0) {
			IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
			goto out_pci_disable_msi;
		}

		if (iwl_trans_grab_nic_access(trans, false, &flags)) {
			u32 hw_step;

2648
			hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2649
			hw_step |= ENABLE_WFPM;
2650 2651
			iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
			hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2652 2653 2654 2655 2656 2657 2658 2659
			hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
			if (hw_step == 0x3)
				trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
						(SILICON_C_STEP << 2);
			iwl_trans_release_nic_access(trans, &flags);
		}
	}

E
Emmanuel Grumbach 已提交
2660
	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2661 2662
	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2663

2664
	/* Initialize the wait queue for commands */
2665
	init_waitqueue_head(&trans_pcie->wait_command_queue);
2666

2667 2668
	ret = iwl_pcie_alloc_ict(trans);
	if (ret)
2669
		goto out_pci_disable_msi;
J
Johannes Berg 已提交
2670

2671
	ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2672 2673
				   iwl_pcie_irq_handler,
				   IRQF_SHARED, DRV_NAME, trans);
2674
	if (ret) {
J
Johannes Berg 已提交
2675 2676 2677 2678
		IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
		goto out_free_ict;
	}

2679
	trans_pcie->inta_mask = CSR_INI_SET_MASK;
2680
	trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2681

2682 2683
	return trans;

J
Johannes Berg 已提交
2684 2685
out_free_ict:
	iwl_pcie_free_ict(trans);
2686 2687
out_pci_disable_msi:
	pci_disable_msi(pdev);
2688 2689 2690 2691 2692
out_pci_release_regions:
	pci_release_regions(pdev);
out_pci_disable_device:
	pci_disable_device(pdev);
out_no_pci:
2693
	iwl_trans_free(trans);
2694
	return ERR_PTR(ret);
2695
}