ste-nomadik-stn8815.dtsi 3.9 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
/*
 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
 */
/include/ "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		reg = <0x00000000 0x04000000>,
		    <0x08000000 0x04000000>;
	};

	L2: l2-cache {
		compatible = "arm,l210-cache";
		reg = <0x10210000 0x1000>;
		interrupt-parent = <&vica>;
		interrupts = <30>;
		cache-unified;
		cache-level = <2>;
	};

	mtu0 {
		/* Nomadik system timer */
		reg = <0x101e2000 0x1000>;
		interrupt-parent = <&vica>;
		interrupts = <4>;
	};

	mtu1 {
		/* Secondary timer */
		reg = <0x101e3000 0x1000>;
		interrupt-parent = <&vica>;
		interrupts = <5>;
	};

38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
	gpio0: gpio@101e4000 {
		compatible = "st,nomadik-gpio";
		reg =  <0x101e4000 0x80>;
		interrupt-parent = <&vica>;
		interrupts = <6>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-bank = <0>;
	};

	gpio1: gpio@101e5000 {
		compatible = "st,nomadik-gpio";
		reg =  <0x101e5000 0x80>;
		interrupt-parent = <&vica>;
		interrupts = <7>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-bank = <1>;
	};

	gpio2: gpio@101e6000 {
		compatible = "st,nomadik-gpio";
		reg =  <0x101e6000 0x80>;
		interrupt-parent = <&vica>;
		interrupts = <8>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-bank = <2>;
	};

	gpio3: gpio@101e7000 {
		compatible = "st,nomadik-gpio";
		reg =  <0x101e7000 0x80>;
		interrupt-parent = <&vica>;
		interrupts = <9>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-bank = <3>;
	};

	pinctrl {
		compatible = "stericsson,nmk-pinctrl-stn8815";
	};

L
Linus Walleij 已提交
90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
	/* A NAND flash of 128 MiB */
	fsmc: flash@40000000 {
		compatible = "stericsson,fsmc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x10100000 0x1000>,	/* FSMC Register*/
			<0x40000000 0x2000>,	/* NAND Base DATA */
			<0x41000000 0x2000>,	/* NAND Base ADDR */
			<0x40800000 0x2000>;	/* NAND Base CMD */
		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
		status = "okay";

		partition@0 {
		label = "X-Loader(NAND)";
			reg = <0x0 0x40000>;
		};
		partition@40000 {
			label = "MemInit(NAND)";
			reg = <0x40000 0x40000>;
		};
		partition@80000 {
			label = "BootLoader(NAND)";
			reg = <0x80000 0x200000>;
		};
		partition@280000 {
			label = "Kernel zImage(NAND)";
			reg = <0x280000 0x300000>;
		};
		partition@580000 {
			label = "Root Filesystem(NAND)";
			reg = <0x580000 0x1600000>;
		};
		partition@1b80000 {
			label = "User Filesystem(NAND)";
			reg = <0x1b80000 0x6480000>;
		};
	};

128 129 130 131 132 133 134 135 136 137 138 139
	external-bus@34000000 {
		compatible = "simple-bus";
		reg = <0x34000000 0x1000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x34000000 0x1000000>;
		ethernet@300 {
			compatible = "smsc,lan91c111";
			reg = <0x300 0x0fd00>;
		};
	};

140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
	amba {
		compatible = "arm,amba-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vica: intc@0x10140000 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10140000 0x20>;
		};

		vicb: intc@0x10140020 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10140020 0x20>;
		};

		uart0: uart@101fd000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101fd000 0x1000>;
			interrupt-parent = <&vica>;
			interrupts = <12>;
		};

		uart1: uart@101fb000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101fb000 0x1000>;
			interrupt-parent = <&vica>;
			interrupts = <17>;
		};

		uart2: uart@101f2000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f2000 0x1000>;
			interrupt-parent = <&vica>;
			interrupts = <28>;
			status = "disabled";
		};
181 182 183 184 185 186 187 188 189 190 191 192

		rng: rng@101b0000 {
			compatible = "arm,primecell";
			reg = <0x101b0000 0x1000>;
		};

		rtc: rtc@101e8000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x101e8000 0x1000>;
			interrupt-parent = <&vica>;
			interrupts = <10>;
		};
193 194
	};
};